sb1.md revision 169689
1169689Skan;; 2169689Skan;; DFA-based pipeline description for Broadcom SB-1 3169689Skan;; 4169689Skan 5169689Skan;; The Broadcom SB-1 core is 4-way superscalar, in-order. It has 2 load/store 6169689Skan;; pipes (one of which can support some ALU operations), 2 alu pipes, 2 FP 7169689Skan;; pipes, and 1 MDMX pipes. It can issue 2 ls insns and 2 exe/fpu/mdmx insns 8169689Skan;; each cycle. 9169689Skan 10169689Skan;; We model the 4-way issue by ordering unit choices. The possible choices are 11169689Skan;; {ex1,fp1}|{ex0,fp0}|ls1|ls0. Instructions issue to the first eligible unit 12169689Skan;; in the list in most cases. Non-indexed load/stores issue to ls0 first. 13169689Skan;; simple alu operations issue to ls1 if it is still available, and their 14169689Skan;; operands are ready (no co-issue with loads), otherwise to the first 15169689Skan;; available ex unit. 16169689Skan 17169689Skan;; When exceptions are enabled, can only issue FP insns to fp1. This is 18169689Skan;; to ensure that instructions complete in order. The -mfp-exceptions option 19169689Skan;; can be used to specify whether the system has FP exceptions enabled or not. 20169689Skan 21169689Skan;; In 32-bit mode, dependent FP can't co-issue with load, and only one FP exe 22169689Skan;; insn can issue per cycle (fp1). 23169689Skan 24169689Skan;; The A1 MDMX pipe is separate from the FP pipes, but uses the same register 25169689Skan;; file. As a result, once an MDMX insn is issued, no FP insns can be issued 26169689Skan;; for 3 cycles. When an FP insn is issued, no MDMX insn can be issued for 27169689Skan;; 5 cycles. This is currently not handled because there is no MDMX insn 28169689Skan;; support as yet. 29169689Skan 30169689Skan;; 31169689Skan;; We use two automata. sb1_cpu_div is for the integer divides, which are 32169689Skan;; not pipelined. sb1_cpu is for everything else. 33169689Skan;; 34169689Skan(define_automaton "sb1_cpu, sb1_cpu_div") 35169689Skan 36169689Skan;; Load/store function units. 37169689Skan(define_cpu_unit "sb1_ls0" "sb1_cpu") 38169689Skan(define_cpu_unit "sb1_ls1" "sb1_cpu") 39169689Skan 40169689Skan;; CPU function units. 41169689Skan(define_cpu_unit "sb1_ex0" "sb1_cpu") 42169689Skan(define_cpu_unit "sb1_ex1" "sb1_cpu") 43169689Skan 44169689Skan;; The divide unit is not pipelined, and blocks hi/lo reads and writes. 45169689Skan(define_cpu_unit "sb1_div" "sb1_cpu_div") 46169689Skan;; DMULT block any multiply from issuing in the next cycle. 47169689Skan(define_cpu_unit "sb1_mul" "sb1_cpu") 48169689Skan 49169689Skan;; Floating-point units. 50169689Skan(define_cpu_unit "sb1_fp0" "sb1_cpu") 51169689Skan(define_cpu_unit "sb1_fp1" "sb1_cpu") 52169689Skan 53169689Skan;; Can only issue to one of the ex and fp pipes at a time. 54169689Skan(exclusion_set "sb1_ex0" "sb1_fp0") 55169689Skan(exclusion_set "sb1_ex1" "sb1_fp1") 56169689Skan 57169689Skan;; Define an SB-1 specific attribute to simplify some FP descriptions. 58169689Skan;; We can use 2 FP pipes only if we have 64-bit FP code, and exceptions are 59169689Skan;; disabled. 60169689Skan 61169689Skan(define_attr "sb1_fp_pipes" "one,two" 62169689Skan (cond [(and (ne (symbol_ref "TARGET_FLOAT64") (const_int 0)) 63169689Skan (eq (symbol_ref "TARGET_FP_EXCEPTIONS") (const_int 0))) 64169689Skan (const_string "two")] 65169689Skan (const_string "one"))) 66169689Skan 67169689Skan;; Define reservations for common combinations. 68169689Skan 69169689Skan;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats, 70169689Skan;; effectively re-issuing the operation every 4 cycles. This means that we 71169689Skan;; can have at most 4 long-cycle operations per pipe. 72169689Skan 73169689Skan;; ??? The fdiv operations should be e.g. 74169689Skan;; sb1_fp1_4cycles*7" | "sb1_fp0_4cycle*7 75169689Skan;; but the DFA is too large when we do that. Perhaps have to use scheduler 76169689Skan;; hooks here. 77169689Skan 78169689Skan;; ??? Try limiting scheduler to 2 long latency operations, and see if this 79169689Skan;; results in a usable DFA, and whether it helps code performance. 80169689Skan 81169689Skan;;(define_reservation "sb1_fp0_4cycles" "sb1_fp0, nothing*3") 82169689Skan;;(define_reservation "sb1_fp1_4cycles" "sb1_fp1, nothing*3") 83169689Skan 84169689Skan;; 85169689Skan;; The ordering of the instruction-execution-path/resource-usage 86169689Skan;; descriptions (also known as reservation RTL) is roughly ordered 87169689Skan;; based on the define attribute RTL for the "type" classification. 88169689Skan;; When modifying, remember that the first test that matches is the 89169689Skan;; reservation used! 90169689Skan;; 91169689Skan 92169689Skan(define_insn_reservation "ir_sb1_unknown" 1 93169689Skan (and (eq_attr "cpu" "sb1,sb1a") 94169689Skan (eq_attr "type" "unknown,multi")) 95169689Skan "sb1_ls0+sb1_ls1+sb1_ex0+sb1_ex1+sb1_fp0+sb1_fp1") 96169689Skan 97169689Skan;; predicted taken branch causes 2 cycle ifetch bubble. predicted not 98169689Skan;; taken branch causes 0 cycle ifetch bubble. mispredicted branch causes 8 99169689Skan;; cycle ifetch bubble. We assume all branches predicted not taken. 100169689Skan 101169689Skan;; ??? This assumption that branches are predicated not taken should be 102169689Skan;; investigated. Maybe using 2 here will give better results. 103169689Skan 104169689Skan(define_insn_reservation "ir_sb1_branch" 0 105169689Skan (and (eq_attr "cpu" "sb1,sb1a") 106169689Skan (eq_attr "type" "branch,jump,call")) 107169689Skan "sb1_ex0") 108169689Skan 109169689Skan;; ??? This is 1 cycle for ldl/ldr to ldl/ldr when they use the same data 110169689Skan;; register as destination. 111169689Skan 112169689Skan;; ??? SB-1 can co-issue a load with a dependent arith insn if it executes on 113169689Skan;; an EX unit. Can not co-issue if the dependent insn executes on an LS unit. 114169689Skan;; SB-1A can always co-issue here. 115169689Skan 116169689Skan;; A load normally has a latency of zero cycles. In some cases, dependent 117169689Skan;; insns can be issued in the same cycle. However, a value of 1 gives 118169689Skan;; better performance in empirical testing. 119169689Skan 120169689Skan(define_insn_reservation "ir_sb1_load" 1 121169689Skan (and (eq_attr "cpu" "sb1") 122169689Skan (eq_attr "type" "load,prefetch")) 123169689Skan "sb1_ls0 | sb1_ls1") 124169689Skan 125169689Skan(define_insn_reservation "ir_sb1a_load" 0 126169689Skan (and (eq_attr "cpu" "sb1a") 127169689Skan (eq_attr "type" "load,prefetch")) 128169689Skan "sb1_ls0 | sb1_ls1") 129169689Skan 130169689Skan;; Can not co-issue fpload with fp exe when in 32-bit mode. 131169689Skan 132169689Skan(define_insn_reservation "ir_sb1_fpload" 0 133169689Skan (and (eq_attr "cpu" "sb1,sb1a") 134169689Skan (and (eq_attr "type" "fpload") 135169689Skan (ne (symbol_ref "TARGET_FLOAT64") 136169689Skan (const_int 0)))) 137169689Skan "sb1_ls0 | sb1_ls1") 138169689Skan 139169689Skan(define_insn_reservation "ir_sb1_fpload_32bitfp" 1 140169689Skan (and (eq_attr "cpu" "sb1,sb1a") 141169689Skan (and (eq_attr "type" "fpload") 142169689Skan (eq (symbol_ref "TARGET_FLOAT64") 143169689Skan (const_int 0)))) 144169689Skan "sb1_ls0 | sb1_ls1") 145169689Skan 146169689Skan;; Indexed loads can only execute on LS1 pipe. 147169689Skan 148169689Skan(define_insn_reservation "ir_sb1_fpidxload" 0 149169689Skan (and (eq_attr "cpu" "sb1,sb1a") 150169689Skan (and (eq_attr "type" "fpidxload") 151169689Skan (ne (symbol_ref "TARGET_FLOAT64") 152169689Skan (const_int 0)))) 153169689Skan "sb1_ls1") 154169689Skan 155169689Skan(define_insn_reservation "ir_sb1_fpidxload_32bitfp" 1 156169689Skan (and (eq_attr "cpu" "sb1,sb1a") 157169689Skan (and (eq_attr "type" "fpidxload") 158169689Skan (eq (symbol_ref "TARGET_FLOAT64") 159169689Skan (const_int 0)))) 160169689Skan "sb1_ls1") 161169689Skan 162169689Skan;; prefx can only execute on the ls1 pipe. 163169689Skan 164169689Skan(define_insn_reservation "ir_sb1_prefetchx" 0 165169689Skan (and (eq_attr "cpu" "sb1,sb1a") 166169689Skan (eq_attr "type" "prefetchx")) 167169689Skan "sb1_ls1") 168169689Skan 169169689Skan;; ??? There is a 4.5 cycle latency if a store is followed by a load, and 170169689Skan;; there is a RAW dependency. 171169689Skan 172169689Skan(define_insn_reservation "ir_sb1_store" 1 173169689Skan (and (eq_attr "cpu" "sb1,sb1a") 174169689Skan (eq_attr "type" "store")) 175169689Skan "sb1_ls0+sb1_ex1 | sb1_ls0+sb1_ex0 | sb1_ls1+sb1_ex1 | sb1_ls1+sb1_ex0") 176169689Skan 177169689Skan(define_insn_reservation "ir_sb1_fpstore" 1 178169689Skan (and (eq_attr "cpu" "sb1,sb1a") 179169689Skan (eq_attr "type" "fpstore")) 180169689Skan "sb1_ls0+sb1_fp1 | sb1_ls0+sb1_fp0 | sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 181169689Skan 182169689Skan;; Indexed stores can only execute on LS1 pipe. 183169689Skan 184169689Skan(define_insn_reservation "ir_sb1_fpidxstore" 1 185169689Skan (and (eq_attr "cpu" "sb1,sb1a") 186169689Skan (eq_attr "type" "fpidxstore")) 187169689Skan "sb1_ls1+sb1_fp1 | sb1_ls1+sb1_fp0") 188169689Skan 189169689Skan;; Load latencies are 3 cycles for one load to another load or store (address 190169689Skan;; only). This is 0 cycles for one load to a store using it as the data 191169689Skan;; written. 192169689Skan 193169689Skan;; This assumes that if a load is dependent on a previous insn, then it must 194169689Skan;; be an address dependence. 195169689Skan 196169689Skan(define_bypass 3 197169689Skan "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 198169689Skan ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" 199169689Skan "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 200169689Skan ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 201169689Skan 202169689Skan(define_bypass 3 203169689Skan "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 204169689Skan ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp" 205169689Skan "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 206169689Skan "mips_store_data_bypass_p") 207169689Skan 208169689Skan;; On SB-1, simple alu instructions can execute on the LS1 unit. 209169689Skan 210169689Skan;; ??? A simple alu insn issued on an LS unit has 0 cycle latency to an EX 211169689Skan;; insn, to a store (for data), and to an xfer insn. It has 1 cycle latency to 212169689Skan;; another LS insn (excluding store data). A simple alu insn issued on an EX 213169689Skan;; unit has a latency of 5 cycles when the results goes to a LS unit (excluding 214169689Skan;; store data), otherwise a latency of 1 cycle. 215169689Skan 216169689Skan;; ??? We cannot handle latencies properly for simple alu instructions 217169689Skan;; within the DFA pipeline model. Latencies can be defined only from one 218169689Skan;; insn reservation to another. We can't make them depend on which function 219169689Skan;; unit was used. This isn't a DFA flaw. There is a conflict here, as we 220169689Skan;; need to know the latency before we can determine which unit will be 221169689Skan;; available, but we need to know which unit it is issued to before we can 222169689Skan;; compute the latency. Perhaps this can be handled via scheduler hooks. 223169689Skan;; This needs to be investigated. 224169689Skan 225169689Skan;; ??? Optimal scheduling taking the LS units into account seems to require 226169689Skan;; a pre-scheduling pass. We need to determine which instructions feed results 227169689Skan;; into store/load addresses, and thus benefit most from being issued to the 228169689Skan;; LS unit. Also, we need to prune the list to ensure we don't overschedule 229169689Skan;; insns to the LS unit, and that we don't conflict with insns that need LS1 230169689Skan;; such as indexed loads. We then need to emit nops to ensure that simple 231169689Skan;; alu instructions that are not supposed to be scheduled to LS1 don't 232169689Skan;; accidentally end up there because LS1 is free when they are issued. This 233169689Skan;; will be a lot of work, and it isn't clear how useful it will be. 234169689Skan 235169689Skan;; Empirical testing shows that 2 gives the best result. 236169689Skan 237169689Skan(define_insn_reservation "ir_sb1_simple_alu" 2 238169689Skan (and (eq_attr "cpu" "sb1") 239169689Skan (eq_attr "type" "const,arith")) 240169689Skan "sb1_ls1 | sb1_ex1 | sb1_ex0") 241169689Skan 242169689Skan;; On SB-1A, simple alu instructions can not execute on the LS1 unit, and we 243169689Skan;; have none of the above problems. 244169689Skan 245169689Skan(define_insn_reservation "ir_sb1a_simple_alu" 1 246169689Skan (and (eq_attr "cpu" "sb1a") 247169689Skan (eq_attr "type" "const,arith")) 248169689Skan "sb1_ex1 | sb1_ex0") 249169689Skan 250169689Skan;; ??? condmove also includes some FP instructions that execute on the FP 251169689Skan;; units. This needs to be clarified. 252169689Skan 253169689Skan(define_insn_reservation "ir_sb1_alu" 1 254169689Skan (and (eq_attr "cpu" "sb1,sb1a") 255169689Skan (eq_attr "type" "condmove,nop,shift")) 256169689Skan "sb1_ex1 | sb1_ex0") 257169689Skan 258169689Skan;; These are type arith/darith that only execute on the EX0 unit. 259169689Skan 260169689Skan(define_insn_reservation "ir_sb1_alu_0" 1 261169689Skan (and (eq_attr "cpu" "sb1,sb1a") 262169689Skan (eq_attr "type" "slt,clz,trap")) 263169689Skan "sb1_ex0") 264169689Skan 265169689Skan;; An alu insn issued on an EX unit has a latency of 5 cycles when the 266169689Skan;; result goes to a LS unit (excluding store data). 267169689Skan 268169689Skan;; This assumes that if a load is dependent on a previous insn, then it must 269169689Skan;; be an address dependence. 270169689Skan 271169689Skan(define_bypass 5 272169689Skan "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 273169689Skan "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 274169689Skan ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 275169689Skan 276169689Skan(define_bypass 5 277169689Skan "ir_sb1a_simple_alu,ir_sb1_alu,ir_sb1_alu_0,ir_sb1_mfhi,ir_sb1_mflo" 278169689Skan "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 279169689Skan "mips_store_data_bypass_p") 280169689Skan 281169689Skan;; mf{hi,lo} is 1 cycle. 282169689Skan 283169689Skan(define_insn_reservation "ir_sb1_mfhi" 1 284169689Skan (and (eq_attr "cpu" "sb1,sb1a") 285169689Skan (and (eq_attr "type" "mfhilo") 286169689Skan (not (match_operand 1 "lo_operand")))) 287169689Skan "sb1_ex1") 288169689Skan 289169689Skan(define_insn_reservation "ir_sb1_mflo" 1 290169689Skan (and (eq_attr "cpu" "sb1,sb1a") 291169689Skan (and (eq_attr "type" "mfhilo") 292169689Skan (match_operand 1 "lo_operand"))) 293169689Skan "sb1_ex1") 294169689Skan 295169689Skan;; mt{hi,lo} to mul/div is 4 cycles. 296169689Skan 297169689Skan(define_insn_reservation "ir_sb1_mthilo" 4 298169689Skan (and (eq_attr "cpu" "sb1,sb1a") 299169689Skan (eq_attr "type" "mthilo")) 300169689Skan "sb1_ex1") 301169689Skan 302169689Skan;; mt{hi,lo} to mf{hi,lo} is 3 cycles. 303169689Skan 304169689Skan(define_bypass 3 "ir_sb1_mthilo" "ir_sb1_mfhi,ir_sb1_mflo") 305169689Skan 306169689Skan;; multiply latency to an EX operation is 3 cycles. 307169689Skan 308169689Skan;; ??? Should check whether we need to make multiply conflict with moves 309169689Skan;; to/from hilo registers. 310169689Skan 311169689Skan(define_insn_reservation "ir_sb1_mulsi" 3 312169689Skan (and (eq_attr "cpu" "sb1,sb1a") 313169689Skan (and (eq_attr "type" "imul,imul3,imadd") 314169689Skan (eq_attr "mode" "SI"))) 315169689Skan "sb1_ex1+sb1_mul") 316169689Skan 317169689Skan;; muldi to mfhi is 4 cycles. 318169689Skan;; Blocks any other multiply insn issue for 1 cycle. 319169689Skan 320169689Skan(define_insn_reservation "ir_sb1_muldi" 4 321169689Skan (and (eq_attr "cpu" "sb1,sb1a") 322169689Skan (and (eq_attr "type" "imul,imul3") 323169689Skan (eq_attr "mode" "DI"))) 324169689Skan "sb1_ex1+sb1_mul, sb1_mul") 325169689Skan 326169689Skan;; muldi to mflo is 3 cycles. 327169689Skan 328169689Skan(define_bypass 3 "ir_sb1_muldi" "ir_sb1_mflo") 329169689Skan 330169689Skan;; mul latency is 7 cycles if the result is used by any LS insn. 331169689Skan 332169689Skan;; This assumes that if a load is dependent on a previous insn, then it must 333169689Skan;; be an address dependence. 334169689Skan 335169689Skan(define_bypass 7 336169689Skan "ir_sb1_mulsi,ir_sb1_muldi" 337169689Skan "ir_sb1_load,ir_sb1a_load,ir_sb1_fpload,ir_sb1_fpload_32bitfp, 338169689Skan ir_sb1_fpidxload,ir_sb1_fpidxload_32bitfp,ir_sb1_prefetchx") 339169689Skan 340169689Skan(define_bypass 7 341169689Skan "ir_sb1_mulsi,ir_sb1_muldi" 342169689Skan "ir_sb1_store,ir_sb1_fpstore,ir_sb1_fpidxstore" 343169689Skan "mips_store_data_bypass_p") 344169689Skan 345169689Skan;; The divide unit is not pipelined. Divide busy is asserted in the 4th 346169689Skan;; cycle, and then deasserted on the latency cycle. So only one divide at 347169689Skan;; a time, but the first/last 4 cycles can overlap. 348169689Skan 349169689Skan;; ??? All divides block writes to hi/lo regs. hi/lo regs are written 4 cycles 350169689Skan;; after the latency cycle for divides (e.g. 40/72). dmult writes lo in 351169689Skan;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7. 352169689Skan;; Default for output dependencies is the difference in latencies, which is 353169689Skan;; only 1 cycle off here, e.g. div to mtlo stalls for 32 cycles, but should 354169689Skan;; stall for 33 cycles. This does not seem significant enough to worry about. 355169689Skan 356169689Skan(define_insn_reservation "ir_sb1_divsi" 36 357169689Skan (and (eq_attr "cpu" "sb1,sb1a") 358169689Skan (and (eq_attr "type" "idiv") 359169689Skan (eq_attr "mode" "SI"))) 360169689Skan "sb1_ex1, nothing*3, sb1_div*32") 361169689Skan 362169689Skan(define_insn_reservation "ir_sb1_divdi" 68 363169689Skan (and (eq_attr "cpu" "sb1,sb1a") 364169689Skan (and (eq_attr "type" "idiv") 365169689Skan (eq_attr "mode" "DI"))) 366169689Skan "sb1_ex1, nothing*3, sb1_div*64") 367169689Skan 368169689Skan(define_insn_reservation "ir_sb1_fpu_2pipes" 4 369169689Skan (and (eq_attr "cpu" "sb1,sb1a") 370169689Skan (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 371169689Skan (eq_attr "sb1_fp_pipes" "two"))) 372169689Skan "sb1_fp1 | sb1_fp0") 373169689Skan 374169689Skan(define_insn_reservation "ir_sb1_fpu_1pipe" 4 375169689Skan (and (eq_attr "cpu" "sb1,sb1a") 376169689Skan (and (eq_attr "type" "fmove,fadd,fmul,fabs,fneg,fcvt,frdiv1,frsqrt1") 377169689Skan (eq_attr "sb1_fp_pipes" "one"))) 378169689Skan "sb1_fp1") 379169689Skan 380169689Skan(define_insn_reservation "ir_sb1_fpu_step2_2pipes" 8 381169689Skan (and (eq_attr "cpu" "sb1,sb1a") 382169689Skan (and (eq_attr "type" "frdiv2,frsqrt2") 383169689Skan (eq_attr "sb1_fp_pipes" "two"))) 384169689Skan "sb1_fp1 | sb1_fp0") 385169689Skan 386169689Skan(define_insn_reservation "ir_sb1_fpu_step2_1pipe" 8 387169689Skan (and (eq_attr "cpu" "sb1,sb1a") 388169689Skan (and (eq_attr "type" "frdiv2,frsqrt2") 389169689Skan (eq_attr "sb1_fp_pipes" "one"))) 390169689Skan "sb1_fp1") 391169689Skan 392169689Skan;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency 393169689Skan;; otherwise. 394169689Skan 395169689Skan;; ??? Blocks issue of another non-madd/msub after 4 cycles. 396169689Skan 397169689Skan(define_insn_reservation "ir_sb1_fmadd_2pipes" 8 398169689Skan (and (eq_attr "cpu" "sb1,sb1a") 399169689Skan (and (eq_attr "type" "fmadd") 400169689Skan (eq_attr "sb1_fp_pipes" "two"))) 401169689Skan "sb1_fp1 | sb1_fp0") 402169689Skan 403169689Skan(define_insn_reservation "ir_sb1_fmadd_1pipe" 8 404169689Skan (and (eq_attr "cpu" "sb1,sb1a") 405169689Skan (and (eq_attr "type" "fmadd") 406169689Skan (eq_attr "sb1_fp_pipes" "one"))) 407169689Skan "sb1_fp1") 408169689Skan 409169689Skan(define_insn_reservation "ir_sb1_fcmp" 4 410169689Skan (and (eq_attr "cpu" "sb1,sb1a") 411169689Skan (eq_attr "type" "fcmp")) 412169689Skan "sb1_fp1") 413169689Skan 414169689Skan;; mtc1 latency 5 cycles. 415169689Skan 416169689Skan(define_insn_reservation "ir_sb1_mtxfer" 5 417169689Skan (and (eq_attr "cpu" "sb1,sb1a") 418169689Skan (and (eq_attr "type" "xfer") 419169689Skan (match_operand 0 "fpr_operand"))) 420169689Skan "sb1_fp0") 421169689Skan 422169689Skan;; mfc1 latency 1 cycle. 423169689Skan 424169689Skan(define_insn_reservation "ir_sb1_mfxfer" 1 425169689Skan (and (eq_attr "cpu" "sb1,sb1a") 426169689Skan (and (eq_attr "type" "xfer") 427169689Skan (not (match_operand 0 "fpr_operand")))) 428169689Skan "sb1_fp0") 429169689Skan 430169689Skan;; ??? Can deliver at most 1 result per every 6 cycles because of issue 431169689Skan;; restrictions. 432169689Skan 433169689Skan(define_insn_reservation "ir_sb1_divsf_2pipes" 24 434169689Skan (and (eq_attr "cpu" "sb1,sb1a") 435169689Skan (and (eq_attr "type" "fdiv") 436169689Skan (and (eq_attr "mode" "SF") 437169689Skan (eq_attr "sb1_fp_pipes" "two")))) 438169689Skan "sb1_fp1 | sb1_fp0") 439169689Skan 440169689Skan(define_insn_reservation "ir_sb1_divsf_1pipe" 24 441169689Skan (and (eq_attr "cpu" "sb1,sb1a") 442169689Skan (and (eq_attr "type" "fdiv") 443169689Skan (and (eq_attr "mode" "SF") 444169689Skan (eq_attr "sb1_fp_pipes" "one")))) 445169689Skan "sb1_fp1") 446169689Skan 447169689Skan;; ??? Can deliver at most 1 result per every 8 cycles because of issue 448169689Skan;; restrictions. 449169689Skan 450169689Skan(define_insn_reservation "ir_sb1_divdf_2pipes" 32 451169689Skan (and (eq_attr "cpu" "sb1,sb1a") 452169689Skan (and (eq_attr "type" "fdiv") 453169689Skan (and (eq_attr "mode" "DF") 454169689Skan (eq_attr "sb1_fp_pipes" "two")))) 455169689Skan "sb1_fp1 | sb1_fp0") 456169689Skan 457169689Skan(define_insn_reservation "ir_sb1_divdf_1pipe" 32 458169689Skan (and (eq_attr "cpu" "sb1,sb1a") 459169689Skan (and (eq_attr "type" "fdiv") 460169689Skan (and (eq_attr "mode" "DF") 461169689Skan (eq_attr "sb1_fp_pipes" "one")))) 462169689Skan "sb1_fp1") 463169689Skan 464169689Skan;; ??? Can deliver at most 1 result per every 3 cycles because of issue 465169689Skan;; restrictions. 466169689Skan 467169689Skan(define_insn_reservation "ir_sb1_recipsf_2pipes" 12 468169689Skan (and (eq_attr "cpu" "sb1,sb1a") 469169689Skan (and (eq_attr "type" "frdiv") 470169689Skan (and (eq_attr "mode" "SF") 471169689Skan (eq_attr "sb1_fp_pipes" "two")))) 472169689Skan "sb1_fp1 | sb1_fp0") 473169689Skan 474169689Skan(define_insn_reservation "ir_sb1_recipsf_1pipe" 12 475169689Skan (and (eq_attr "cpu" "sb1,sb1a") 476169689Skan (and (eq_attr "type" "frdiv") 477169689Skan (and (eq_attr "mode" "SF") 478169689Skan (eq_attr "sb1_fp_pipes" "one")))) 479169689Skan "sb1_fp1") 480169689Skan 481169689Skan;; ??? Can deliver at most 1 result per every 5 cycles because of issue 482169689Skan;; restrictions. 483169689Skan 484169689Skan(define_insn_reservation "ir_sb1_recipdf_2pipes" 20 485169689Skan (and (eq_attr "cpu" "sb1,sb1a") 486169689Skan (and (eq_attr "type" "frdiv") 487169689Skan (and (eq_attr "mode" "DF") 488169689Skan (eq_attr "sb1_fp_pipes" "two")))) 489169689Skan "sb1_fp1 | sb1_fp0") 490169689Skan 491169689Skan(define_insn_reservation "ir_sb1_recipdf_1pipe" 20 492169689Skan (and (eq_attr "cpu" "sb1,sb1a") 493169689Skan (and (eq_attr "type" "frdiv") 494169689Skan (and (eq_attr "mode" "DF") 495169689Skan (eq_attr "sb1_fp_pipes" "one")))) 496169689Skan "sb1_fp1") 497169689Skan 498169689Skan;; ??? Can deliver at most 1 result per every 7 cycles because of issue 499169689Skan;; restrictions. 500169689Skan 501169689Skan(define_insn_reservation "ir_sb1_sqrtsf_2pipes" 28 502169689Skan (and (eq_attr "cpu" "sb1,sb1a") 503169689Skan (and (eq_attr "type" "fsqrt") 504169689Skan (and (eq_attr "mode" "SF") 505169689Skan (eq_attr "sb1_fp_pipes" "two")))) 506169689Skan "sb1_fp1 | sb1_fp0") 507169689Skan 508169689Skan(define_insn_reservation "ir_sb1_sqrtsf_1pipe" 28 509169689Skan (and (eq_attr "cpu" "sb1,sb1a") 510169689Skan (and (eq_attr "type" "fsqrt") 511169689Skan (and (eq_attr "mode" "SF") 512169689Skan (eq_attr "sb1_fp_pipes" "one")))) 513169689Skan "sb1_fp1") 514169689Skan 515169689Skan;; ??? Can deliver at most 1 result per every 10 cycles because of issue 516169689Skan;; restrictions. 517169689Skan 518169689Skan(define_insn_reservation "ir_sb1_sqrtdf_2pipes" 40 519169689Skan (and (eq_attr "cpu" "sb1,sb1a") 520169689Skan (and (eq_attr "type" "fsqrt") 521169689Skan (and (eq_attr "mode" "DF") 522169689Skan (eq_attr "sb1_fp_pipes" "two")))) 523169689Skan "sb1_fp1 | sb1_fp0") 524169689Skan 525169689Skan(define_insn_reservation "ir_sb1_sqrtdf_1pipe" 40 526169689Skan (and (eq_attr "cpu" "sb1,sb1a") 527169689Skan (and (eq_attr "type" "fsqrt") 528169689Skan (and (eq_attr "mode" "DF") 529169689Skan (eq_attr "sb1_fp_pipes" "one")))) 530169689Skan "sb1_fp1") 531169689Skan 532169689Skan;; ??? Can deliver at most 1 result per every 4 cycles because of issue 533169689Skan;; restrictions. 534169689Skan 535169689Skan(define_insn_reservation "ir_sb1_rsqrtsf_2pipes" 16 536169689Skan (and (eq_attr "cpu" "sb1,sb1a") 537169689Skan (and (eq_attr "type" "frsqrt") 538169689Skan (and (eq_attr "mode" "SF") 539169689Skan (eq_attr "sb1_fp_pipes" "two")))) 540169689Skan "sb1_fp1 | sb1_fp0") 541169689Skan 542169689Skan(define_insn_reservation "ir_sb1_rsqrtsf_1pipe" 16 543169689Skan (and (eq_attr "cpu" "sb1,sb1a") 544169689Skan (and (eq_attr "type" "frsqrt") 545169689Skan (and (eq_attr "mode" "SF") 546169689Skan (eq_attr "sb1_fp_pipes" "one")))) 547169689Skan "sb1_fp1") 548169689Skan 549169689Skan;; ??? Can deliver at most 1 result per every 7 cycles because of issue 550169689Skan;; restrictions. 551169689Skan 552169689Skan(define_insn_reservation "ir_sb1_rsqrtdf_2pipes" 28 553169689Skan (and (eq_attr "cpu" "sb1,sb1a") 554169689Skan (and (eq_attr "type" "frsqrt") 555169689Skan (and (eq_attr "mode" "DF") 556169689Skan (eq_attr "sb1_fp_pipes" "two")))) 557169689Skan "sb1_fp1 | sb1_fp0") 558169689Skan 559169689Skan(define_insn_reservation "ir_sb1_rsqrtdf_1pipe" 28 560169689Skan (and (eq_attr "cpu" "sb1,sb1a") 561169689Skan (and (eq_attr "type" "frsqrt") 562169689Skan (and (eq_attr "mode" "DF") 563169689Skan (eq_attr "sb1_fp_pipes" "one")))) 564169689Skan "sb1_fp1") 565