1169689Skan;; MIPS Paired-Single Floating and MIPS-3D Instructions. 2169689Skan;; Copyright (C) 2004 Free Software Foundation, Inc. 3169689Skan;; 4169689Skan;; This file is part of GCC. 5169689Skan;; 6169689Skan;; GCC is free software; you can redistribute it and/or modify 7169689Skan;; it under the terms of the GNU General Public License as published by 8169689Skan;; the Free Software Foundation; either version 2, or (at your option) 9169689Skan;; any later version. 10169689Skan;; 11169689Skan;; GCC is distributed in the hope that it will be useful, 12169689Skan;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13169689Skan;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14169689Skan;; GNU General Public License for more details. 15169689Skan;; 16169689Skan;; You should have received a copy of the GNU General Public License 17169689Skan;; along with GCC; see the file COPYING. If not, write to 18169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19169689Skan;; Boston, MA 02110-1301, USA. 20169689Skan 21169689Skan(define_insn "*movcc_v2sf_<mode>" 22169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f,f") 23169689Skan (if_then_else:V2SF 24169689Skan (match_operator:GPR 4 "equality_operator" 25169689Skan [(match_operand:GPR 1 "register_operand" "d,d") 26169689Skan (const_int 0)]) 27169689Skan (match_operand:V2SF 2 "register_operand" "f,0") 28169689Skan (match_operand:V2SF 3 "register_operand" "0,f")))] 29169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 30169689Skan "@ 31169689Skan mov%T4.ps\t%0,%2,%1 32169689Skan mov%t4.ps\t%0,%3,%1" 33169689Skan [(set_attr "type" "condmove") 34169689Skan (set_attr "mode" "SF")]) 35169689Skan 36169689Skan(define_insn "mips_cond_move_tf_ps" 37169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f,f") 38169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f,0") 39169689Skan (match_operand:V2SF 2 "register_operand" "0,f") 40169689Skan (match_operand:CCV2 3 "register_operand" "z,z")] 41169689Skan UNSPEC_MOVE_TF_PS))] 42169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 43169689Skan "@ 44169689Skan movt.ps\t%0,%1,%3 45169689Skan movf.ps\t%0,%2,%3" 46169689Skan [(set_attr "type" "condmove") 47169689Skan (set_attr "mode" "SF")]) 48169689Skan 49169689Skan(define_expand "movv2sfcc" 50169689Skan [(set (match_dup 4) (match_operand 1 "comparison_operator")) 51169689Skan (set (match_operand:V2SF 0 "register_operand") 52169689Skan (if_then_else:V2SF (match_dup 5) 53169689Skan (match_operand:V2SF 2 "register_operand") 54169689Skan (match_operand:V2SF 3 "register_operand")))] 55169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 56169689Skan{ 57169689Skan /* We can only support MOVN.PS and MOVZ.PS. 58169689Skan NOTE: MOVT.PS and MOVF.PS have different semantics from MOVN.PS and 59169689Skan MOVZ.PS. MOVT.PS and MOVF.PS depend on two CC values and move 60169689Skan each item independently. */ 61169689Skan 62169689Skan if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT) 63169689Skan FAIL; 64169689Skan 65169689Skan gen_conditional_move (operands); 66169689Skan DONE; 67169689Skan}) 68169689Skan 69169689Skan; pul.ps - Pair Upper Lower 70169689Skan(define_insn "mips_pul_ps" 71169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 72169689Skan (vec_merge:V2SF 73169689Skan (match_operand:V2SF 1 "register_operand" "f") 74169689Skan (match_operand:V2SF 2 "register_operand" "f") 75169689Skan (const_int 2)))] 76169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 77169689Skan "pul.ps\t%0,%1,%2" 78169689Skan [(set_attr "type" "fmove") 79169689Skan (set_attr "mode" "SF")]) 80169689Skan 81169689Skan; puu.ps - Pair upper upper 82169689Skan(define_insn "mips_puu_ps" 83169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 84169689Skan (vec_merge:V2SF 85169689Skan (match_operand:V2SF 1 "register_operand" "f") 86169689Skan (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") 87169689Skan (parallel [(const_int 1) 88169689Skan (const_int 0)])) 89169689Skan (const_int 2)))] 90169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 91169689Skan "puu.ps\t%0,%1,%2" 92169689Skan [(set_attr "type" "fmove") 93169689Skan (set_attr "mode" "SF")]) 94169689Skan 95169689Skan; pll.ps - Pair Lower Lower 96169689Skan(define_insn "mips_pll_ps" 97169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 98169689Skan (vec_merge:V2SF 99169689Skan (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") 100169689Skan (parallel [(const_int 1) 101169689Skan (const_int 0)])) 102169689Skan (match_operand:V2SF 2 "register_operand" "f") 103169689Skan (const_int 2)))] 104169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 105169689Skan "pll.ps\t%0,%1,%2" 106169689Skan [(set_attr "type" "fmove") 107169689Skan (set_attr "mode" "SF")]) 108169689Skan 109169689Skan; plu.ps - Pair Lower Upper 110169689Skan(define_insn "mips_plu_ps" 111169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 112169689Skan (vec_merge:V2SF 113169689Skan (vec_select:V2SF (match_operand:V2SF 1 "register_operand" "f") 114169689Skan (parallel [(const_int 1) 115169689Skan (const_int 0)])) 116169689Skan (vec_select:V2SF (match_operand:V2SF 2 "register_operand" "f") 117169689Skan (parallel [(const_int 1) 118169689Skan (const_int 0)])) 119169689Skan (const_int 2)))] 120169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 121169689Skan "plu.ps\t%0,%1,%2" 122169689Skan [(set_attr "type" "fmove") 123169689Skan (set_attr "mode" "SF")]) 124169689Skan 125169689Skan; vec_init 126169689Skan(define_expand "vec_initv2sf" 127169689Skan [(match_operand:V2SF 0 "register_operand") 128169689Skan (match_operand:V2SF 1 "")] 129169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 130169689Skan{ 131169689Skan rtx op0 = force_reg (SFmode, XVECEXP (operands[1], 0, 0)); 132169689Skan rtx op1 = force_reg (SFmode, XVECEXP (operands[1], 0, 1)); 133169689Skan emit_insn (gen_vec_initv2sf_internal (operands[0], op0, op1)); 134169689Skan DONE; 135169689Skan}) 136169689Skan 137169689Skan(define_insn "vec_initv2sf_internal" 138169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 139169689Skan (vec_concat:V2SF 140169689Skan (match_operand:SF 1 "register_operand" "f") 141169689Skan (match_operand:SF 2 "register_operand" "f")))] 142169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 143169689Skan{ 144169689Skan if (BYTES_BIG_ENDIAN) 145169689Skan return "cvt.ps.s\t%0,%1,%2"; 146169689Skan else 147169689Skan return "cvt.ps.s\t%0,%2,%1"; 148169689Skan} 149169689Skan [(set_attr "type" "fcvt") 150169689Skan (set_attr "mode" "SF")]) 151169689Skan 152169689Skan;; ??? This is only generated if we perform a vector operation that has to be 153169689Skan;; emulated. There is no other way to get a vector mode bitfield extract 154169689Skan;; currently. 155169689Skan 156169689Skan(define_insn "vec_extractv2sf" 157169689Skan [(set (match_operand:SF 0 "register_operand" "=f") 158169689Skan (vec_select:SF (match_operand:V2SF 1 "register_operand" "f") 159169689Skan (parallel 160169689Skan [(match_operand 2 "const_0_or_1_operand" "")])))] 161169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 162169689Skan{ 163169689Skan if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) 164169689Skan return "cvt.s.pu\t%0,%1"; 165169689Skan else 166169689Skan return "cvt.s.pl\t%0,%1"; 167169689Skan} 168169689Skan [(set_attr "type" "fcvt") 169169689Skan (set_attr "mode" "SF")]) 170169689Skan 171169689Skan;; ??? This is only generated if we disable the vec_init pattern. There is 172169689Skan;; no other way to get a vector mode bitfield store currently. 173169689Skan 174169689Skan(define_expand "vec_setv2sf" 175169689Skan [(match_operand:V2SF 0 "register_operand") 176169689Skan (match_operand:SF 1 "register_operand") 177169689Skan (match_operand 2 "const_0_or_1_operand")] 178169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 179169689Skan{ 180169689Skan rtx temp; 181169689Skan 182169689Skan /* We don't have an insert instruction, so we duplicate the float, and 183169689Skan then use a PUL instruction. */ 184169689Skan temp = gen_reg_rtx (V2SFmode); 185169689Skan emit_insn (gen_mips_cvt_ps_s (temp, operands[1], operands[1])); 186169689Skan if (INTVAL (operands[2]) == !BYTES_BIG_ENDIAN) 187169689Skan emit_insn (gen_mips_pul_ps (operands[0], temp, operands[0])); 188169689Skan else 189169689Skan emit_insn (gen_mips_pul_ps (operands[0], operands[0], temp)); 190169689Skan DONE; 191169689Skan}) 192169689Skan 193169689Skan; cvt.ps.s - Floating Point Convert Pair to Paired Single 194169689Skan(define_expand "mips_cvt_ps_s" 195169689Skan [(match_operand:V2SF 0 "register_operand") 196169689Skan (match_operand:SF 1 "register_operand") 197169689Skan (match_operand:SF 2 "register_operand")] 198169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 199169689Skan{ 200169689Skan if (BYTES_BIG_ENDIAN) 201169689Skan emit_insn (gen_vec_initv2sf_internal (operands[0], operands[1], 202169689Skan operands[2])); 203169689Skan else 204169689Skan emit_insn (gen_vec_initv2sf_internal (operands[0], operands[2], 205169689Skan operands[1])); 206169689Skan DONE; 207169689Skan}) 208169689Skan 209169689Skan; cvt.s.pl - Floating Point Convert Pair Lower to Single Floating Point 210169689Skan(define_expand "mips_cvt_s_pl" 211169689Skan [(set (match_operand:SF 0 "register_operand") 212169689Skan (vec_select:SF (match_operand:V2SF 1 "register_operand") 213169689Skan (parallel [(match_dup 2)])))] 214169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 215169689Skan { operands[2] = GEN_INT (BYTES_BIG_ENDIAN); }) 216169689Skan 217169689Skan; cvt.s.pu - Floating Point Convert Pair Upper to Single Floating Point 218169689Skan(define_expand "mips_cvt_s_pu" 219169689Skan [(set (match_operand:SF 0 "register_operand") 220169689Skan (vec_select:SF (match_operand:V2SF 1 "register_operand") 221169689Skan (parallel [(match_dup 2)])))] 222169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 223169689Skan { operands[2] = GEN_INT (!BYTES_BIG_ENDIAN); }) 224169689Skan 225169689Skan; alnv.ps - Floating Point Align Variable 226169689Skan(define_insn "mips_alnv_ps" 227169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 228169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 229169689Skan (match_operand:V2SF 2 "register_operand" "f") 230169689Skan (match_operand:SI 3 "register_operand" "d")] 231169689Skan UNSPEC_ALNV_PS))] 232169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 233169689Skan "alnv.ps\t%0,%1,%2,%3" 234169689Skan [(set_attr "type" "fmove") 235169689Skan (set_attr "mode" "SF")]) 236169689Skan 237169689Skan; addr.ps - Floating Point Reduction Add 238169689Skan(define_insn "mips_addr_ps" 239169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 240169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 241169689Skan (match_operand:V2SF 2 "register_operand" "f")] 242169689Skan UNSPEC_ADDR_PS))] 243169689Skan "TARGET_MIPS3D" 244169689Skan "addr.ps\t%0,%1,%2" 245169689Skan [(set_attr "type" "fadd") 246169689Skan (set_attr "mode" "SF")]) 247169689Skan 248169689Skan; cvt.pw.ps - Floating Point Convert Paired Single to Paired Word 249169689Skan(define_insn "mips_cvt_pw_ps" 250169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 251169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 252169689Skan UNSPEC_CVT_PW_PS))] 253169689Skan "TARGET_MIPS3D" 254169689Skan "cvt.pw.ps\t%0,%1" 255169689Skan [(set_attr "type" "fcvt") 256169689Skan (set_attr "mode" "SF")]) 257169689Skan 258169689Skan; cvt.ps.pw - Floating Point Convert Paired Word to Paired Single 259169689Skan(define_insn "mips_cvt_ps_pw" 260169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 261169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 262169689Skan UNSPEC_CVT_PS_PW))] 263169689Skan "TARGET_MIPS3D" 264169689Skan "cvt.ps.pw\t%0,%1" 265169689Skan [(set_attr "type" "fcvt") 266169689Skan (set_attr "mode" "SF")]) 267169689Skan 268169689Skan; mulr.ps - Floating Point Reduction Multiply 269169689Skan(define_insn "mips_mulr_ps" 270169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 271169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f") 272169689Skan (match_operand:V2SF 2 "register_operand" "f")] 273169689Skan UNSPEC_MULR_PS))] 274169689Skan "TARGET_MIPS3D" 275169689Skan "mulr.ps\t%0,%1,%2" 276169689Skan [(set_attr "type" "fmul") 277169689Skan (set_attr "mode" "SF")]) 278169689Skan 279169689Skan; abs.ps 280169689Skan(define_expand "mips_abs_ps" 281169689Skan [(set (match_operand:V2SF 0 "register_operand") 282169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand")] 283169689Skan UNSPEC_ABS_PS))] 284169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 285169689Skan{ 286169689Skan /* If we can ignore NaNs, this operation is equivalent to the 287169689Skan rtl ABS code. */ 288169689Skan if (!HONOR_NANS (V2SFmode)) 289169689Skan { 290169689Skan emit_insn (gen_absv2sf2 (operands[0], operands[1])); 291169689Skan DONE; 292169689Skan } 293169689Skan}) 294169689Skan 295169689Skan(define_insn "*mips_abs_ps" 296169689Skan [(set (match_operand:V2SF 0 "register_operand" "=f") 297169689Skan (unspec:V2SF [(match_operand:V2SF 1 "register_operand" "f")] 298169689Skan UNSPEC_ABS_PS))] 299169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 300169689Skan "abs.ps\t%0,%1" 301169689Skan [(set_attr "type" "fabs") 302169689Skan (set_attr "mode" "SF")]) 303169689Skan 304169689Skan;---------------------------------------------------------------------------- 305169689Skan; Floating Point Comparisons for Scalars 306169689Skan;---------------------------------------------------------------------------- 307169689Skan 308169689Skan(define_insn "mips_cabs_cond_<fmt>" 309169689Skan [(set (match_operand:CC 0 "register_operand" "=z") 310169689Skan (unspec:CC [(match_operand:SCALARF 1 "register_operand" "f") 311169689Skan (match_operand:SCALARF 2 "register_operand" "f") 312169689Skan (match_operand 3 "const_int_operand" "")] 313169689Skan UNSPEC_CABS))] 314169689Skan "TARGET_MIPS3D" 315169689Skan "cabs.%Y3.<fmt>\t%0,%1,%2" 316169689Skan [(set_attr "type" "fcmp") 317169689Skan (set_attr "mode" "FPSW")]) 318169689Skan 319169689Skan 320169689Skan;---------------------------------------------------------------------------- 321169689Skan; Floating Point Comparisons for Four Singles 322169689Skan;---------------------------------------------------------------------------- 323169689Skan 324169689Skan(define_insn_and_split "mips_c_cond_4s" 325169689Skan [(set (match_operand:CCV4 0 "register_operand" "=z") 326169689Skan (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") 327169689Skan (match_operand:V2SF 2 "register_operand" "f") 328169689Skan (match_operand:V2SF 3 "register_operand" "f") 329169689Skan (match_operand:V2SF 4 "register_operand" "f") 330169689Skan (match_operand 5 "const_int_operand" "")] 331169689Skan UNSPEC_C))] 332169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 333169689Skan "#" 334169689Skan "&& reload_completed" 335169689Skan [(set (match_dup 6) 336169689Skan (unspec:CCV2 [(match_dup 1) 337169689Skan (match_dup 2) 338169689Skan (match_dup 5)] 339169689Skan UNSPEC_C)) 340169689Skan (set (match_dup 7) 341169689Skan (unspec:CCV2 [(match_dup 3) 342169689Skan (match_dup 4) 343169689Skan (match_dup 5)] 344169689Skan UNSPEC_C))] 345169689Skan{ 346169689Skan operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); 347169689Skan operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); 348169689Skan} 349169689Skan [(set_attr "type" "fcmp") 350169689Skan (set_attr "length" "8") 351169689Skan (set_attr "mode" "FPSW")]) 352169689Skan 353169689Skan(define_insn_and_split "mips_cabs_cond_4s" 354169689Skan [(set (match_operand:CCV4 0 "register_operand" "=z") 355169689Skan (unspec:CCV4 [(match_operand:V2SF 1 "register_operand" "f") 356169689Skan (match_operand:V2SF 2 "register_operand" "f") 357169689Skan (match_operand:V2SF 3 "register_operand" "f") 358169689Skan (match_operand:V2SF 4 "register_operand" "f") 359169689Skan (match_operand 5 "const_int_operand" "")] 360169689Skan UNSPEC_CABS))] 361169689Skan "TARGET_MIPS3D" 362169689Skan "#" 363169689Skan "&& reload_completed" 364169689Skan [(set (match_dup 6) 365169689Skan (unspec:CCV2 [(match_dup 1) 366169689Skan (match_dup 2) 367169689Skan (match_dup 5)] 368169689Skan UNSPEC_CABS)) 369169689Skan (set (match_dup 7) 370169689Skan (unspec:CCV2 [(match_dup 3) 371169689Skan (match_dup 4) 372169689Skan (match_dup 5)] 373169689Skan UNSPEC_CABS))] 374169689Skan{ 375169689Skan operands[6] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 0); 376169689Skan operands[7] = simplify_gen_subreg (CCV2mode, operands[0], CCV4mode, 8); 377169689Skan} 378169689Skan [(set_attr "type" "fcmp") 379169689Skan (set_attr "length" "8") 380169689Skan (set_attr "mode" "FPSW")]) 381169689Skan 382169689Skan 383169689Skan;---------------------------------------------------------------------------- 384169689Skan; Floating Point Comparisons for Paired Singles 385169689Skan;---------------------------------------------------------------------------- 386169689Skan 387169689Skan(define_insn "mips_c_cond_ps" 388169689Skan [(set (match_operand:CCV2 0 "register_operand" "=z") 389169689Skan (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") 390169689Skan (match_operand:V2SF 2 "register_operand" "f") 391169689Skan (match_operand 3 "const_int_operand" "")] 392169689Skan UNSPEC_C))] 393169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 394169689Skan "c.%Y3.ps\t%0,%1,%2" 395169689Skan [(set_attr "type" "fcmp") 396169689Skan (set_attr "mode" "FPSW")]) 397169689Skan 398169689Skan(define_insn "mips_cabs_cond_ps" 399169689Skan [(set (match_operand:CCV2 0 "register_operand" "=z") 400169689Skan (unspec:CCV2 [(match_operand:V2SF 1 "register_operand" "f") 401169689Skan (match_operand:V2SF 2 "register_operand" "f") 402169689Skan (match_operand 3 "const_int_operand" "")] 403169689Skan UNSPEC_CABS))] 404169689Skan "TARGET_MIPS3D" 405169689Skan "cabs.%Y3.ps\t%0,%1,%2" 406169689Skan [(set_attr "type" "fcmp") 407169689Skan (set_attr "mode" "FPSW")]) 408169689Skan 409169689Skan;; An expander for generating an scc operation. 410169689Skan(define_expand "scc_ps" 411169689Skan [(set (match_operand:CCV2 0) 412169689Skan (unspec:CCV2 [(match_operand 1)] UNSPEC_SCC))]) 413169689Skan 414169689Skan(define_insn "s<code>_ps" 415169689Skan [(set (match_operand:CCV2 0 "register_operand" "=z") 416169689Skan (unspec:CCV2 417169689Skan [(fcond (match_operand:V2SF 1 "register_operand" "f") 418169689Skan (match_operand:V2SF 2 "register_operand" "f"))] 419169689Skan UNSPEC_SCC))] 420169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 421169689Skan "c.<fcond>.ps\t%0,%1,%2" 422169689Skan [(set_attr "type" "fcmp") 423169689Skan (set_attr "mode" "FPSW")]) 424169689Skan 425169689Skan(define_insn "s<code>_ps" 426169689Skan [(set (match_operand:CCV2 0 "register_operand" "=z") 427169689Skan (unspec:CCV2 428169689Skan [(swapped_fcond (match_operand:V2SF 1 "register_operand" "f") 429169689Skan (match_operand:V2SF 2 "register_operand" "f"))] 430169689Skan UNSPEC_SCC))] 431169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 432169689Skan "c.<swapped_fcond>.ps\t%0,%2,%1" 433169689Skan [(set_attr "type" "fcmp") 434169689Skan (set_attr "mode" "FPSW")]) 435169689Skan 436169689Skan;---------------------------------------------------------------------------- 437169689Skan; Floating Point Branch Instructions. 438169689Skan;---------------------------------------------------------------------------- 439169689Skan 440169689Skan; Branch on Any of Four Floating Point Condition Codes True 441169689Skan(define_insn "bc1any4t" 442169689Skan [(set (pc) 443169689Skan (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 444169689Skan (const_int 0)) 445169689Skan (label_ref (match_operand 1 "" "")) 446169689Skan (pc)))] 447169689Skan "TARGET_MIPS3D" 448169689Skan "%*bc1any4t\t%0,%1%/" 449169689Skan [(set_attr "type" "branch") 450169689Skan (set_attr "mode" "none")]) 451169689Skan 452169689Skan; Branch on Any of Four Floating Point Condition Codes False 453169689Skan(define_insn "bc1any4f" 454169689Skan [(set (pc) 455169689Skan (if_then_else (ne (match_operand:CCV4 0 "register_operand" "z") 456169689Skan (const_int -1)) 457169689Skan (label_ref (match_operand 1 "" "")) 458169689Skan (pc)))] 459169689Skan "TARGET_MIPS3D" 460169689Skan "%*bc1any4f\t%0,%1%/" 461169689Skan [(set_attr "type" "branch") 462169689Skan (set_attr "mode" "none")]) 463169689Skan 464169689Skan; Branch on Any of Two Floating Point Condition Codes True 465169689Skan(define_insn "bc1any2t" 466169689Skan [(set (pc) 467169689Skan (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 468169689Skan (const_int 0)) 469169689Skan (label_ref (match_operand 1 "" "")) 470169689Skan (pc)))] 471169689Skan "TARGET_MIPS3D" 472169689Skan "%*bc1any2t\t%0,%1%/" 473169689Skan [(set_attr "type" "branch") 474169689Skan (set_attr "mode" "none")]) 475169689Skan 476169689Skan; Branch on Any of Two Floating Point Condition Codes False 477169689Skan(define_insn "bc1any2f" 478169689Skan [(set (pc) 479169689Skan (if_then_else (ne (match_operand:CCV2 0 "register_operand" "z") 480169689Skan (const_int -1)) 481169689Skan (label_ref (match_operand 1 "" "")) 482169689Skan (pc)))] 483169689Skan "TARGET_MIPS3D" 484169689Skan "%*bc1any2f\t%0,%1%/" 485169689Skan [(set_attr "type" "branch") 486169689Skan (set_attr "mode" "none")]) 487169689Skan 488169689Skan; Used to access one register in a CCV2 pair. Operand 0 is the register 489169689Skan; pair and operand 1 is the index of the register we want (a CONST_INT). 490169689Skan(define_expand "single_cc" 491169689Skan [(ne (unspec:CC [(match_operand 0) (match_operand 1)] UNSPEC_SINGLE_CC) 492169689Skan (const_int 0))]) 493169689Skan 494169689Skan; This is a normal floating-point branch pattern, but rather than check 495169689Skan; a single CCmode register, it checks one register in a CCV2 pair. 496169689Skan; Operand 2 is the register pair and operand 3 is the index of the 497169689Skan; register we want. 498169689Skan(define_insn "*branch_upper_lower" 499169689Skan [(set (pc) 500169689Skan (if_then_else 501169689Skan (match_operator 0 "equality_operator" 502169689Skan [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 503169689Skan (match_operand 3 "const_int_operand")] 504169689Skan UNSPEC_SINGLE_CC) 505169689Skan (const_int 0)]) 506169689Skan (label_ref (match_operand 1 "" "")) 507169689Skan (pc)))] 508169689Skan "TARGET_HARD_FLOAT" 509169689Skan{ 510169689Skan operands[2] 511169689Skan = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 512169689Skan return mips_output_conditional_branch (insn, operands, 513169689Skan MIPS_BRANCH ("b%F0", "%2,%1"), 514169689Skan MIPS_BRANCH ("b%W0", "%2,%1")); 515169689Skan} 516169689Skan [(set_attr "type" "branch") 517169689Skan (set_attr "mode" "none")]) 518169689Skan 519169689Skan; As above, but with the sense of the condition reversed. 520169689Skan(define_insn "*branch_upper_lower_inverted" 521169689Skan [(set (pc) 522169689Skan (if_then_else 523169689Skan (match_operator 0 "equality_operator" 524169689Skan [(unspec:CC [(match_operand:CCV2 2 "register_operand" "z") 525169689Skan (match_operand 3 "const_int_operand")] 526169689Skan UNSPEC_SINGLE_CC) 527169689Skan (const_int 0)]) 528169689Skan (pc) 529169689Skan (label_ref (match_operand 1 "" ""))))] 530169689Skan "TARGET_HARD_FLOAT" 531169689Skan{ 532169689Skan operands[2] 533169689Skan = gen_rtx_REG (CCmode, REGNO (operands[2]) + INTVAL (operands[3])); 534169689Skan return mips_output_conditional_branch (insn, operands, 535169689Skan MIPS_BRANCH ("b%W0", "%2,%1"), 536169689Skan MIPS_BRANCH ("b%F0", "%2,%1")); 537169689Skan} 538169689Skan [(set_attr "type" "branch") 539169689Skan (set_attr "mode" "none")]) 540169689Skan 541169689Skan;---------------------------------------------------------------------------- 542169689Skan; Floating Point Reduced Precision Reciprocal Square Root Instructions. 543169689Skan;---------------------------------------------------------------------------- 544169689Skan 545169689Skan(define_insn "mips_rsqrt1_<fmt>" 546169689Skan [(set (match_operand:ANYF 0 "register_operand" "=f") 547169689Skan (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] 548169689Skan UNSPEC_RSQRT1))] 549169689Skan "TARGET_MIPS3D" 550169689Skan "rsqrt1.<fmt>\t%0,%1" 551169689Skan [(set_attr "type" "frsqrt1") 552169689Skan (set_attr "mode" "<UNITMODE>")]) 553169689Skan 554169689Skan(define_insn "mips_rsqrt2_<fmt>" 555169689Skan [(set (match_operand:ANYF 0 "register_operand" "=f") 556169689Skan (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") 557169689Skan (match_operand:ANYF 2 "register_operand" "f")] 558169689Skan UNSPEC_RSQRT2))] 559169689Skan "TARGET_MIPS3D" 560169689Skan "rsqrt2.<fmt>\t%0,%1,%2" 561169689Skan [(set_attr "type" "frsqrt2") 562169689Skan (set_attr "mode" "<UNITMODE>")]) 563169689Skan 564169689Skan(define_insn "mips_recip1_<fmt>" 565169689Skan [(set (match_operand:ANYF 0 "register_operand" "=f") 566169689Skan (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")] 567169689Skan UNSPEC_RECIP1))] 568169689Skan "TARGET_MIPS3D" 569169689Skan "recip1.<fmt>\t%0,%1" 570169689Skan [(set_attr "type" "frdiv1") 571169689Skan (set_attr "mode" "<UNITMODE>")]) 572169689Skan 573169689Skan(define_insn "mips_recip2_<fmt>" 574169689Skan [(set (match_operand:ANYF 0 "register_operand" "=f") 575169689Skan (unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f") 576169689Skan (match_operand:ANYF 2 "register_operand" "f")] 577169689Skan UNSPEC_RECIP2))] 578169689Skan "TARGET_MIPS3D" 579169689Skan "recip2.<fmt>\t%0,%1,%2" 580169689Skan [(set_attr "type" "frdiv2") 581169689Skan (set_attr "mode" "<UNITMODE>")]) 582169689Skan 583169689Skan(define_expand "vcondv2sf" 584169689Skan [(set (match_operand:V2SF 0 "register_operand") 585169689Skan (if_then_else:V2SF 586169689Skan (match_operator 3 "" 587169689Skan [(match_operand:V2SF 4 "register_operand") 588169689Skan (match_operand:V2SF 5 "register_operand")]) 589169689Skan (match_operand:V2SF 1 "register_operand") 590169689Skan (match_operand:V2SF 2 "register_operand")))] 591169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 592169689Skan{ 593169689Skan mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 594169689Skan GET_CODE (operands[3]), operands[4], operands[5]); 595169689Skan DONE; 596169689Skan}) 597169689Skan 598169689Skan(define_expand "sminv2sf3" 599169689Skan [(set (match_operand:V2SF 0 "register_operand") 600169689Skan (smin:V2SF (match_operand:V2SF 1 "register_operand") 601169689Skan (match_operand:V2SF 2 "register_operand")))] 602169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 603169689Skan{ 604169689Skan mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 605169689Skan LE, operands[1], operands[2]); 606169689Skan DONE; 607169689Skan}) 608169689Skan 609169689Skan(define_expand "smaxv2sf3" 610169689Skan [(set (match_operand:V2SF 0 "register_operand") 611169689Skan (smax:V2SF (match_operand:V2SF 1 "register_operand") 612169689Skan (match_operand:V2SF 2 "register_operand")))] 613169689Skan "TARGET_PAIRED_SINGLE_FLOAT" 614169689Skan{ 615169689Skan mips_expand_vcondv2sf (operands[0], operands[1], operands[2], 616169689Skan LE, operands[2], operands[1]); 617169689Skan DONE; 618169689Skan}) 619