constraints.md revision 169689
171167Sache;; Constraint definitions for MIPS. 271167Sache;; Copyright (C) 2006 Free Software Foundation, Inc. 371167Sache;; 471167Sache;; This file is part of GCC. 571167Sache;; 671167Sache;; GCC is free software; you can redistribute it and/or modify 771167Sache;; it under the terms of the GNU General Public License as published by 871167Sache;; the Free Software Foundation; either version 2, or (at your option) 971167Sache;; any later version. 1071167Sache;; 1171167Sache;; GCC is distributed in the hope that it will be useful, 1271167Sache;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13270114Sse;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1471167Sache;; GNU General Public License for more details. 1571167Sache;; 1671167Sache;; You should have received a copy of the GNU General Public License 1771167Sache;; along with GCC; see the file COPYING. If not, write to 1871167Sache;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 1971167Sache;; Boston, MA 02110-1301, USA. 2071167Sache 2171167Sache;; Register constraints 2271167Sache 2371167Sache(define_register_constraint "d" "BASE_REG_CLASS" 2471167Sache "An address register. This is equivalent to @code{r} unless 25270114Sse generating MIPS16 code.") 26270114Sse 27270114Sse(define_register_constraint "t" "T_REG" 28270114Sse "@internal") 29270114Sse 30270114Sse(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" 31270114Sse "A floating-point register (if available).") 32270114Sse 33270114Sse(define_register_constraint "h" "HI_REG" 34270114Sse "The @code{hi} register.") 3571167Sache 3671167Sache(define_register_constraint "l" "LO_REG" 3771167Sache "The @code{lo} register.") 3871167Sache 39270114Sse(define_register_constraint "x" "MD_REGS" 40270114Sse "The @code{hi} and @code{lo} registers.") 41270114Sse 42270114Sse(define_register_constraint "b" "ALL_REGS" 43270114Sse "@internal") 44270114Sse 45270114Sse(define_register_constraint "c" "TARGET_ABICALLS ? PIC_FN_ADDR_REG 46270114Sse : TARGET_MIPS16 ? M16_NA_REGS 47270114Sse : GR_REGS" 4871167Sache "A register suitable for use in an indirect jump. This will always be 4971167Sache @code{$25} for @option{-mabicalls}.") 5071167Sache 5171167Sache(define_register_constraint "e" "LEA_REGS" 5271167Sache "@internal") 53270114Sse 54270114Sse(define_register_constraint "j" "PIC_FN_ADDR_REG" 55270114Sse "@internal") 56270114Sse 57270114Sse(define_register_constraint "v" "V1_REG" 58270114Sse "@internal") 59270114Sse 6071167Sache(define_register_constraint "y" "GR_REGS" 6171167Sache "Equivalent to @code{r}; retained for backwards compatibility.") 6271167Sache 6371167Sache(define_register_constraint "z" "ST_REGS" 6471167Sache "A floating-point condition code register.") 6571167Sache 6671167Sache(define_register_constraint "A" "DSP_ACC_REGS" 6771167Sache "@internal") 6871167Sache 6971167Sache(define_register_constraint "a" "ACC_REGS" 7071167Sache "@internal") 7171167Sache 7271167Sache(define_register_constraint "B" "COP0_REGS" 7371167Sache "@internal") 7471167Sache 7571167Sache(define_register_constraint "C" "COP2_REGS" 7671167Sache "@internal") 7771167Sache 7871167Sache(define_register_constraint "D" "COP3_REGS" 7971167Sache "@internal") 8071167Sache 8171167Sache;; Integer constraints 8271167Sache 8371167Sache(define_constraint "I" 8471167Sache "A signed 16-bit constant (for arithmetic instructions)." 8571167Sache (and (match_code "const_int") 8671167Sache (match_test "SMALL_OPERAND (ival)"))) 8771167Sache 8871167Sache(define_constraint "J" 8971167Sache "Integer zero." 9071167Sache (and (match_code "const_int") 9171167Sache (match_test "ival == 0"))) 9271167Sache 9371167Sache(define_constraint "K" 9471167Sache "An unsigned 16-bit constant (for logic instructions)." 9571167Sache (and (match_code "const_int") 9671167Sache (match_test "SMALL_OPERAND_UNSIGNED (ival)"))) 9771167Sache 9871167Sache(define_constraint "L" 9971167Sache "A signed 32-bit constant in which the lower 16 bits are zero. 10071167Sache Such constants can be loaded using @code{lui}." 10174119Sache (and (match_code "const_int") 10271167Sache (match_test "LUI_OPERAND (ival)"))) 10371167Sache 10471167Sache(define_constraint "M" 10571167Sache "A constant that cannot be loaded using @code{lui}, @code{addiu} 10671167Sache or @code{ori}." 10771167Sache (and (match_code "const_int") 10871167Sache (match_test "!SMALL_OPERAND (ival)") 10971167Sache (match_test "!SMALL_OPERAND_UNSIGNED (ival)") 11071167Sache (match_test "!LUI_OPERAND (ival)"))) 11174119Sache 112270114Sse(define_constraint "N" 11371167Sache "A constant in the range -65535 to -1 (inclusive)." 114270114Sse (and (match_code "const_int") 115270114Sse (match_test "ival >= -0xffff && ival < 0"))) 116270114Sse 11771167Sache(define_constraint "O" 11871167Sache "A signed 15-bit constant." 11971167Sache (and (match_code "const_int") 12071167Sache (match_test "ival >= -0x4000 && ival < 0x4000"))) 12171167Sache 12271167Sache(define_constraint "P" 12371167Sache "A constant in the range 1 to 65535 (inclusive)." 12471167Sache (and (match_code "const_int") 12571167Sache (match_test "ival > 0 && ival < 0x10000"))) 12671167Sache 12771167Sache;; Floating-point constraints 12871167Sache 12971167Sache(define_constraint "G" 13071167Sache "Floating-point zero." 13171167Sache (and (match_code "const_double") 13271167Sache (match_test "op == CONST0_RTX (mode)"))) 13371167Sache 13471167Sache;; General constraints 13571167Sache 13671167Sache(define_constraint "Q" 13771167Sache "@internal" 13871167Sache (match_operand 0 "const_arith_operand")) 13971167Sache 14071167Sache(define_memory_constraint "R" 14171167Sache "An address that can be used in a non-macro load or store." 14271167Sache (and (match_code "mem") 143270114Sse (match_test "mips_fetch_insns (op) == 1"))) 14471167Sache 14571167Sache(define_constraint "S" 14671167Sache "@internal 14771167Sache A constant call address." 14871167Sache (and (match_operand 0 "call_insn_operand") 14971167Sache (match_test "CONSTANT_P (op)"))) 15071167Sache 15171167Sache(define_constraint "T" 15271167Sache "@internal 15371167Sache A constant @code{move_operand} that cannot be safely loaded into @code{$25} 15471167Sache using @code{la}." 155270114Sse (and (match_operand 0 "move_operand") 156270114Sse (match_test "CONSTANT_P (op)") 157270114Sse (match_test "mips_dangerous_for_la25_p (op)"))) 158270114Sse 159270114Sse(define_constraint "U" 160270114Sse "@internal 161270114Sse A constant @code{move_operand} that can be safely loaded into @code{$25} 162270114Sse using @code{la}." 163270114Sse (and (match_operand 0 "move_operand") 164270114Sse (match_test "CONSTANT_P (op)") 16571167Sache (match_test "!mips_dangerous_for_la25_p (op)"))) 16671167Sache 16771167Sache(define_memory_constraint "W" 16871167Sache "@internal 169270114Sse A memory address based on a member of @code{BASE_REG_CLASS}. This is 170270114Sse true for all non-mips16 references (although it can sometimes be implicit 171270114Sse if @samp{!TARGET_EXPLICIT_RELOCS}). For MIPS16, it excludes stack and 172270114Sse constant-pool references." 173270114Sse (and (match_code "mem") 174270114Sse (match_operand 0 "memory_operand") 175270114Sse (ior (match_test "!TARGET_MIPS16") 176270114Sse (and (not (match_operand 0 "stack_operand")) 177270114Sse (not (match_test "CONSTANT_P (XEXP (op, 0))")))))) 17871167Sache 17971167Sache(define_constraint "YG" 18071167Sache "@internal 18171167Sache A vector zero." 18271167Sache (and (match_code "const_vector") 183270114Sse (match_test "op == CONST0_RTX (mode)"))) 184270114Sse 185270114Sse(define_constraint "YA" 186270114Sse "@internal 187270114Sse An unsigned 6-bit constant." 188270114Sse (and (match_code "const_int") 189270114Sse (match_test "UIMM6_OPERAND (ival)"))) 19071167Sache 19171167Sache(define_constraint "YB" 19271167Sache "@internal 19371167Sache A signed 10-bit constant." 19471167Sache (and (match_code "const_int") 19571167Sache (match_test "IMM10_OPERAND (ival)"))) 19671167Sache