5k.md revision 169690
1;; DFA-based pipeline descriptions for MIPS32 5K processor family 2;; Contributed by David Ung (davidu@mips.com) 3;; and Nigel Stephens (nigel@mips.com) 4;; 5;; References: 6;; "MIPS64 5K Processor Core Family Software User's Manual, 7;; Doc no: MD00012, Rev 2.09, Jan 28, 2005." 8;; 9;; 5Kc - Single issue with no floating point unit. 10;; 5kf - Separate floating point pipe which can dual-issue with the 11;; integer pipe. 12;; 13;; Copyright (C) 2005 Free Software Foundation, Inc. 14;; 15;; This file is part of GCC. 16;; 17;; GCC is free software; you can redistribute it and/or modify it 18;; under the terms of the GNU General Public License as published 19;; by the Free Software Foundation; either version 2, or (at your 20;; option) any later version. 21 22;; GCC is distributed in the hope that it will be useful, but WITHOUT 23;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25;; License for more details. 26 27;; You should have received a copy of the GNU General Public License 28;; along with GCC; see the file COPYING. If not, write to the 29;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 30;; MA 02110-1301, USA. 31 32(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu") 33 34;; Integer execution unit. 35(define_cpu_unit "r5k_ixu_arith" "r5k_cpu") 36(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu") 37(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu") 38 39(define_insn_reservation "r5k_int_load" 2 40 (and (eq_attr "cpu" "5kc,5kf") 41 (eq_attr "type" "load")) 42 "r5k_ixu_arith") 43 44(define_insn_reservation "r5k_int_prefetch" 1 45 (and (eq_attr "cpu" "5kc,5kf") 46 (eq_attr "type" "prefetch,prefetchx")) 47 "r5k_ixu_arith") 48 49(define_insn_reservation "r5k_int_store" 1 50 (and (eq_attr "cpu" "5kc,5kf") 51 (eq_attr "type" "store")) 52 "r5k_ixu_arith") 53 54;; Divides 55(define_insn_reservation "r5k_int_divsi" 34 56 (and (eq_attr "cpu" "5kc,5kf") 57 (and (eq_attr "type" "idiv") 58 (eq_attr "mode" "!DI"))) 59 "r5k_ixu_arith+(r5k_ixu_mpydiv*34)") 60 61(define_insn_reservation "r5k_int_divdi" 66 62 (and (eq_attr "cpu" "5kc,5kf") 63 (and (eq_attr "type" "idiv") 64 (eq_attr "mode" "DI"))) 65 "r5k_ixu_arith+(r5k_ixu_mpydiv*66)") 66 67;; 32x32 multiply 68;; 32x16 is faster, but there's no way to detect this 69(define_insn_reservation "r5k_int_mult" 2 70 (and (eq_attr "cpu" "5kc,5kf") 71 (and (eq_attr "type" "imul,imadd") 72 (eq_attr "mode" "SI"))) 73 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 74 75;; 64x64 multiply 76(define_insn_reservation "r5k_int_mult_64" 9 77 (and (eq_attr "cpu" "5kc,5kf") 78 (and (eq_attr "type" "imul,imadd") 79 (eq_attr "mode" "DI"))) 80 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 81 82;; 3 operand MUL 32x32 83(define_insn_reservation "r5k_int_mul" 4 84 (and (eq_attr "cpu" "5kc,5kf") 85 (and (eq_attr "type" "imul3") 86 (eq_attr "mode" "SI"))) 87 "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 88 89;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 90(define_insn_reservation "r5k_int_mthilo" 1 91 (and (eq_attr "cpu" "5kc,5kf") 92 (eq_attr "type" "mthilo")) 93 "r5k_ixu_arith+r5k_ixu_mpydiv") 94 95;; Move from HI/LO -> integer operation has a 2 cycle latency. 96(define_insn_reservation "r5k_int_mfhilo" 2 97 (and (eq_attr "cpu" "5kc,5kf") 98 (eq_attr "type" "mfhilo")) 99 "r5k_ixu_arith+r5k_ixu_mpydiv") 100 101;; All other integer insns. 102(define_insn_reservation "r5k_int_alu" 1 103 (and (eq_attr "cpu" "5kc,5kf") 104 (eq_attr "type" "arith,condmove,shift,const,nop,slt")) 105 "r5k_ixu_arith") 106 107(define_insn_reservation "r5k_int_branch" 1 108 (and (eq_attr "cpu" "5kc,5kf") 109 (eq_attr "type" "branch")) 110 "r5k_ixu_arith") 111 112;; JR/JALR always cause one pipeline bubble because of interlock. 113(define_insn_reservation "r5k_int_jump" 2 114 (and (eq_attr "cpu" "5kc,5kf") 115 (eq_attr "type" "jump,call")) 116 "r5k_ixu_arith") 117 118;; Any -> JR/JALR (without dependency) : 1 clock issue delay 119;; Any -> JR/JALR (with dependency) : 2 clock issue delay 120;; load -> JR/JALR (with dependency) : 3 clock issue delay 121;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay 122;; mul -> JR/JALR (with dependency) : 3 clock issue delay 123(define_bypass 2 "r5k_int_alu" "r5k_int_jump") 124(define_bypass 3 "r5k_int_load" "r5k_int_jump") 125(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump") 126(define_bypass 3 "r5k_int_mul" "r5k_int_jump") 127 128;; Unknown or multi - single issue 129(define_insn_reservation "r5k_int_unknown" 1 130 (and (eq_attr "cpu" "5kc,5kf") 131 (eq_attr "type" "unknown,multi")) 132 "r5k_ixu_arith+r5k_ixu_mpydiv") 133 134 135;; Floating Point Instructions 136;; The 5Kf is a partial dual-issue cpu which can dual issue an integer 137;; and floating-point instruction in the same cycle. 138 139;; fadd, fabs, fneg 140(define_insn_reservation "r5kf_fadd" 4 141 (and (eq_attr "cpu" "5kf") 142 (eq_attr "type" "fadd,fabs,fneg")) 143 "r5kf_fpu_arith") 144 145;; fmove, fcmove 146(define_insn_reservation "r5kf_fmove" 4 147 (and (eq_attr "cpu" "5kf") 148 (eq_attr "type" "fmove")) 149 "r5kf_fpu_arith") 150 151;; fload 152(define_insn_reservation "r5kf_fload" 3 153 (and (eq_attr "cpu" "5kf") 154 (eq_attr "type" "fpload,fpidxload")) 155 "r5kf_fpu_arith") 156 157;; fstore 158(define_insn_reservation "r5kf_fstore" 1 159 (and (eq_attr "cpu" "5kf") 160 (eq_attr "type" "fpstore")) 161 "r5kf_fpu_arith") 162 163;; fmul, fmadd 164(define_insn_reservation "r5kf_fmul_sf" 4 165 (and (eq_attr "cpu" "5kf") 166 (and (eq_attr "type" "fmul,fmadd") 167 (eq_attr "mode" "SF"))) 168 "r5kf_fpu_arith") 169 170(define_insn_reservation "r5kf_fmul_df" 5 171 (and (eq_attr "cpu" "5kf") 172 (and (eq_attr "type" "fmul,fmadd") 173 (eq_attr "mode" "DF"))) 174 "r5kf_fpu_arith*2") 175 176;; fdiv, fsqrt, frsqrt 177(define_insn_reservation "r5kf_fdiv_sf" 17 178 (and (eq_attr "cpu" "5kf") 179 (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 180 (eq_attr "mode" "SF"))) 181 "r5kf_fpu_arith*14") 182 183(define_insn_reservation "r5kf_fdiv_df" 32 184 (and (eq_attr "cpu" "5kf") 185 (and (eq_attr "type" "fdiv,fsqrt") 186 (eq_attr "mode" "DF"))) 187 "r5kf_fpu_arith*29") 188 189;; frsqrt 190(define_insn_reservation "r5kf_frsqrt_df" 35 191 (and (eq_attr "cpu" "5kf") 192 (and (eq_attr "type" "frsqrt") 193 (eq_attr "mode" "DF"))) 194 "r5kf_fpu_arith*31") 195 196;; fcmp 197(define_insn_reservation "r5kf_fcmp" 2 198 (and (eq_attr "cpu" "5kf") 199 (eq_attr "type" "fcmp")) 200 "r5kf_fpu_arith") 201 202;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition) 203(define_bypass 1 "r5kf_fcmp" "r5kf_fmove") 204 205;; fcvt (cvt.d.s, cvt.[sd].[wl] 206(define_insn_reservation "r5kf_fcvt_d2s" 4 207 (and (eq_attr "cpu" "5kf") 208 (and (eq_attr "type" "fcvt") 209 (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 210 "r5kf_fpu_arith") 211 212;; fcvt (cvt.s.d) 213(define_insn_reservation "r5kf_fcvt_s2d" 6 214 (and (eq_attr "cpu" "5kc") 215 (and (eq_attr "type" "fcvt") 216 (eq_attr "cnv_mode" "D2S"))) 217 "r5kf_fpu_arith") 218 219;; fcvt (cvt.[wl].[sd], etc) 220(define_insn_reservation "r5kf_fcvt_f2i" 5 221 (and (eq_attr "cpu" "5kf") 222 (and (eq_attr "type" "fcvt") 223 (eq_attr "cnv_mode" "S2I,D2I"))) 224 "r5kf_fpu_arith") 225 226;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue 227(define_insn_reservation "r5kf_fxfer" 2 228 (and (eq_attr "cpu" "5kf") 229 (eq_attr "type" "xfer")) 230 "r5k_ixu_arith+r5kf_fpu_arith") 231