5k.md revision 169689
1169689Skan;; DFA-based pipeline descriptions for MIPS32 5K processor family 2169689Skan;; Contributed by David Ung (davidu@mips.com) 3169689Skan;; and Nigel Stephens (nigel@mips.com) 4169689Skan;; 5169689Skan;; References: 6169689Skan;; "MIPS64 5K Processor Core Family Software User's Manual, 7169689Skan;; Doc no: MD00012, Rev 2.09, Jan 28, 2005." 8169689Skan;; 9169689Skan;; 5Kc - Single issue with no floating point unit. 10169689Skan;; 5kf - Separate floating point pipe which can dual-issue with the 11169689Skan;; integer pipe. 12169689Skan;; 13169689Skan;; Copyright (C) 2005 Free Software Foundation, Inc. 14169689Skan;; 15169689Skan;; This file is part of GCC. 16169689Skan;; 17169689Skan;; GCC is free software; you can redistribute it and/or modify it 18169689Skan;; under the terms of the GNU General Public License as published 19169689Skan;; by the Free Software Foundation; either version 2, or (at your 20169689Skan;; option) any later version. 21169689Skan 22169689Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 23169689Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24169689Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25169689Skan;; License for more details. 26169689Skan 27169689Skan;; You should have received a copy of the GNU General Public License 28169689Skan;; along with GCC; see the file COPYING. If not, write to the 29169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 30169689Skan;; MA 02110-1301, USA. 31169689Skan 32169689Skan(define_automaton "r5k_cpu, r5k_mdu, r5k_fpu") 33169689Skan 34169689Skan;; Integer execution unit. 35169689Skan(define_cpu_unit "r5k_ixu_arith" "r5k_cpu") 36169689Skan(define_cpu_unit "r5k_ixu_mpydiv" "r5k_mdu") 37169689Skan(define_cpu_unit "r5kf_fpu_arith" "r5k_fpu") 38169689Skan 39169689Skan(define_insn_reservation "r5k_int_load" 2 40169689Skan (and (eq_attr "cpu" "5kc,5kf") 41169689Skan (eq_attr "type" "load")) 42169689Skan "r5k_ixu_arith") 43169689Skan 44169689Skan(define_insn_reservation "r5k_int_prefetch" 1 45169689Skan (and (eq_attr "cpu" "5kc,5kf") 46169689Skan (eq_attr "type" "prefetch,prefetchx")) 47169689Skan "r5k_ixu_arith") 48169689Skan 49169689Skan(define_insn_reservation "r5k_int_store" 1 50169689Skan (and (eq_attr "cpu" "5kc,5kf") 51169689Skan (eq_attr "type" "store")) 52169689Skan "r5k_ixu_arith") 53169689Skan 54169689Skan;; Divides 55169689Skan(define_insn_reservation "r5k_int_divsi" 34 56169689Skan (and (eq_attr "cpu" "5kc,5kf") 57169689Skan (and (eq_attr "type" "idiv") 58169689Skan (eq_attr "mode" "!DI"))) 59169689Skan "r5k_ixu_arith+(r5k_ixu_mpydiv*34)") 60169689Skan 61169689Skan(define_insn_reservation "r5k_int_divdi" 66 62169689Skan (and (eq_attr "cpu" "5kc,5kf") 63169689Skan (and (eq_attr "type" "idiv") 64169689Skan (eq_attr "mode" "DI"))) 65169689Skan "r5k_ixu_arith+(r5k_ixu_mpydiv*66)") 66169689Skan 67169689Skan;; 32x32 multiply 68169689Skan;; 32x16 is faster, but there's no way to detect this 69169689Skan(define_insn_reservation "r5k_int_mult" 2 70169689Skan (and (eq_attr "cpu" "5kc,5kf") 71169689Skan (and (eq_attr "type" "imul,imadd") 72169689Skan (eq_attr "mode" "SI"))) 73169689Skan "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 74169689Skan 75169689Skan;; 64x64 multiply 76169689Skan(define_insn_reservation "r5k_int_mult_64" 9 77169689Skan (and (eq_attr "cpu" "5kc,5kf") 78169689Skan (and (eq_attr "type" "imul,imadd") 79169689Skan (eq_attr "mode" "DI"))) 80169689Skan "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 81169689Skan 82169689Skan;; 3 operand MUL 32x32 83169689Skan(define_insn_reservation "r5k_int_mul" 4 84169689Skan (and (eq_attr "cpu" "5kc,5kf") 85169689Skan (and (eq_attr "type" "imul3") 86169689Skan (eq_attr "mode" "SI"))) 87169689Skan "r5k_ixu_arith+(r5k_ixu_mpydiv*2)") 88169689Skan 89169689Skan;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 90169689Skan(define_insn_reservation "r5k_int_mthilo" 1 91169689Skan (and (eq_attr "cpu" "5kc,5kf") 92169689Skan (eq_attr "type" "mthilo")) 93169689Skan "r5k_ixu_arith+r5k_ixu_mpydiv") 94169689Skan 95169689Skan;; Move from HI/LO -> integer operation has a 2 cycle latency. 96169689Skan(define_insn_reservation "r5k_int_mfhilo" 2 97169689Skan (and (eq_attr "cpu" "5kc,5kf") 98169689Skan (eq_attr "type" "mfhilo")) 99169689Skan "r5k_ixu_arith+r5k_ixu_mpydiv") 100169689Skan 101169689Skan;; All other integer insns. 102169689Skan(define_insn_reservation "r5k_int_alu" 1 103169689Skan (and (eq_attr "cpu" "5kc,5kf") 104169689Skan (eq_attr "type" "arith,condmove,shift,const,nop,slt")) 105169689Skan "r5k_ixu_arith") 106169689Skan 107169689Skan(define_insn_reservation "r5k_int_branch" 1 108169689Skan (and (eq_attr "cpu" "5kc,5kf") 109169689Skan (eq_attr "type" "branch")) 110169689Skan "r5k_ixu_arith") 111169689Skan 112169689Skan;; JR/JALR always cause one pipeline bubble because of interlock. 113169689Skan(define_insn_reservation "r5k_int_jump" 2 114169689Skan (and (eq_attr "cpu" "5kc,5kf") 115169689Skan (eq_attr "type" "jump,call")) 116169689Skan "r5k_ixu_arith") 117169689Skan 118169689Skan;; Any -> JR/JALR (without dependency) : 1 clock issue delay 119169689Skan;; Any -> JR/JALR (with dependency) : 2 clock issue delay 120169689Skan;; load -> JR/JALR (with dependency) : 3 clock issue delay 121169689Skan;; mfhilo -> JR/JALR (with dependency) : 3 clock issue delay 122169689Skan;; mul -> JR/JALR (with dependency) : 3 clock issue delay 123169689Skan(define_bypass 2 "r5k_int_alu" "r5k_int_jump") 124169689Skan(define_bypass 3 "r5k_int_load" "r5k_int_jump") 125169689Skan(define_bypass 3 "r5k_int_mfhilo" "r5k_int_jump") 126169689Skan(define_bypass 3 "r5k_int_mul" "r5k_int_jump") 127169689Skan 128169689Skan;; Unknown or multi - single issue 129169689Skan(define_insn_reservation "r5k_int_unknown" 1 130169689Skan (and (eq_attr "cpu" "5kc,5kf") 131169689Skan (eq_attr "type" "unknown,multi")) 132169689Skan "r5k_ixu_arith+r5k_ixu_mpydiv") 133169689Skan 134169689Skan 135169689Skan;; Floating Point Instructions 136169689Skan;; The 5Kf is a partial dual-issue cpu which can dual issue an integer 137169689Skan;; and floating-point instruction in the same cycle. 138169689Skan 139169689Skan;; fadd, fabs, fneg 140169689Skan(define_insn_reservation "r5kf_fadd" 4 141169689Skan (and (eq_attr "cpu" "5kf") 142169689Skan (eq_attr "type" "fadd,fabs,fneg")) 143169689Skan "r5kf_fpu_arith") 144169689Skan 145169689Skan;; fmove, fcmove 146169689Skan(define_insn_reservation "r5kf_fmove" 4 147169689Skan (and (eq_attr "cpu" "5kf") 148169689Skan (eq_attr "type" "fmove")) 149169689Skan "r5kf_fpu_arith") 150169689Skan 151169689Skan;; fload 152169689Skan(define_insn_reservation "r5kf_fload" 3 153169689Skan (and (eq_attr "cpu" "5kf") 154169689Skan (eq_attr "type" "fpload,fpidxload")) 155169689Skan "r5kf_fpu_arith") 156169689Skan 157169689Skan;; fstore 158169689Skan(define_insn_reservation "r5kf_fstore" 1 159169689Skan (and (eq_attr "cpu" "5kf") 160169689Skan (eq_attr "type" "fpstore")) 161169689Skan "r5kf_fpu_arith") 162169689Skan 163169689Skan;; fmul, fmadd 164169689Skan(define_insn_reservation "r5kf_fmul_sf" 4 165169689Skan (and (eq_attr "cpu" "5kf") 166169689Skan (and (eq_attr "type" "fmul,fmadd") 167169689Skan (eq_attr "mode" "SF"))) 168169689Skan "r5kf_fpu_arith") 169169689Skan 170169689Skan(define_insn_reservation "r5kf_fmul_df" 5 171169689Skan (and (eq_attr "cpu" "5kf") 172169689Skan (and (eq_attr "type" "fmul,fmadd") 173169689Skan (eq_attr "mode" "DF"))) 174169689Skan "r5kf_fpu_arith*2") 175169689Skan 176169689Skan;; fdiv, fsqrt, frsqrt 177169689Skan(define_insn_reservation "r5kf_fdiv_sf" 17 178169689Skan (and (eq_attr "cpu" "5kf") 179169689Skan (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 180169689Skan (eq_attr "mode" "SF"))) 181169689Skan "r5kf_fpu_arith*14") 182169689Skan 183169689Skan(define_insn_reservation "r5kf_fdiv_df" 32 184169689Skan (and (eq_attr "cpu" "5kf") 185169689Skan (and (eq_attr "type" "fdiv,fsqrt") 186169689Skan (eq_attr "mode" "DF"))) 187169689Skan "r5kf_fpu_arith*29") 188169689Skan 189169689Skan;; frsqrt 190169689Skan(define_insn_reservation "r5kf_frsqrt_df" 35 191169689Skan (and (eq_attr "cpu" "5kf") 192169689Skan (and (eq_attr "type" "frsqrt") 193169689Skan (eq_attr "mode" "DF"))) 194169689Skan "r5kf_fpu_arith*31") 195169689Skan 196169689Skan;; fcmp 197169689Skan(define_insn_reservation "r5kf_fcmp" 2 198169689Skan (and (eq_attr "cpu" "5kf") 199169689Skan (eq_attr "type" "fcmp")) 200169689Skan "r5kf_fpu_arith") 201169689Skan 202169689Skan;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on condition) 203169689Skan(define_bypass 1 "r5kf_fcmp" "r5kf_fmove") 204169689Skan 205169689Skan;; fcvt (cvt.d.s, cvt.[sd].[wl] 206169689Skan(define_insn_reservation "r5kf_fcvt_d2s" 4 207169689Skan (and (eq_attr "cpu" "5kf") 208169689Skan (and (eq_attr "type" "fcvt") 209169689Skan (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 210169689Skan "r5kf_fpu_arith") 211169689Skan 212169689Skan;; fcvt (cvt.s.d) 213169689Skan(define_insn_reservation "r5kf_fcvt_s2d" 6 214169689Skan (and (eq_attr "cpu" "5kc") 215169689Skan (and (eq_attr "type" "fcvt") 216169689Skan (eq_attr "cnv_mode" "D2S"))) 217169689Skan "r5kf_fpu_arith") 218169689Skan 219169689Skan;; fcvt (cvt.[wl].[sd], etc) 220169689Skan(define_insn_reservation "r5kf_fcvt_f2i" 5 221169689Skan (and (eq_attr "cpu" "5kf") 222169689Skan (and (eq_attr "type" "fcvt") 223169689Skan (eq_attr "cnv_mode" "S2I,D2I"))) 224169689Skan "r5kf_fpu_arith") 225169689Skan 226169689Skan;; fxfer (mfc1, mfhc1, mtc1, mthc1) - single issue 227169689Skan(define_insn_reservation "r5kf_fxfer" 2 228169689Skan (and (eq_attr "cpu" "5kf") 229169689Skan (eq_attr "type" "xfer")) 230169689Skan "r5k_ixu_arith+r5kf_fpu_arith") 231