5500.md revision 169689
1169689Skan;; DFA-based pipeline description for 5500 2169689Skan(define_automaton "vr55") 3169689Skan(define_cpu_unit "vr55_dp0" "vr55") 4169689Skan(define_cpu_unit "vr55_dp1" "vr55") 5169689Skan(define_cpu_unit "vr55_mem" "vr55") 6169689Skan(define_cpu_unit "vr55_mac" "vr55") 7169689Skan(define_cpu_unit "vr55_fp" "vr55") 8169689Skan(define_cpu_unit "vr55_bru" "vr55") 9169689Skan 10169689Skan;; 11169689Skan;; The ordering of the instruction-execution-path/resource-usage 12169689Skan;; descriptions (also known as reservation RTL) is roughly ordered 13169689Skan;; based on the define attribute RTL for the "type" classification. 14169689Skan;; When modifying, remember that the first test that matches is the 15169689Skan;; reservation used! 16169689Skan;; 17169689Skan 18169689Skan(define_insn_reservation "ir_vr55_unknown" 1 19169689Skan (and (eq_attr "cpu" "r5500") 20169689Skan (eq_attr "type" "unknown")) 21169689Skan "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 22169689Skan 23169689Skan;; Assume prediction fails. 24169689Skan(define_insn_reservation "ir_vr55_branch" 2 25169689Skan (and (eq_attr "cpu" "r5500") 26169689Skan (eq_attr "type" "branch,jump,call")) 27169689Skan "vr55_bru") 28169689Skan 29169689Skan(define_insn_reservation "ir_vr55_load" 3 30169689Skan (and (eq_attr "cpu" "r5500") 31169689Skan (eq_attr "type" "load,fpload,fpidxload")) 32169689Skan "vr55_mem") 33169689Skan 34169689Skan(define_bypass 4 35169689Skan "ir_vr55_load" 36169689Skan "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 37169689Skan ir_vr55_idiv_si,ir_vr55_idiv_di") 38169689Skan 39169689Skan(define_insn_reservation "ir_vr55_store" 0 40169689Skan (and (eq_attr "cpu" "r5500") 41169689Skan (eq_attr "type" "store,fpstore,fpidxstore")) 42169689Skan "vr55_mem") 43169689Skan 44169689Skan;; This reservation is for conditional move based on integer 45169689Skan;; or floating point CC. 46169689Skan(define_insn_reservation "ir_vr55_condmove" 2 47169689Skan (and (eq_attr "cpu" "r5500") 48169689Skan (eq_attr "type" "condmove")) 49169689Skan "vr55_dp0|vr55_dp1") 50169689Skan 51169689Skan;; Move to/from FPU registers 52169689Skan(define_insn_reservation "ir_vr55_xfer" 2 53169689Skan (and (eq_attr "cpu" "r5500") 54169689Skan (eq_attr "type" "xfer")) 55169689Skan "vr55_dp0|vr55_dp1") 56169689Skan 57169689Skan(define_insn_reservation "ir_vr55_arith" 1 58169689Skan (and (eq_attr "cpu" "r5500") 59169689Skan (eq_attr "type" "arith,shift,slt,clz,const,nop,trap")) 60169689Skan "vr55_dp0|vr55_dp1") 61169689Skan 62169689Skan(define_bypass 2 63169689Skan "ir_vr55_arith" 64169689Skan "ir_vr55_mthilo,ir_vr55_imul_si,ir_vr55_imul_di,ir_vr55_imadd, 65169689Skan ir_vr55_idiv_si,ir_vr55_idiv_di") 66169689Skan 67169689Skan(define_insn_reservation "ir_vr55_mthilo" 1 68169689Skan (and (eq_attr "cpu" "r5500") 69169689Skan (eq_attr "type" "mthilo")) 70169689Skan "vr55_mac") 71169689Skan 72169689Skan(define_insn_reservation "ir_vr55_mfhilo" 5 73169689Skan (and (eq_attr "cpu" "r5500") 74169689Skan (eq_attr "type" "mfhilo")) 75169689Skan "vr55_mac") 76169689Skan 77169689Skan;; The default latency is for the GPR result of a mul. Bypasses handle the 78169689Skan;; latency of {mul,mult}->{mfhi,mflo}. 79169689Skan(define_insn_reservation "ir_vr55_imul_si" 5 80169689Skan (and (eq_attr "cpu" "r5500") 81169689Skan (and (eq_attr "type" "imul,imul3") 82169689Skan (eq_attr "mode" "SI"))) 83169689Skan "vr55_mac") 84169689Skan 85169689Skan;; The default latency is for pre-reload scheduling and handles the case 86169689Skan;; where a pseudo destination will be stored in a GPR (as it usually is). 87169689Skan;; The delay includes the latency of the dmult itself and the anticipated 88169689Skan;; mflo or mfhi. 89169689Skan;; 90169689Skan;; Once the mflo or mfhi has been created, bypasses handle the latency 91169689Skan;; between it and the dmult. 92169689Skan(define_insn_reservation "ir_vr55_imul_di" 9 93169689Skan (and (eq_attr "cpu" "r5500") 94169689Skan (and (eq_attr "type" "imul,imul3") 95169689Skan (eq_attr "mode" "DI"))) 96169689Skan "vr55_mac*4") 97169689Skan 98169689Skan;; The default latency is as for ir_vr55_imul_si. 99169689Skan(define_insn_reservation "ir_vr55_imadd" 5 100169689Skan (and (eq_attr "cpu" "r5500") 101169689Skan (eq_attr "type" "imadd")) 102169689Skan "vr55_mac") 103169689Skan 104169689Skan(define_bypass 1 105169689Skan "ir_vr55_imul_si,ir_vr55_imadd" 106169689Skan "ir_vr55_imadd" 107169689Skan "mips_linked_madd_p") 108169689Skan 109169689Skan(define_bypass 2 110169689Skan "ir_vr55_imul_si,ir_vr55_imadd" 111169689Skan "ir_vr55_mfhilo") 112169689Skan 113169689Skan(define_bypass 4 114169689Skan "ir_vr55_imul_di" 115169689Skan "ir_vr55_mfhilo") 116169689Skan 117169689Skan;; Divide algorithm is early out with best latency of 7 pcycles. 118169689Skan;; Use worst case for scheduling purposes. 119169689Skan(define_insn_reservation "ir_vr55_idiv_si" 42 120169689Skan (and (eq_attr "cpu" "r5500") 121169689Skan (and (eq_attr "type" "idiv") 122169689Skan (eq_attr "mode" "SI"))) 123169689Skan "vr55_mac") 124169689Skan 125169689Skan(define_insn_reservation "ir_vr55_idiv_di" 74 126169689Skan (and (eq_attr "cpu" "r5500") 127169689Skan (and (eq_attr "type" "idiv") 128169689Skan (eq_attr "mode" "DI"))) 129169689Skan "vr55_mac") 130169689Skan 131169689Skan(define_insn_reservation "ir_vr55_fadd" 4 132169689Skan (and (eq_attr "cpu" "r5500") 133169689Skan (eq_attr "type" "fadd")) 134169689Skan "vr55_fp") 135169689Skan 136169689Skan(define_insn_reservation "ir_vr55_fmul_sf" 5 137169689Skan (and (eq_attr "cpu" "r5500") 138169689Skan (and (eq_attr "type" "fmul") 139169689Skan (eq_attr "mode" "SF"))) 140169689Skan "vr55_mac") 141169689Skan 142169689Skan(define_insn_reservation "ir_vr55_fmul_df" 6 143169689Skan (and (eq_attr "cpu" "r5500") 144169689Skan (and (eq_attr "type" "fmul") 145169689Skan (eq_attr "mode" "DF"))) 146169689Skan "vr55_mac") 147169689Skan 148169689Skan(define_insn_reservation "ir_vr55_fmadd_sf" 9 149169689Skan (and (eq_attr "cpu" "r5500") 150169689Skan (and (eq_attr "type" "fmadd") 151169689Skan (eq_attr "mode" "SF"))) 152169689Skan "vr55_mac") 153169689Skan 154169689Skan(define_insn_reservation "ir_vr55_fmadd_df" 10 155169689Skan (and (eq_attr "cpu" "r5500") 156169689Skan (and (eq_attr "type" "fmadd") 157169689Skan (eq_attr "mode" "DF"))) 158169689Skan "vr55_mac") 159169689Skan 160169689Skan(define_insn_reservation "ir_vr55_fdiv_sf" 30 161169689Skan (and (eq_attr "cpu" "r5500") 162169689Skan (and (eq_attr "type" "fdiv,frdiv,fsqrt") 163169689Skan (eq_attr "mode" "SF"))) 164169689Skan "vr55_mac") 165169689Skan 166169689Skan(define_insn_reservation "ir_vr55_fdiv_df" 59 167169689Skan (and (eq_attr "cpu" "r5500") 168169689Skan (and (eq_attr "type" "fdiv,frdiv,fsqrt") 169169689Skan (eq_attr "mode" "DF"))) 170169689Skan "vr55_mac") 171169689Skan 172169689Skan(define_insn_reservation "ir_vr55_fabs" 2 173169689Skan (and (eq_attr "cpu" "r5500") 174169689Skan (eq_attr "type" "fabs,fneg,fmove")) 175169689Skan "vr55_fp") 176169689Skan 177169689Skan(define_insn_reservation "ir_vr55_fcmp" 2 178169689Skan (and (eq_attr "cpu" "r5500") 179169689Skan (eq_attr "type" "fcmp")) 180169689Skan "vr55_fp") 181169689Skan 182169689Skan(define_insn_reservation "ir_vr55_fcvt_sf" 4 183169689Skan (and (eq_attr "cpu" "r5500") 184169689Skan (and (eq_attr "type" "fcvt") 185169689Skan (eq_attr "mode" "SF"))) 186169689Skan "vr55_fp") 187169689Skan 188169689Skan(define_insn_reservation "ir_vr55_fcvt_df" 6 189169689Skan (and (eq_attr "cpu" "r5500") 190169689Skan (and (eq_attr "type" "fcvt") 191169689Skan (eq_attr "mode" "DF"))) 192169689Skan "vr55_fp") 193169689Skan 194169689Skan(define_insn_reservation "ir_vr55_frsqrt_sf" 60 195169689Skan (and (eq_attr "cpu" "r5500") 196169689Skan (and (eq_attr "type" "frsqrt") 197169689Skan (eq_attr "mode" "SF"))) 198169689Skan "vr55_mac") 199169689Skan 200169689Skan(define_insn_reservation "ir_vr55_frsqrt_df" 118 201169689Skan (and (eq_attr "cpu" "r5500") 202169689Skan (and (eq_attr "type" "frsqrt") 203169689Skan (eq_attr "mode" "DF"))) 204169689Skan "vr55_mac") 205169689Skan 206169689Skan(define_insn_reservation "ir_vr55_multi" 1 207169689Skan (and (eq_attr "cpu" "r5500") 208169689Skan (eq_attr "type" "multi")) 209169689Skan "vr55_dp0+vr55_dp1+vr55_mem+vr55_mac+vr55_fp+vr55_bru") 210