5000.md revision 169690 
1227825Stheraven;; VR5000 pipeline description.
2227825Stheraven;;   Copyright (C) 2004, 2005 Free Software Foundation, Inc.
3227825Stheraven;;
4227825Stheraven;; This file is part of GCC.
5227825Stheraven
6227825Stheraven;; GCC is free software; you can redistribute it and/or modify it
7227825Stheraven;; under the terms of the GNU General Public License as published
8227825Stheraven;; by the Free Software Foundation; either version 2, or (at your
9227825Stheraven;; option) any later version.
10227825Stheraven
11227825Stheraven;; GCC is distributed in the hope that it will be useful, but WITHOUT
12227825Stheraven;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13227825Stheraven;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
14227825Stheraven;; License for more details.
15227825Stheraven
16227825Stheraven;; You should have received a copy of the GNU General Public License
17227825Stheraven;; along with GCC; see the file COPYING.  If not, write to the
18227825Stheraven;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
19227825Stheraven;; MA 02110-1301, USA.
20227825Stheraven
21227825Stheraven
22227825Stheraven;; This file overrides parts of generic.md.  It is derived from the
23227825Stheraven;; old define_function_unit description.
24227825Stheraven
25227825Stheraven(define_insn_reservation "r5k_load" 2
26227825Stheraven  (and (eq_attr "cpu" "r5000")
27227825Stheraven       (eq_attr "type" "load,fpload,fpidxload,xfer"))
28227825Stheraven  "alu")
29227825Stheraven
30227825Stheraven(define_insn_reservation "r5k_imul_si" 5
31227825Stheraven  (and (eq_attr "cpu" "r5000")
32227825Stheraven       (and (eq_attr "type" "imul,imul3,imadd")
33227825Stheraven	    (eq_attr "mode" "SI")))
34227825Stheraven  "imuldiv*5")
35227825Stheraven
36227825Stheraven(define_insn_reservation "r5k_imul_di" 9
37227825Stheraven  (and (eq_attr "cpu" "r5000")
38227825Stheraven       (and (eq_attr "type" "imul,imul3,imadd")
39227825Stheraven	    (eq_attr "mode" "DI")))
40227825Stheraven  "imuldiv*9")
41262801Sdim
42262801Sdim(define_insn_reservation "r5k_idiv_si" 36
43227825Stheraven  (and (eq_attr "cpu" "r5000")
44262801Sdim       (and (eq_attr "type" "idiv")
45227825Stheraven	    (eq_attr "mode" "SI")))
46227825Stheraven  "imuldiv*36")
47227825Stheraven
48227825Stheraven(define_insn_reservation "r5k_idiv_di" 68
49227825Stheraven  (and (eq_attr "cpu" "r5000")
50227825Stheraven       (and (eq_attr "type" "idiv")
51227825Stheraven	    (eq_attr "mode" "DI")))
52227825Stheraven  "imuldiv*68")
53262801Sdim
54227825Stheraven(define_insn_reservation "r5k_fmove" 1
55227825Stheraven  (and (eq_attr "cpu" "r5000")
56227825Stheraven       (eq_attr "type" "fcmp,fabs,fneg,fmove"))
57227825Stheraven  "alu")
58227825Stheraven
59227825Stheraven(define_insn_reservation "r5k_fmul_single" 4
60227825Stheraven  (and (eq_attr "cpu" "r5000")
61227825Stheraven       (and (eq_attr "type" "fmul,fmadd")
62227825Stheraven	    (eq_attr "mode" "SF")))
63227825Stheraven  "alu")
64227825Stheraven
65227825Stheraven(define_insn_reservation "r5k_fmul_double" 5
66227825Stheraven  (and (eq_attr "cpu" "r5000")
67227825Stheraven       (and (eq_attr "type" "fmul,fmadd")
68227825Stheraven	    (eq_attr "mode" "DF")))
69262801Sdim  "alu")
70262801Sdim
71262801Sdim(define_insn_reservation "r5k_fdiv_single" 21
72262801Sdim  (and (eq_attr "cpu" "r5000")
73227825Stheraven       (and (eq_attr "type" "fdiv,frdiv,fsqrt,frsqrt")
74227825Stheraven	    (eq_attr "mode" "SF")))
75227825Stheraven  "alu")
76227825Stheraven
77227825Stheraven(define_insn_reservation "r5k_fsqrt_double" 36
78227825Stheraven  (and (eq_attr "cpu" "r5000")
79227825Stheraven       (and (eq_attr "type" "fsqrt,frsqrt")
80227825Stheraven	    (eq_attr "mode" "DF")))
81227825Stheraven  "alu")
82227825Stheraven