1169689Skan;; DFA-based pipeline descriptions for MIPS32 4K processor family 2169689Skan;; Contributed by Nigel Stephens (nigel@mips.com) 3169689Skan;; and David Ung (davidu@mips.com) 4169689Skan;; 5169689Skan;; References: 6169689Skan;; "MIPS32 4K Processor Core Family Software User's Manual, 7169689Skan;; Doc no: MD00016, Rev 1.18, Nov 15, 2004." 8169689Skan;; 9169689Skan;; 4Kc - pipelined multiplier and translation lookaside buffer (TLB) 10169689Skan;; 4km - pipelined multiplier and block address translator (BAT) 11169689Skan;; 4kp - non-pipelined multiplier and block address translator (BAT) 12169689Skan;; 13169689Skan;; Copyright (C) 2005 Free Software Foundation, Inc. 14169689Skan;; 15169689Skan;; This file is part of GCC. 16169689Skan;; 17169689Skan;; GCC is free software; you can redistribute it and/or modify it 18169689Skan;; under the terms of the GNU General Public License as published 19169689Skan;; by the Free Software Foundation; either version 2, or (at your 20169689Skan;; option) any later version. 21169689Skan 22169689Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 23169689Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 24169689Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 25169689Skan;; License for more details. 26169689Skan 27169689Skan;; You should have received a copy of the GNU General Public License 28169689Skan;; along with GCC; see the file COPYING. If not, write to the 29169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 30169689Skan;; MA 02110-1301, USA. 31169689Skan 32169689Skan(define_automaton "r4k_cpu, r4k_mdu") 33169689Skan 34169689Skan;; Integer execution unit. 35169689Skan(define_cpu_unit "r4k_ixu_arith" "r4k_cpu") 36169689Skan(define_cpu_unit "r4k_ixu_mpydiv" "r4k_mdu") 37169689Skan 38169689Skan(define_insn_reservation "r4k_int_load" 2 39169689Skan (and (eq_attr "cpu" "4kc,4kp") 40169689Skan (eq_attr "type" "load")) 41169689Skan "r4k_ixu_arith") 42169689Skan 43169689Skan(define_insn_reservation "r4k_int_prefetch" 1 44169689Skan (and (eq_attr "cpu" "4kc,4kp") 45169689Skan (eq_attr "type" "prefetch")) 46169689Skan "r4k_ixu_arith") 47169689Skan 48169689Skan(define_insn_reservation "r4k_int_store" 1 49169689Skan (and (eq_attr "cpu" "4kc,4kp") 50169689Skan (eq_attr "type" "store")) 51169689Skan "r4k_ixu_arith") 52169689Skan 53169689Skan;; 4Kc/4Km 54169689Skan;; unsigned divide - 8/16/24/32 bit operand have latencies 9/17/25/33 55169689Skan;; signed divide - 8/16/24/32 bit operand have latencies 10/18/26/34 56169689Skan(define_insn_reservation "r4k_idiv_4kc" 34 57169689Skan (and (eq_attr "cpu" "4kc") 58169689Skan (and (eq_attr "type" "idiv") 59169689Skan (eq_attr "mode" "!DI"))) 60169689Skan "r4k_ixu_arith+(r4k_ixu_mpydiv*34)") 61169689Skan 62169689Skan;; 4Kp 63169689Skan;; unsigned divide - 33 64169689Skan;; signed divide - 33-35 65169689Skan(define_insn_reservation "r4k_idiv_4kp" 35 66169689Skan (and (eq_attr "cpu" "4kp") 67169689Skan (and (eq_attr "type" "idiv") 68169689Skan (eq_attr "mode" "!DI"))) 69169689Skan "r4k_ixu_arith+(r4k_ixu_mpydiv*35)") 70169689Skan 71169689Skan;; 4Kc/4Km fast 32x32 multiply 72169689Skan;; 16x32 is faster, but there's no way to detect this 73169689Skan(define_insn_reservation "r4k_mult_4kc" 2 74169689Skan (and (eq_attr "cpu" "4kc") 75169689Skan (and (eq_attr "type" "imul,imadd") 76169689Skan (eq_attr "mode" "SI"))) 77169689Skan "r4k_ixu_arith+(r4k_ixu_mpydiv*2)") 78169689Skan 79169689Skan;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will 80169689Skan;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall, 81169689Skan;; while MUL 32x32 forces 2 cycle stall. If next insn use the result, an 82169689Skan;; additional stall is forced. 83169689Skan(define_insn_reservation "r4k_mul_4kc" 4 84169689Skan (and (eq_attr "cpu" "4kc") 85169689Skan (and (eq_attr "type" "imul3") 86169689Skan (eq_attr "mode" "SI"))) 87169689Skan "(r4k_ixu_arith+r4k_ixu_mpydiv)*3") 88169689Skan 89169689Skan;; 4Kp slow iterative 2-op MULT 90169689Skan;; Latency of 32 if next insn is MADD/MSUB,MFHI/MFLO. 91169689Skan;; Repeat rate of 33 cycles. 92169689Skan(define_insn_reservation "r4k_mult_4kp" 32 93169689Skan (and (eq_attr "cpu" "4kp") 94169689Skan (and (eq_attr "type" "imul") 95169689Skan (eq_attr "mode" "SI"))) 96169689Skan "r4k_ixu_arith+(r4k_ixu_mpydiv*32)") 97169689Skan 98169689Skan;; 4Kp slow iterative 3-op MUL 99169689Skan;; Latency of 32 cycles, but stalls the whole pipeline until complete. 100169689Skan(define_insn_reservation "r4k_mul_4kp" 32 101169689Skan (and (eq_attr "cpu" "4kp") 102169689Skan (and (eq_attr "type" "imul3") 103169689Skan (eq_attr "mode" "SI"))) 104169689Skan "(r4k_ixu_arith+r4k_ixu_mpydiv)*32") 105169689Skan 106169689Skan;; 4Kp slow iterative MADD 107169689Skan;; Latency of 34 if next use insn is MADD/MSUB,MFHI/MFLO. 108169689Skan;; Repeat rate of 35 cycles. 109169689Skan(define_insn_reservation "r4k_madd_4kp" 34 110169689Skan (and (eq_attr "cpu" "4kp") 111169689Skan (and (eq_attr "type" "imadd") 112169689Skan (eq_attr "mode" "SI"))) 113169689Skan "r4k_ixu_arith+(r4k_ixu_mpydiv*34)") 114169689Skan 115169689Skan;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency. 116169689Skan(define_insn_reservation "r4k_int_mthilo" 1 117169689Skan (and (eq_attr "cpu" "4kc,4kp") 118169689Skan (eq_attr "type" "mthilo")) 119169689Skan "r4k_ixu_arith+r4k_ixu_mpydiv") 120169689Skan 121169689Skan;; Move from HI/LO -> integer operation has a 2 cycle latency. 122169689Skan(define_insn_reservation "r4k_int_mfhilo" 2 123169689Skan (and (eq_attr "cpu" "4kc,4kp") 124169689Skan (eq_attr "type" "mfhilo")) 125169689Skan "r4k_ixu_arith+r4k_ixu_mpydiv") 126169689Skan 127169689Skan;; All other integer insns. 128169689Skan(define_insn_reservation "r4k_int_alu" 1 129169689Skan (and (eq_attr "cpu" "4kc,4kp") 130169689Skan (eq_attr "type" "arith,condmove,shift,const,nop,slt")) 131169689Skan "r4k_ixu_arith") 132169689Skan 133169689Skan(define_insn_reservation "r4k_int_branch" 1 134169689Skan (and (eq_attr "cpu" "4kc,4kp") 135169689Skan (eq_attr "type" "branch")) 136169689Skan "r4k_ixu_arith") 137169689Skan 138169689Skan(define_insn_reservation "r4k_int_jump_4k" 1 139169689Skan (and (eq_attr "cpu" "4kc,4kp") 140169689Skan (eq_attr "type" "jump,call")) 141169689Skan "r4k_ixu_arith") 142169689Skan 143169689Skan;; mfcx/mtcx - non FPU 144169689Skan;; (Disabled until we add cop0 support) 145169689Skan;; (define_insn_reservation "r4k_int_cop" 2 146169689Skan;; (and (eq_attr "cpu" "4kc,4kp") 147169689Skan;; (eq_attr "type" "cop0")) 148169689Skan;; "r4k_ixu_arith") 149169689Skan 150169689Skan;; Unknown or multi - single issue 151169689Skan(define_insn_reservation "r4k_unknown" 1 152169689Skan (and (eq_attr "cpu" "4kc,4kp") 153169689Skan (eq_attr "type" "unknown,multi")) 154169689Skan "r4k_ixu_arith+r4k_ixu_mpydiv") 155