4130.md revision 169689
1;; 2;; Pipeline description for the VR4130 family. 3;; 4;; The processor issues each 8-byte aligned pair of instructions together, 5;; stalling the second instruction if it depends on the first. Thus, if we 6;; want two instructions to issue in parallel, we need to make sure that the 7;; first one is 8-byte aligned. 8;; 9;; For the purposes of this pipeline description, we treat the processor 10;; like a standard two-way superscalar architecture. If scheduling were 11;; the last pass to run, we could use the scheduler hooks to vary the 12;; issue rate depending on whether an instruction is at an aligned or 13;; unaligned address. Unfortunately, delayed branch scheduling and 14;; hazard avoidance are done after the final scheduling pass, and they 15;; can change the addresses of many instructions. 16;; 17;; We get around this in two ways: 18;; 19;; (1) By running an extra pass at the end of compilation. This pass goes 20;; through the function looking for pairs of instructions that could 21;; execute in parallel. It makes sure that the first instruction in 22;; each pair is suitably aligned, inserting nops if necessary. Doing 23;; this gives the same kind of pipeline behavior we would see on a 24;; normal superscalar target. 25;; 26;; This pass is generally a speed improvement, but the extra nops will 27;; obviously make the program bigger. It is therefore unsuitable for 28;; -Os (at the very least). 29;; 30;; (2) By modifying the scheduler hooks so that, where possible: 31;; 32;; (a) dependent instructions are separated by a non-dependent 33;; instruction; 34;; 35;; (b) instructions that use the multiplication unit are separated 36;; by non-multiplication instructions; and 37;; 38;; (c) memory access instructions are separated by non-memory 39;; instructions. 40;; 41;; The idea is to keep conflicting instructions apart wherever possible 42;; and thus make the schedule less dependent on alignment. 43 44(define_automaton "vr4130_main, vr4130_muldiv, vr4130_mulpre") 45 46(define_cpu_unit "vr4130_alu1, vr4130_alu2, vr4130_dcache" "vr4130_main") 47(define_cpu_unit "vr4130_muldiv" "vr4130_muldiv") 48 49;; This is a fake unit for pre-reload scheduling of multiplications. 50;; It enforces the true post-reload repeat rate. 51(define_cpu_unit "vr4130_mulpre" "vr4130_mulpre") 52 53;; The scheduling hooks use this attribute for (b) above. 54(define_attr "vr4130_class" "mul,mem,alu" 55 (cond [(eq_attr "type" "load,store") 56 (const_string "mem") 57 58 (eq_attr "type" "mfhilo,mthilo,imul,imul3,imadd,idiv") 59 (const_string "mul")] 60 (const_string "alu"))) 61 62(define_insn_reservation "vr4130_multi" 1 63 (and (eq_attr "cpu" "r4130") 64 (eq_attr "type" "multi,unknown")) 65 "vr4130_alu1 + vr4130_alu2 + vr4130_dcache + vr4130_muldiv") 66 67(define_insn_reservation "vr4130_int" 1 68 (and (eq_attr "cpu" "r4130") 69 (eq_attr "type" "const,arith,shift,slt,nop")) 70 "vr4130_alu1 | vr4130_alu2") 71 72(define_insn_reservation "vr4130_load" 3 73 (and (eq_attr "cpu" "r4130") 74 (eq_attr "type" "load")) 75 "vr4130_dcache") 76 77(define_insn_reservation "vr4130_store" 1 78 (and (eq_attr "cpu" "r4130") 79 (eq_attr "type" "store")) 80 "vr4130_dcache") 81 82(define_insn_reservation "vr4130_mfhilo" 3 83 (and (eq_attr "cpu" "r4130") 84 (eq_attr "type" "mfhilo")) 85 "vr4130_muldiv") 86 87(define_insn_reservation "vr4130_mthilo" 1 88 (and (eq_attr "cpu" "r4130") 89 (eq_attr "type" "mthilo")) 90 "vr4130_muldiv") 91 92;; The product is available in LO & HI after one cycle. Moving the result 93;; into an integer register will take an additional three cycles, see mflo 94;; & mfhi above. Note that the same latencies and repeat rates apply if we 95;; use "mtlo; macc" instead of "mult; mflo". 96(define_insn_reservation "vr4130_mulsi" 4 97 (and (eq_attr "cpu" "r4130") 98 (and (eq_attr "type" "imul,imul3") 99 (eq_attr "mode" "SI"))) 100 "vr4130_muldiv + (vr4130_mulpre * 2)") 101 102;; As for vr4130_mulsi, but the product is available in LO and HI 103;; after 3 cycles. 104(define_insn_reservation "vr4130_muldi" 6 105 (and (eq_attr "cpu" "r4130") 106 (and (eq_attr "type" "imul,imul3") 107 (eq_attr "mode" "DI"))) 108 "(vr4130_muldiv * 3) + (vr4130_mulpre * 4)") 109 110;; maccs can execute in consecutive cycles without stalling, but it 111;; is 3 cycles before the integer destination can be read. 112(define_insn_reservation "vr4130_macc" 3 113 (and (eq_attr "cpu" "r4130") 114 (eq_attr "type" "imadd")) 115 "vr4130_muldiv") 116 117(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_macc" "mips_linked_madd_p") 118(define_bypass 1 "vr4130_mulsi,vr4130_macc" "vr4130_mfhilo") 119(define_bypass 3 "vr4130_muldi" "vr4130_mfhilo") 120 121(define_insn_reservation "vr4130_divsi" 36 122 (and (eq_attr "cpu" "r4130") 123 (and (eq_attr "type" "idiv") 124 (eq_attr "mode" "SI"))) 125 "vr4130_muldiv * 36") 126 127(define_insn_reservation "vr4130_divdi" 72 128 (and (eq_attr "cpu" "r4130") 129 (and (eq_attr "type" "idiv") 130 (eq_attr "mode" "DI"))) 131 "vr4130_muldiv * 72") 132 133(define_insn_reservation "vr4130_branch" 0 134 (and (eq_attr "cpu" "r4130") 135 (eq_attr "type" "branch,jump,call")) 136 "vr4130_alu1 | vr4130_alu2") 137