24k.md revision 296373
155714Skris;; DFA-based pipeline descriptions for MIPS Technologies 24K core. 2160814Ssimon;; Contributed by Chao-ying Fu (fu@mips.com), Nigel Stephens (nigel@mips.com) 3160814Ssimon;; and David Ung (davidu@mips.com) 4160814Ssimon;; 5160814Ssimon;; The 24K is a single-issue processor with a half-clocked fpu. 6160814Ssimon;; The 24Kx is 24k with 1:1 clocked fpu. 7160814Ssimon;; 8160814Ssimon;; References: 9160814Ssimon;; "MIPS32 24K Processor Core Family Software User's Manual, Rev 3.04." 10160814Ssimon;; 11160814Ssimon;; Copyright (C) 2005 Free Software Foundation, Inc. 12160814Ssimon;; 13160814Ssimon;; This file is part of GCC. 14160814Ssimon;; 15160814Ssimon;; GCC is free software; you can redistribute it and/or modify it 16160814Ssimon;; under the terms of the GNU General Public License as published 17160814Ssimon;; by the Free Software Foundation; either version 2, or (at your 18160814Ssimon;; option) any later version. 19160814Ssimon 20160814Ssimon;; GCC is distributed in the hope that it will be useful, but WITHOUT 21160814Ssimon;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 22160814Ssimon;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 23160814Ssimon;; License for more details. 24160814Ssimon 25160814Ssimon;; You should have received a copy of the GNU General Public License 26160814Ssimon;; along with GCC; see the file COPYING. If not, write to the 27160814Ssimon;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 28160814Ssimon;; MA 02110-1301, USA. 29160814Ssimon 30160814Ssimon(define_automaton "r24k_cpu, r24k_mdu, r24k_fpu") 31160814Ssimon 32160814Ssimon;; Integer execution unit. 33160814Ssimon(define_cpu_unit "r24k_iss" "r24k_cpu") 34160814Ssimon(define_cpu_unit "r24k_ixu_arith" "r24k_cpu") 35160814Ssimon(define_cpu_unit "r24k_mul3a" "r24k_mdu") 36160814Ssimon(define_cpu_unit "r24k_mul3b" "r24k_mdu") 37160814Ssimon(define_cpu_unit "r24k_mul3c" "r24k_mdu") 38160814Ssimon 39160814Ssimon;; -------------------------------------------------------------- 40160814Ssimon;; Producers 41160814Ssimon;; -------------------------------------------------------------- 42160814Ssimon 43160814Ssimon;; 1. Loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs 44160814Ssimon(define_insn_reservation "r24k_int_load" 2 45160814Ssimon (and (eq_attr "cpu" "24k,24kx") 46160814Ssimon (eq_attr "type" "load")) 47160814Ssimon "r24k_iss+r24k_ixu_arith") 48160814Ssimon 49160814Ssimon 50160814Ssimon;; 2. Arithmetic: add, addi, addiu, addiupc, addu, and, andi, clo, clz, 51160814Ssimon;; ext, ins, lui, movn, movz, nor, or, ori, rotr, rotrv, seb, seh, sll, 52160814Ssimon;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh, 53160814Ssimon;; xor, xori 54160814Ssimon;; (movn/movz is not matched, we'll need to split condmov to 5555714Skris;; differentiate between integer/float moves) 5655714Skris(define_insn_reservation "r24k_int_arith" 1 5755714Skris (and (eq_attr "cpu" "24k,24kx") 5855714Skris (eq_attr "type" "arith,const,nop,shift,slt")) 5955714Skris "r24k_iss+r24k_ixu_arith") 6055714Skris 6155714Skris 6255714Skris;; 3. Links: bgezal, bgezall, bltzal, bltzall, jal, jalr, jalx 6355714Skris;; 3a. jr/jalr consumer 6455714Skris(define_insn_reservation "r24k_int_jump" 1 6555714Skris (and (eq_attr "cpu" "24k,24kx") 6655714Skris (eq_attr "type" "call,jump")) 6755714Skris "r24k_iss+r24k_ixu_arith") 6855714Skris 6955714Skris;; 3b. branch consumer 7055714Skris(define_insn_reservation "r24k_int_branch" 1 7155714Skris (and (eq_attr "cpu" "24k,24kx") 7255714Skris (eq_attr "type" "branch")) 7355714Skris "r24k_iss+r24k_ixu_arith") 7455714Skris 7555714Skris 7655714Skris;; 4. MDU: fully pipelined multiplier 7755714Skris;; mult - delivers result to hi/lo in 1 cycle (pipelined) 7855714Skris(define_insn_reservation "r24k_int_mult" 1 7955714Skris (and (eq_attr "cpu" "24k,24kx") 8055714Skris (eq_attr "type" "imul")) 8155714Skris "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 8255714Skris 8355714Skris;; madd, msub - delivers result to hi/lo in 1 cycle (pipelined) 8455714Skris(define_insn_reservation "r24k_int_madd" 1 8555714Skris (and (eq_attr "cpu" "24k,24kx") 8655714Skris (eq_attr "type" "imadd")) 8755714Skris "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 8855714Skris 8955714Skris;; mul - delivers result to gpr in 5 cycles 9055714Skris(define_insn_reservation "r24k_int_mul3" 5 9155714Skris (and (eq_attr "cpu" "24k,24kx") 9255714Skris (eq_attr "type" "imul3")) 9355714Skris "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)*5") 9455714Skris 9555714Skris;; mfhi, mflo, mflhxu - deliver result to gpr in 5 cycles 9655714Skris(define_insn_reservation "r24k_int_mfhilo" 5 9755714Skris (and (eq_attr "cpu" "24k,24kx") 9855714Skris (eq_attr "type" "mfhilo")) 9955714Skris "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 10055714Skris 10155714Skris;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass 10255714Skris(define_insn_reservation "r24k_int_mthilo" 1 10355714Skris (and (eq_attr "cpu" "24k,24kx") 10455714Skris (eq_attr "type" "mthilo")) 10555714Skris "r24k_iss+(r24k_mul3a|r24k_mul3b|r24k_mul3c)") 10655714Skris 10755714Skris;; div - default to 36 cycles for 32bit operands. Faster for 24bit, 16bit and 10855714Skris;; 8bit, but is tricky to identify. 10955714Skris(define_insn_reservation "r24k_int_div" 36 11055714Skris (and (eq_attr "cpu" "24k,24kx") 111160814Ssimon (eq_attr "type" "idiv")) 112160814Ssimon "r24k_iss+(r24k_mul3a+r24k_mul3b+r24k_mul3c)*36") 113160814Ssimon 114160814Ssimon 115160814Ssimon;; 5. Cop: cfc1, di, ei, mfc0, mtc0 11655714Skris;; (Disabled until we add proper cop0 support) 11755714Skris;;(define_insn_reservation "r24k_int_cop" 3 11855714Skris;; (and (eq_attr "cpu" "24k,24kx") 11955714Skris;; (eq_attr "type" "cop0")) 12059191Skris;; "r24k_iss+r24k_ixu_arith") 12159191Skris 122160814Ssimon 123160814Ssimon;; 6. Store 124109998Smarkm(define_insn_reservation "r24k_int_store" 1 12555714Skris (and (eq_attr "cpu" "24k,24kx") 12655714Skris (and (eq_attr "type" "store") 12755714Skris (eq_attr "mode" "!unknown"))) 12855714Skris "r24k_iss+r24k_ixu_arith") 12959191Skris 13055714Skris;; 6.1 Special case - matches the cprestore pattern which don't set the mode 131160814Ssimon;; attrib. This avoids being set as r24k_int_store and have it checked 13255714Skris;; against store_data_bypass_p, which would then fail because cprestore 13355714Skris;; does not have a normal SET pattern. 13455714Skris(define_insn_reservation "r24k_unknown_store" 1 13555714Skris (and (eq_attr "cpu" "24k,24kx") 13655714Skris (and (eq_attr "type" "store") 13768651Skris (eq_attr "mode" "unknown"))) 13868651Skris "r24k_iss+r24k_ixu_arith") 13968651Skris 14068651Skris 14168651Skris;; 7. Multiple instructions 14268651Skris(define_insn_reservation "r24k_int_multi" 1 14359191Skris (and (eq_attr "cpu" "24k,24kx") 14459191Skris (eq_attr "type" "multi")) 14555714Skris "r24k_iss+r24k_ixu_arith+r24k_fpu_arith+(r24k_mul3a+r24k_mul3b+r24k_mul3c)") 14655714Skris 14755714Skris 14855714Skris;; 8. Unknowns - Currently these include blockage, consttable and alignment 14955714Skris;; rtls. They do not really affect scheduling latency, (blockage affects 15055714Skris;; scheduling via log links, but not used here). 15155714Skris(define_insn_reservation "r24k_int_unknown" 0 15255714Skris (and (eq_attr "cpu" "24k,24kx") 15355714Skris (eq_attr "type" "unknown")) 154109998Smarkm "r24k_iss") 15555714Skris 156160814Ssimon 157160814Ssimon;; 9. Prefetch 158160814Ssimon(define_insn_reservation "r24k_int_prefetch" 1 159160814Ssimon (and (eq_attr "cpu" "24k,24kx") 160160814Ssimon (eq_attr "type" "prefetch,prefetchx")) 161160814Ssimon "r24k_iss+r24k_ixu_arith") 162160814Ssimon 163160814Ssimon 164160814Ssimon;; -------------------------------------------------------------- 165160814Ssimon;; Bypass to Consumer 166160814Ssimon;; -------------------------------------------------------------- 167160814Ssimon 168160814Ssimon;; load->next use : 2 cycles (Default) 169160814Ssimon;; load->load base: 3 cycles 170160814Ssimon;; load->store base: 3 cycles 171160814Ssimon;; load->prefetch: 3 cycles 172160814Ssimon(define_bypass 3 "r24k_int_load" "r24k_int_load") 173160814Ssimon(define_bypass 3 "r24k_int_load" "r24k_int_store" "!store_data_bypass_p") 174160814Ssimon(define_bypass 3 "r24k_int_load" "r24k_int_prefetch") 175160814Ssimon 176160814Ssimon;; arith->next use : 1 cycles (Default) 177160814Ssimon;; arith->load base: 2 cycles 178160814Ssimon;; arith->store base: 2 cycles 179160814Ssimon;; arith->prefetch: 2 cycles 18055714Skris(define_bypass 2 "r24k_int_arith" "r24k_int_load") 18155714Skris(define_bypass 2 "r24k_int_arith" "r24k_int_store" "!store_data_bypass_p") 18255714Skris(define_bypass 2 "r24k_int_arith" "r24k_int_prefetch") 18355714Skris 184160814Ssimon;; mul3->next use : 5 cycles (default) 185160814Ssimon;; mul3->l/s base : 6 cycles 186160814Ssimon;; mul3->prefetch : 6 cycles 187160814Ssimon(define_bypass 6 "r24k_int_mul3" "r24k_int_load") 188160814Ssimon(define_bypass 6 "r24k_int_mul3" "r24k_int_store" "!store_data_bypass_p") 18955714Skris(define_bypass 6 "r24k_int_mul3" "r24k_int_prefetch") 19055714Skris 19155714Skris;; mfhilo->next use : 5 cycles (default) 19255714Skris;; mfhilo->l/s base : 6 cycles 19355714Skris;; mfhilo->prefetch : 6 cycles 194109998Smarkm;; mthilo->madd/msub : 2 cycle (only for mthi/lo not mfhi/lo) 195109998Smarkm(define_bypass 6 "r24k_int_mfhilo" "r24k_int_load") 196109998Smarkm(define_bypass 6 "r24k_int_mfhilo" "r24k_int_store" "!store_data_bypass_p") 197109998Smarkm(define_bypass 6 "r24k_int_mfhilo" "r24k_int_prefetch") 198109998Smarkm(define_bypass 2 "r24k_int_mthilo" "r24k_int_madd") 199109998Smarkm 200109998Smarkm;; cop->next use : 3 cycles (Default) 201109998Smarkm;; cop->l/s base : 4 cycles 202109998Smarkm;; (define_bypass 4 "r24k_int_cop" "r24k_int_load") 203109998Smarkm;; (define_bypass 4 "r24k_int_cop" "r24k_int_store" "!store_data_bypass_p") 204109998Smarkm 205109998Smarkm;; multi->next use : 1 cycles (Default) 206109998Smarkm;; multi->l/s base : 2 cycles 207109998Smarkm;; multi->prefetch : 2 cycles 208109998Smarkm(define_bypass 2 "r24k_int_multi" "r24k_int_load") 209109998Smarkm(define_bypass 2 "r24k_int_multi" "r24k_int_store" "!store_data_bypass_p") 210109998Smarkm(define_bypass 2 "r24k_int_multi" "r24k_int_prefetch") 211109998Smarkm 212109998Smarkm 213109998Smarkm;; -------------------------------------------------------------- 214109998Smarkm;; Floating Point Instructions 215160814Ssimon;; -------------------------------------------------------------- 216160814Ssimon 217160814Ssimon(define_cpu_unit "r24k_fpu_arith" "r24k_fpu") 218160814Ssimon 219160814Ssimon;; The 24k is a single issue cpu, and the fpu runs at half clock speed, 220160814Ssimon;; so each fpu instruction ties up the shared instruction scheduler for 221160814Ssimon;; 1 cycle, and the fpu scheduler for 2 cycles. 222194206Ssimon;; 223160814Ssimon;; These timings are therefore twice the values in the 24K manual, 224194206Ssimon;; which are quoted in fpu clocks. 225194206Ssimon;; 226194206Ssimon;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use 227194206Ssimon;; the unscaled timings 228194206Ssimon 22955714Skris(define_reservation "r24k_fpu_iss" "r24k_iss+(r24k_fpu_arith*2)") 23055714Skris 23155714Skris;; fadd, fabs, fneg 23255714Skris(define_insn_reservation "r24k_fadd" 8 23355714Skris (and (eq_attr "cpu" "24k") 23455714Skris (eq_attr "type" "fadd,fabs,fneg")) 235109998Smarkm "r24k_fpu_iss") 23655714Skris 23755714Skris;; fmove, fcmove 23855714Skris(define_insn_reservation "r24k_fmove" 8 23955714Skris (and (eq_attr "cpu" "24k") 24055714Skris (eq_attr "type" "fmove,condmove")) 24155714Skris "r24k_fpu_iss") 24255714Skris 24355714Skris;; fload 24455714Skris(define_insn_reservation "r24k_fload" 6 24555714Skris (and (eq_attr "cpu" "24k") 24655714Skris (eq_attr "type" "fpload,fpidxload")) 24755714Skris "r24k_fpu_iss") 24855714Skris 24955714Skris;; fstore 250109998Smarkm(define_insn_reservation "r24k_fstore" 2 25155714Skris (and (eq_attr "cpu" "24k") 25255714Skris (eq_attr "type" "fpstore")) 25355714Skris "r24k_fpu_iss") 25455714Skris 25555714Skris;; fmul, fmadd 25668651Skris(define_insn_reservation "r24k_fmul_sf" 8 25768651Skris (and (eq_attr "cpu" "24k") 25868651Skris (and (eq_attr "type" "fmul,fmadd") 25968651Skris (eq_attr "mode" "SF"))) 26068651Skris "r24k_fpu_iss") 26168651Skris 26268651Skris(define_insn_reservation "r24k_fmul_df" 10 26368651Skris (and (eq_attr "cpu" "24k") 26468651Skris (and (eq_attr "type" "fmul,fmadd") 26568651Skris (eq_attr "mode" "DF"))) 26668651Skris "r24k_fpu_iss,(r24k_fpu_arith*2)") 26755714Skris 26855714Skris 26955714Skris;; fdiv, fsqrt, frsqrt 27055714Skris(define_insn_reservation "r24k_fdiv_sf" 34 27155714Skris (and (eq_attr "cpu" "24k") 27255714Skris (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 27355714Skris (eq_attr "mode" "SF"))) 27455714Skris "r24k_fpu_iss,(r24k_fpu_arith*26)") 27559191Skris 27659191Skris(define_insn_reservation "r24k_fdiv_df" 64 27755714Skris (and (eq_attr "cpu" "24k") 27859191Skris (and (eq_attr "type" "fdiv,fsqrt") 27959191Skris (eq_attr "mode" "DF"))) 28059191Skris "r24k_fpu_iss,(r24k_fpu_arith*56)") 28159191Skris 28259191Skris;; frsqrt 28359191Skris(define_insn_reservation "r24k_frsqrt_df" 70 28459191Skris (and (eq_attr "cpu" "24k") 28559191Skris (and (eq_attr "type" "frsqrt") 28655714Skris (eq_attr "mode" "DF"))) 28755714Skris "r24k_fpu_iss,(r24k_fpu_arith*60)") 28855714Skris 289160814Ssimon;; fcmp 29055714Skris(define_insn_reservation "r24k_fcmp" 4 29155714Skris (and (eq_attr "cpu" "24k") 29255714Skris (eq_attr "type" "fcmp")) 293160814Ssimon "r24k_fpu_iss") 29455714Skris 29555714Skris;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) 29659191Skris(define_bypass 2 "r24k_fcmp" "r24k_fmove") 29759191Skris 29855714Skris;; fcvt (cvt.d.s, cvt.[sd].[wl]) 29955714Skris(define_insn_reservation "r24k_fcvt_i2f_s2d" 8 30055714Skris (and (eq_attr "cpu" "24k") 30159191Skris (and (eq_attr "type" "fcvt") 30259191Skris (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 30359191Skris "r24k_fpu_iss") 30459191Skris 30555714Skris;; fcvt (cvt.s.d) 30655714Skris(define_insn_reservation "r24k_fcvt_s2d" 12 30759191Skris (and (eq_attr "cpu" "24k") 30859191Skris (and (eq_attr "type" "fcvt") 30955714Skris (eq_attr "cnv_mode" "D2S"))) 31055714Skris "r24k_fpu_iss") 31155714Skris 31255714Skris;; fcvt (cvt.[wl].[sd], etc) 31355714Skris(define_insn_reservation "r24k_fcvt_f2i" 10 31455714Skris (and (eq_attr "cpu" "24k") 31555714Skris (and (eq_attr "type" "fcvt") 31655714Skris (eq_attr "cnv_mode" "S2I,D2I"))) 31755714Skris "r24k_fpu_iss") 31855714Skris 319109998Smarkm;; fxfer (mfc1, mfhc1, mtc1, mthc1) 320109998Smarkm(define_insn_reservation "r24k_fxfer" 4 321109998Smarkm (and (eq_attr "cpu" "24k") 322109998Smarkm (eq_attr "type" "xfer")) 323109998Smarkm "r24k_fpu_iss") 324109998Smarkm 325160814Ssimon;; -------------------------------------------------------------- 326160814Ssimon;; Bypass to Consumer 327160814Ssimon;; -------------------------------------------------------------- 328160814Ssimon;; r24k_fcvt_f2i->l/s base : 11 cycles 32955714Skris;; r24k_fcvt_f2i->prefetch : 11 cycles 330109998Smarkm(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_load") 331109998Smarkm(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p") 332109998Smarkm(define_bypass 11 "r24k_fcvt_f2i" "r24k_int_prefetch") 33359191Skris 334109998Smarkm;; r24k_fxfer->l/s base : 5 cycles 33559191Skris;; r24k_fxfer->prefetch : 5 cycles 33659191Skris(define_bypass 5 "r24k_fxfer" "r24k_int_load") 33759191Skris(define_bypass 5 "r24k_fxfer" "r24k_int_store" "!store_data_bypass_p") 33859191Skris(define_bypass 5 "r24k_fxfer" "r24k_int_prefetch") 33955714Skris 34059191Skris;; -------------------------------------------------------------- 34155714Skris;; The 24kx is a 24k configured with 1:1 cpu and fpu, so use 34259191Skris;; the unscaled timings 34355714Skris;; -------------------------------------------------------------- 34455714Skris 34555714Skris(define_reservation "r24kx_fpu_iss" "r24k_iss+r24k_fpu_arith") 34655714Skris 34755714Skris;; fadd, fabs, fneg 34859191Skris(define_insn_reservation "r24kx_fadd" 4 34959191Skris (and (eq_attr "cpu" "24kx") 350194206Ssimon (eq_attr "type" "fadd,fabs,fneg")) 35159191Skris "r24kx_fpu_iss") 35259191Skris 35359191Skris;; fmove, fcmove 35459191Skris(define_insn_reservation "r24kx_fmove" 4 35559191Skris (and (eq_attr "cpu" "24kx") 35655714Skris (eq_attr "type" "fmove,condmove")) 35755714Skris "r24kx_fpu_iss") 35859191Skris 35959191Skris;; fload 36055714Skris(define_insn_reservation "r24kx_fload" 3 36155714Skris (and (eq_attr "cpu" "24kx") 36259191Skris (eq_attr "type" "fpload,fpidxload")) 36359191Skris "r24kx_fpu_iss") 36468651Skris 365194206Ssimon;; fstore 36668651Skris(define_insn_reservation "r24kx_fstore" 1 36759191Skris (and (eq_attr "cpu" "24kx") 368109998Smarkm (eq_attr "type" "fpstore")) 369109998Smarkm "r24kx_fpu_iss") 37068651Skris 37159191Skris;; fmul, fmadd 37268651Skris(define_insn_reservation "r24kx_fmul_sf" 4 37368651Skris (and (eq_attr "cpu" "24kx") 37459191Skris (and (eq_attr "type" "fmul,fmadd") 37568651Skris (eq_attr "mode" "SF"))) 37668651Skris "r24kx_fpu_iss") 37768651Skris 37855714Skris(define_insn_reservation "r24kx_fmul_df" 5 37959191Skris (and (eq_attr "cpu" "24kx") 38055714Skris (and (eq_attr "type" "fmul,fmadd") 38155714Skris (eq_attr "mode" "DF"))) 38255714Skris "r24kx_fpu_iss,r24k_fpu_arith") 38376866Skris 38476866Skris 385109998Smarkm;; fdiv, fsqrt, frsqrt 386109998Smarkm(define_insn_reservation "r24kx_fdiv_sf" 17 387109998Smarkm (and (eq_attr "cpu" "24kx") 388109998Smarkm (and (eq_attr "type" "fdiv,fsqrt,frsqrt") 389109998Smarkm (eq_attr "mode" "SF"))) 390109998Smarkm "r24kx_fpu_iss,(r24k_fpu_arith*13)") 391109998Smarkm 392109998Smarkm(define_insn_reservation "r24kx_fdiv_df" 32 393109998Smarkm (and (eq_attr "cpu" "24kx") 394109998Smarkm (and (eq_attr "type" "fdiv,fsqrt") 395109998Smarkm (eq_attr "mode" "DF"))) 396109998Smarkm "r24kx_fpu_iss,(r24k_fpu_arith*28)") 397109998Smarkm 398109998Smarkm;; frsqrt 399109998Smarkm(define_insn_reservation "r24kx_frsqrt_df" 35 400109998Smarkm (and (eq_attr "cpu" "24kx") 401109998Smarkm (and (eq_attr "type" "frsqrt") 402109998Smarkm (eq_attr "mode" "DF"))) 403109998Smarkm "r24kx_fpu_iss,(r24k_fpu_arith*30)") 404109998Smarkm 40559191Skris;; fcmp 406109998Smarkm(define_insn_reservation "r24kx_fcmp" 2 407109998Smarkm (and (eq_attr "cpu" "24kx") 408109998Smarkm (eq_attr "type" "fcmp")) 409109998Smarkm "r24kx_fpu_iss") 41055714Skris 41155714Skris;; fcmp -> movf.fmt & movt.fmt bypass (dependency must be on the condition) 41255714Skris(define_bypass 1 "r24kx_fcmp" "r24kx_fmove") 41355714Skris 41455714Skris;; fcvt (cvt.d.s, cvt.[sd].[wl]) 41555714Skris(define_insn_reservation "r24kx_fcvt_i2f_s2d" 4 41655714Skris (and (eq_attr "cpu" "24kx") 41755714Skris (and (eq_attr "type" "fcvt") 41855714Skris (eq_attr "cnv_mode" "I2S,I2D,S2D"))) 41955714Skris "r24kx_fpu_iss") 42055714Skris 42155714Skris;; fcvt (cvt.s.d) 42255714Skris(define_insn_reservation "r24kx_fcvt_s2d" 6 42355714Skris (and (eq_attr "cpu" "24kx") 42455714Skris (and (eq_attr "type" "fcvt") 42555714Skris (eq_attr "cnv_mode" "D2S"))) 42655714Skris "r24kx_fpu_iss") 42755714Skris 42855714Skris;; fcvt (cvt.[wl].[sd], etc) 42955714Skris(define_insn_reservation "r24kx_fcvt_f2i" 5 430194206Ssimon (and (eq_attr "cpu" "24kx") 431194206Ssimon (and (eq_attr "type" "fcvt") 432194206Ssimon (eq_attr "cnv_mode" "S2I,D2I"))) 43368651Skris "r24kx_fpu_iss") 43468651Skris 43568651Skris;; fxfer (mfc1, mfhc1, mtc1, mthc1) 43668651Skris(define_insn_reservation "r24kx_fxfer" 2 43768651Skris (and (eq_attr "cpu" "24kx") 43868651Skris (eq_attr "type" "xfer")) 43968651Skris "r24kx_fpu_iss") 44068651Skris 44168651Skris;; -------------------------------------------------------------- 44268651Skris;; Bypass to Consumer 44359191Skris;; -------------------------------------------------------------- 44459191Skris;; r24kx_fcvt_f2i->l/s base : 6 cycles 44559191Skris;; r24kx_fcvt_f2i->prefetch : 6 cycles 44659191Skris(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_load") 447109998Smarkm(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_store" "!store_data_bypass_p") 448109998Smarkm(define_bypass 6 "r24kx_fcvt_f2i" "r24k_int_prefetch") 449109998Smarkm 450109998Smarkm;; r24kx_fxfer->l/s base : 3 cycles 451109998Smarkm;; r24kx_fxfer->prefetch : 3 cycles 45268651Skris(define_bypass 3 "r24kx_fxfer" "r24k_int_load") 45368651Skris(define_bypass 3 "r24kx_fxfer" "r24k_int_store" "!store_data_bypass_p") 45468651Skris(define_bypass 3 "r24kx_fxfer" "r24k_int_prefetch") 45568651Skris 45668651Skris