pentium.md revision 256281
1284345Ssjg;; Pentium Scheduling 2284345Ssjg;; Copyright (C) 2002 Free Software Foundation, Inc. 3284345Ssjg;; 4284345Ssjg;; This file is part of GCC. 5284345Ssjg;; 6284345Ssjg;; GCC is free software; you can redistribute it and/or modify 7284345Ssjg;; it under the terms of the GNU General Public License as published by 8284345Ssjg;; the Free Software Foundation; either version 2, or (at your option) 9284345Ssjg;; any later version. 10284345Ssjg;; 11284345Ssjg;; GCC is distributed in the hope that it will be useful, 12284345Ssjg;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13284345Ssjg;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14284345Ssjg;; GNU General Public License for more details. 15284345Ssjg;; 16284345Ssjg;; You should have received a copy of the GNU General Public License 17284345Ssjg;; along with GCC; see the file COPYING. If not, write to 18284345Ssjg;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 19284345Ssjg;; Boston, MA 02110-1301, USA. */ 20284345Ssjg;; 21284345Ssjg;; The Pentium is an in-order core with two integer pipelines. 22284345Ssjg 23284345Ssjg;; True for insns that behave like prefixed insns on the Pentium. 24284345Ssjg(define_attr "pent_prefix" "false,true" 25284345Ssjg (if_then_else (ior (eq_attr "prefix_0f" "1") 26284345Ssjg (ior (eq_attr "prefix_data16" "1") 27284345Ssjg (eq_attr "prefix_rep" "1"))) 28284345Ssjg (const_string "true") 29284345Ssjg (const_string "false"))) 30284345Ssjg 31284345Ssjg;; Categorize how an instruction slots. 32284345Ssjg 33284345Ssjg;; The non-MMX Pentium slots an instruction with prefixes on U pipe only, 34284345Ssjg;; while MMX Pentium can slot it on either U or V. Model non-MMX Pentium 35284345Ssjg;; rules, because it results in noticeably better code on non-MMX Pentium 36284345Ssjg;; and doesn't hurt much on MMX. (Prefixed instructions are not very 37284345Ssjg;; common, so the scheduler usually has a non-prefixed insn to pair). 38284345Ssjg 39284345Ssjg(define_attr "pent_pair" "uv,pu,pv,np" 40284345Ssjg (cond [(eq_attr "imm_disp" "true") 41284345Ssjg (const_string "np") 42284345Ssjg (ior (eq_attr "type" "alu1,alu,imov,icmp,test,lea,incdec") 43284345Ssjg (and (eq_attr "type" "pop,push") 44284345Ssjg (eq_attr "memory" "!both"))) 45284345Ssjg (if_then_else (eq_attr "pent_prefix" "true") 46284345Ssjg (const_string "pu") 47284345Ssjg (const_string "uv")) 48284345Ssjg (eq_attr "type" "ibr") 49284345Ssjg (const_string "pv") 50284345Ssjg (and (eq_attr "type" "ishift") 51284345Ssjg (match_operand 2 "const_int_operand" "")) 52284345Ssjg (const_string "pu") 53284345Ssjg (and (eq_attr "type" "rotate") 54284345Ssjg (match_operand 2 "const1_operand" "")) 55284345Ssjg (const_string "pu") 56284345Ssjg (and (eq_attr "type" "ishift1") 57284345Ssjg (match_operand 1 "const_int_operand" "")) 58284345Ssjg (const_string "pu") 59284345Ssjg (and (eq_attr "type" "rotate1") 60284345Ssjg (match_operand 1 "const1_operand" "")) 61284345Ssjg (const_string "pu") 62284345Ssjg (and (eq_attr "type" "call") 63284345Ssjg (match_operand 0 "constant_call_address_operand" "")) 64284345Ssjg (const_string "pv") 65284345Ssjg (and (eq_attr "type" "callv") 66284345Ssjg (match_operand 1 "constant_call_address_operand" "")) 67284345Ssjg (const_string "pv") 68284345Ssjg ] 69284345Ssjg (const_string "np"))) 70284345Ssjg 71284345Ssjg(define_automaton "pentium,pentium_fpu") 72284345Ssjg 73284345Ssjg;; Pentium do have U and V pipes. Instruction to both pipes 74284345Ssjg;; are always issued together, much like on VLIW. 75284345Ssjg;; 76284345Ssjg;; predecode 77284345Ssjg;; / \ 78284345Ssjg;; decodeu decodev 79284345Ssjg;; / | | 80284345Ssjg;; fpu executeu executev 81284345Ssjg;; | | | 82284345Ssjg;; fpu retire retire 83284345Ssjg;; | 84284345Ssjg;; fpu 85284345Ssjg;; We add dummy "port" pipes allocated only first cycle of 86284345Ssjg;; instruction to specify this behavior. 87284345Ssjg 88284345Ssjg(define_cpu_unit "pentium-portu,pentium-portv" "pentium") 89284345Ssjg(define_cpu_unit "pentium-u,pentium-v" "pentium") 90284345Ssjg(absence_set "pentium-portu" "pentium-u,pentium-v") 91284345Ssjg(presence_set "pentium-portv" "pentium-portu") 92284345Ssjg 93284345Ssjg;; Floating point instructions can overlap with new issue of integer 94284345Ssjg;; instructions. We model only first cycle of FP pipeline, as it is 95284345Ssjg;; fully pipelined. 96284345Ssjg(define_cpu_unit "pentium-fp" "pentium_fpu") 97284345Ssjg 98284345Ssjg;; There is non-pipelined multiplier unit used for complex operations. 99284345Ssjg(define_cpu_unit "pentium-fmul" "pentium_fpu") 100284345Ssjg 101284345Ssjg;; Pentium preserves memory ordering, so when load-execute-store 102284345Ssjg;; instruction is executed together with other instruction loading 103284345Ssjg;; data, the execution of the other instruction is delayed to very 104284345Ssjg;; last cycle of first instruction, when data are bypassed. 105284345Ssjg;; We model this by allocating "memory" unit when store is pending 106284345Ssjg;; and using conflicting load units together. 107284345Ssjg 108284345Ssjg(define_cpu_unit "pentium-memory" "pentium") 109284345Ssjg(define_cpu_unit "pentium-load0" "pentium") 110284345Ssjg(define_cpu_unit "pentium-load1" "pentium") 111284345Ssjg(absence_set "pentium-load0,pentium-load1" "pentium-memory") 112284345Ssjg 113284345Ssjg(define_reservation "pentium-load" "(pentium-load0 | pentium-load1)") 114284345Ssjg(define_reservation "pentium-np" "(pentium-u + pentium-v)") 115284345Ssjg(define_reservation "pentium-uv" "(pentium-u | pentium-v)") 116284345Ssjg(define_reservation "pentium-portuv" "(pentium-portu | pentium-portv)") 117284345Ssjg(define_reservation "pentium-firstu" "(pentium-u + pentium-portu)") 118284345Ssjg(define_reservation "pentium-firstv" "(pentium-v + pentium-portuv)") 119284345Ssjg(define_reservation "pentium-firstuv" "(pentium-uv + pentium-portuv)") 120284345Ssjg(define_reservation "pentium-firstuload" "(pentium-load + pentium-firstu)") 121284345Ssjg(define_reservation "pentium-firstvload" "(pentium-load + pentium-firstv)") 122284345Ssjg(define_reservation "pentium-firstuvload" "(pentium-load + pentium-firstuv) 123284345Ssjg | (pentium-firstv,pentium-v, 124284345Ssjg (pentium-load+pentium-firstv))") 125284345Ssjg(define_reservation "pentium-firstuboth" "(pentium-load + pentium-firstu 126284345Ssjg + pentium-memory)") 127284345Ssjg(define_reservation "pentium-firstvboth" "(pentium-load + pentium-firstv 128284345Ssjg + pentium-memory)") 129284345Ssjg(define_reservation "pentium-firstuvboth" "(pentium-load + pentium-firstuv 130284345Ssjg + pentium-memory) 131284345Ssjg | (pentium-firstv,pentium-v, 132284345Ssjg (pentium-load+pentium-firstv))") 133284345Ssjg 134284345Ssjg;; Few common long latency instructions 135284345Ssjg(define_insn_reservation "pent_mul" 11 136284345Ssjg (and (eq_attr "cpu" "pentium") 137284345Ssjg (eq_attr "type" "imul")) 138284345Ssjg "pentium-np*11") 139284345Ssjg 140284345Ssjg(define_insn_reservation "pent_str" 12 141284345Ssjg (and (eq_attr "cpu" "pentium") 142284345Ssjg (eq_attr "type" "str")) 143284345Ssjg "pentium-np*12") 144284345Ssjg 145284345Ssjg;; Integer division and some other long latency instruction block all 146284345Ssjg;; units, including the FP pipe. There is no value in modeling the 147284345Ssjg;; latency of these instructions and not modeling the latency 148284345Ssjg;; decreases the size of the DFA. 149284345Ssjg(define_insn_reservation "pent_block" 1 150284345Ssjg (and (eq_attr "cpu" "pentium") 151284345Ssjg (eq_attr "type" "idiv")) 152284345Ssjg "pentium-np+pentium-fp") 153284345Ssjg 154284345Ssjg(define_insn_reservation "pent_cld" 2 155284345Ssjg (and (eq_attr "cpu" "pentium") 156284345Ssjg (eq_attr "type" "cld")) 157284345Ssjg "pentium-np*2") 158284345Ssjg 159284345Ssjg;; Moves usually have one cycle penalty, but there are exceptions. 160284345Ssjg(define_insn_reservation "pent_fmov" 1 161284345Ssjg (and (eq_attr "cpu" "pentium") 162284345Ssjg (and (eq_attr "type" "fmov") 163284345Ssjg (eq_attr "memory" "none,load"))) 164284345Ssjg "(pentium-fp+pentium-np)") 165284345Ssjg 166284345Ssjg(define_insn_reservation "pent_fpmovxf" 3 167284345Ssjg (and (eq_attr "cpu" "pentium") 168284345Ssjg (and (eq_attr "type" "fmov") 169284345Ssjg (and (eq_attr "memory" "load,store") 170284345Ssjg (eq_attr "mode" "XF")))) 171284345Ssjg "(pentium-fp+pentium-np)*3") 172284345Ssjg 173284345Ssjg(define_insn_reservation "pent_fpstore" 2 174284345Ssjg (and (eq_attr "cpu" "pentium") 175284345Ssjg (and (eq_attr "type" "fmov") 176284345Ssjg (ior (match_operand 1 "immediate_operand" "") 177284345Ssjg (eq_attr "memory" "store")))) 178284345Ssjg "(pentium-fp+pentium-np)*2") 179284345Ssjg 180284345Ssjg(define_insn_reservation "pent_imov" 1 181284345Ssjg (and (eq_attr "cpu" "pentium") 182284345Ssjg (eq_attr "type" "imov")) 183284345Ssjg "pentium-firstuv") 184284345Ssjg 185284345Ssjg;; Push and pop instructions have 1 cycle latency and special 186284345Ssjg;; hardware bypass allows them to be paired with other push,pop 187284345Ssjg;; and call instructions. 188284345Ssjg(define_bypass 0 "pent_push,pent_pop" "pent_push,pent_pop,pent_call") 189284345Ssjg(define_insn_reservation "pent_push" 1 190284345Ssjg (and (eq_attr "cpu" "pentium") 191284345Ssjg (and (eq_attr "type" "push") 192284345Ssjg (eq_attr "memory" "store"))) 193284345Ssjg "pentium-firstuv") 194284345Ssjg 195284345Ssjg(define_insn_reservation "pent_pop" 1 196284345Ssjg (and (eq_attr "cpu" "pentium") 197284345Ssjg (eq_attr "type" "pop,leave")) 198284345Ssjg "pentium-firstuv") 199284345Ssjg 200284345Ssjg;; Call and branch instruction can execute in either pipe, but 201284345Ssjg;; they are only pairable when in the v pipe. 202284345Ssjg(define_insn_reservation "pent_call" 10 203284345Ssjg (and (eq_attr "cpu" "pentium") 204284345Ssjg (eq_attr "type" "call,callv")) 205284345Ssjg "pentium-firstv,pentium-v*9") 206284345Ssjg 207284345Ssjg(define_insn_reservation "pent_branch" 1 208284345Ssjg (and (eq_attr "cpu" "pentium") 209284345Ssjg (eq_attr "type" "ibr")) 210284345Ssjg "pentium-firstv") 211284345Ssjg 212284345Ssjg;; Floating point instruction dispatch in U pipe, but continue 213284345Ssjg;; in FP pipeline allowing other instructions to be executed. 214284345Ssjg(define_insn_reservation "pent_fp" 3 215284345Ssjg (and (eq_attr "cpu" "pentium") 216284345Ssjg (eq_attr "type" "fop,fistp")) 217284345Ssjg "(pentium-firstu+pentium-fp),nothing,nothing") 218284345Ssjg 219284345Ssjg;; First two cycles of fmul are not pipelined. 220284345Ssjg(define_insn_reservation "pent_fmul" 3 221284345Ssjg (and (eq_attr "cpu" "pentium") 222284345Ssjg (eq_attr "type" "fmul")) 223284345Ssjg "(pentium-firstuv+pentium-fp+pentium-fmul),pentium-fmul,nothing") 224284345Ssjg 225284345Ssjg;; Long latency FP instructions overlap with integer instructions, 226284345Ssjg;; but only last 2 cycles with FP ones. 227284345Ssjg(define_insn_reservation "pent_fdiv" 39 228284345Ssjg (and (eq_attr "cpu" "pentium") 229284345Ssjg (eq_attr "type" "fdiv")) 230284345Ssjg "(pentium-np+pentium-fp+pentium-fmul), 231284345Ssjg (pentium-fp+pentium-fmul)*36,pentium-fmul*2") 232284345Ssjg 233284345Ssjg(define_insn_reservation "pent_fpspc" 70 234284345Ssjg (and (eq_attr "cpu" "pentium") 235284345Ssjg (eq_attr "type" "fpspc")) 236284345Ssjg "(pentium-np+pentium-fp+pentium-fmul), 237284345Ssjg (pentium-fp+pentium-fmul)*67,pentium-fmul*2") 238284345Ssjg 239284345Ssjg;; Integer instructions. Load/execute/store takes 3 cycles, 240284345Ssjg;; load/execute 2 cycles and execute only one cycle. 241284345Ssjg(define_insn_reservation "pent_uv_both" 3 242284345Ssjg (and (eq_attr "cpu" "pentium") 243284345Ssjg (and (eq_attr "pent_pair" "uv") 244284345Ssjg (eq_attr "memory" "both"))) 245284345Ssjg "pentium-firstuvboth,pentium-uv+pentium-memory,pentium-uv") 246284345Ssjg 247284345Ssjg(define_insn_reservation "pent_u_both" 3 248284345Ssjg (and (eq_attr "cpu" "pentium") 249284345Ssjg (and (eq_attr "pent_pair" "pu") 250284345Ssjg (eq_attr "memory" "both"))) 251284345Ssjg "pentium-firstuboth,pentium-u+pentium-memory,pentium-u") 252284345Ssjg 253284345Ssjg(define_insn_reservation "pent_v_both" 3 254284345Ssjg (and (eq_attr "cpu" "pentium") 255284345Ssjg (and (eq_attr "pent_pair" "pv") 256284345Ssjg (eq_attr "memory" "both"))) 257284345Ssjg "pentium-firstvboth,pentium-v+pentium-memory,pentium-v") 258284345Ssjg 259284345Ssjg(define_insn_reservation "pent_np_both" 3 260284345Ssjg (and (eq_attr "cpu" "pentium") 261284345Ssjg (and (eq_attr "pent_pair" "np") 262284345Ssjg (eq_attr "memory" "both"))) 263284345Ssjg "pentium-np,pentium-np,pentium-np") 264284345Ssjg 265284345Ssjg(define_insn_reservation "pent_uv_load" 2 266284345Ssjg (and (eq_attr "cpu" "pentium") 267284345Ssjg (and (eq_attr "pent_pair" "uv") 268284345Ssjg (eq_attr "memory" "load"))) 269284345Ssjg "pentium-firstuvload,pentium-uv") 270284345Ssjg 271284345Ssjg(define_insn_reservation "pent_u_load" 2 272284345Ssjg (and (eq_attr "cpu" "pentium") 273284345Ssjg (and (eq_attr "pent_pair" "pu") 274284345Ssjg (eq_attr "memory" "load"))) 275284345Ssjg "pentium-firstuload,pentium-u") 276284345Ssjg 277284345Ssjg(define_insn_reservation "pent_v_load" 2 278284345Ssjg (and (eq_attr "cpu" "pentium") 279284345Ssjg (and (eq_attr "pent_pair" "pv") 280284345Ssjg (eq_attr "memory" "load"))) 281284345Ssjg "pentium-firstvload,pentium-v") 282284345Ssjg 283284345Ssjg(define_insn_reservation "pent_np_load" 2 284284345Ssjg (and (eq_attr "cpu" "pentium") 285284345Ssjg (and (eq_attr "pent_pair" "np") 286284345Ssjg (eq_attr "memory" "load"))) 287284345Ssjg "pentium-np,pentium-np") 288284345Ssjg 289284345Ssjg(define_insn_reservation "pent_uv" 1 290284345Ssjg (and (eq_attr "cpu" "pentium") 291284345Ssjg (and (eq_attr "pent_pair" "uv") 292284345Ssjg (eq_attr "memory" "none"))) 293284345Ssjg "pentium-firstuv") 294284345Ssjg 295284345Ssjg(define_insn_reservation "pent_u" 1 296284345Ssjg (and (eq_attr "cpu" "pentium") 297284345Ssjg (and (eq_attr "pent_pair" "pu") 298284345Ssjg (eq_attr "memory" "none"))) 299284345Ssjg "pentium-firstu") 300284345Ssjg 301284345Ssjg(define_insn_reservation "pent_v" 1 302284345Ssjg (and (eq_attr "cpu" "pentium") 303284345Ssjg (and (eq_attr "pent_pair" "pv") 304284345Ssjg (eq_attr "memory" "none"))) 305284345Ssjg "pentium-firstv") 306284345Ssjg 307284345Ssjg(define_insn_reservation "pent_np" 1 308284345Ssjg (and (eq_attr "cpu" "pentium") 309284345Ssjg (and (eq_attr "pent_pair" "np") 310284345Ssjg (eq_attr "memory" "none"))) 311284345Ssjg "pentium-np") 312284345Ssjg 313284345Ssjg