1169689Skan;; Constraint definitions for ARM and Thumb 2169689Skan;; Copyright (C) 2006 Free Software Foundation, Inc. 3169689Skan;; Contributed by ARM Ltd. 4169689Skan 5169689Skan;; This file is part of GCC. 6169689Skan 7169689Skan;; GCC is free software; you can redistribute it and/or modify it 8169689Skan;; under the terms of the GNU General Public License as published 9169689Skan;; by the Free Software Foundation; either version 2, or (at your 10169689Skan;; option) any later version. 11169689Skan 12169689Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 13169689Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14169689Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15169689Skan;; License for more details. 16169689Skan 17169689Skan;; You should have received a copy of the GNU General Public License 18169689Skan;; along with GCC; see the file COPYING. If not, write to 19169689Skan;; the Free Software Foundation, 51 Franklin Street, Fifth Floor, 20169689Skan;; Boston, MA 02110-1301, USA. 21169689Skan 22169689Skan;; The following register constraints have been used: 23169689Skan;; - in ARM state: f, v, w, y, z 24169689Skan;; - in Thumb state: h, k, b 25169689Skan;; - in both states: l, c 26169689Skan;; In ARM state, 'l' is an alias for 'r' 27169689Skan 28169689Skan;; The following normal constraints have been used: 29169689Skan;; in ARM state: G, H, I, J, K, L, M 30169689Skan;; in Thumb state: I, J, K, L, M, N, O 31169689Skan 32169689Skan;; The following multi-letter normal constraints have been used: 33169689Skan;; in ARM state: Da, Db, Dc 34169689Skan 35169689Skan;; The following memory constraints have been used: 36169689Skan;; in ARM state: Q, Uq, Uv, Uy 37169689Skan 38169689Skan 39169689Skan(define_register_constraint "f" "TARGET_ARM ? FPA_REGS : NO_REGS" 40169689Skan "Legacy FPA registers @code{f0}-@code{f7}.") 41169689Skan 42169689Skan(define_register_constraint "v" "TARGET_ARM ? CIRRUS_REGS : NO_REGS" 43169689Skan "The Cirrus Maverick co-processor registers.") 44169689Skan 45169689Skan(define_register_constraint "w" "TARGET_ARM ? VFP_REGS : NO_REGS" 46169689Skan "The VFP registers @code{s0}-@code{s31}.") 47169689Skan 48169689Skan(define_register_constraint "y" "TARGET_REALLY_IWMMXT ? IWMMXT_REGS : NO_REGS" 49169689Skan "The Intel iWMMX co-processor registers.") 50169689Skan 51169689Skan(define_register_constraint "z" 52169689Skan "TARGET_REALLY_IWMMXT ? IWMMXT_GR_REGS : NO_REGS" 53169689Skan "The Intel iWMMX GR registers.") 54169689Skan 55169689Skan(define_register_constraint "l" "TARGET_THUMB ? LO_REGS : GENERAL_REGS" 56169689Skan "In Thumb state the core registers @code{r0}-@code{r7}.") 57169689Skan 58169689Skan(define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS" 59169689Skan "In Thumb state the core registers @code{r8}-@code{r15}.") 60169689Skan 61169689Skan(define_register_constraint "k" "TARGET_THUMB ? STACK_REG : NO_REGS" 62169689Skan "@internal 63169689Skan Thumb only. The stack register.") 64169689Skan 65169689Skan(define_register_constraint "b" "TARGET_THUMB ? BASE_REGS : NO_REGS" 66169689Skan "@internal 67169689Skan Thumb only. The union of the low registers and the stack register.") 68169689Skan 69169689Skan(define_register_constraint "c" "CC_REG" 70169689Skan "@internal The condition code register.") 71169689Skan 72169689Skan(define_constraint "I" 73169689Skan "In ARM state a constant that can be used as an immediate value in a Data 74169689Skan Processing instruction. In Thumb state a constant in the range 0-255." 75169689Skan (and (match_code "const_int") 76169689Skan (match_test "TARGET_ARM ? const_ok_for_arm (ival) 77169689Skan : ival >= 0 && ival <= 255"))) 78169689Skan 79169689Skan(define_constraint "J" 80169689Skan "In ARM state a constant in the range @minus{}4095-4095. In Thumb state 81169689Skan a constant in the range @minus{}255-@minus{}1." 82169689Skan (and (match_code "const_int") 83169689Skan (match_test "TARGET_ARM ? (ival >= -4095 && ival <= 4095) 84169689Skan : (ival >= -255 && ival <= -1)"))) 85169689Skan 86169689Skan(define_constraint "K" 87169689Skan "In ARM state a constant that satisfies the @code{I} constraint if inverted. 88169689Skan In Thumb state a constant that satisfies the @code{I} constraint multiplied 89169689Skan by any power of 2." 90169689Skan (and (match_code "const_int") 91169689Skan (match_test "TARGET_ARM ? const_ok_for_arm (~ival) 92169689Skan : thumb_shiftable_const (ival)"))) 93169689Skan 94169689Skan(define_constraint "L" 95169689Skan "In ARM state a constant that satisfies the @code{I} constraint if negated. 96169689Skan In Thumb state a constant in the range @minus{}7-7." 97169689Skan (and (match_code "const_int") 98169689Skan (match_test "TARGET_ARM ? const_ok_for_arm (-ival) 99169689Skan : (ival >= -7 && ival <= 7)"))) 100169689Skan 101169689Skan;; The ARM state version is internal... 102169689Skan;; @internal In ARM state a constant in the range 0-32 or any power of 2. 103169689Skan(define_constraint "M" 104169689Skan "In Thumb state a constant that is a multiple of 4 in the range 0-1020." 105169689Skan (and (match_code "const_int") 106169689Skan (match_test "TARGET_ARM ? ((ival >= 0 && ival <= 32) 107169689Skan || ((ival & (ival - 1)) == 0)) 108169689Skan : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))"))) 109169689Skan 110169689Skan(define_constraint "N" 111169689Skan "In Thumb state a constant in the range 0-31." 112169689Skan (and (match_code "const_int") 113169689Skan (match_test "TARGET_THUMB && ival >= 0 && ival <= 31"))) 114169689Skan 115169689Skan(define_constraint "O" 116169689Skan "In Thumb state a constant that is a multiple of 4 in the range 117169689Skan @minus{}508-508." 118169689Skan (and (match_code "const_int") 119169689Skan (match_test "TARGET_THUMB && ival >= -508 && ival <= 508 120169689Skan && ((ival & 3) == 0)"))) 121169689Skan 122169689Skan(define_constraint "G" 123169689Skan "In ARM state a valid FPA immediate constant." 124169689Skan (and (match_code "const_double") 125169689Skan (match_test "TARGET_ARM && arm_const_double_rtx (op)"))) 126169689Skan 127169689Skan(define_constraint "H" 128169689Skan "In ARM state a valid FPA immediate constant when negated." 129169689Skan (and (match_code "const_double") 130169689Skan (match_test "TARGET_ARM && neg_const_double_rtx_ok_for_fpa (op)"))) 131169689Skan 132169689Skan(define_constraint "Da" 133169689Skan "@internal 134169689Skan In ARM state a const_int, const_double or const_vector that can 135169689Skan be generated with two Data Processing insns." 136169689Skan (and (match_code "const_double,const_int,const_vector") 137169689Skan (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 2"))) 138169689Skan 139169689Skan(define_constraint "Db" 140169689Skan "@internal 141169689Skan In ARM state a const_int, const_double or const_vector that can 142169689Skan be generated with three Data Processing insns." 143169689Skan (and (match_code "const_double,const_int,const_vector") 144169689Skan (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 3"))) 145169689Skan 146169689Skan(define_constraint "Dc" 147169689Skan "@internal 148169689Skan In ARM state a const_int, const_double or const_vector that can 149169689Skan be generated with four Data Processing insns. This pattern is disabled 150169689Skan if optimizing for space or when we have load-delay slots to fill." 151169689Skan (and (match_code "const_double,const_int,const_vector") 152169689Skan (match_test "TARGET_ARM && arm_const_double_inline_cost (op) == 4 153169689Skan && !(optimize_size || arm_ld_sched)"))) 154169689Skan 155169689Skan(define_memory_constraint "Uv" 156169689Skan "@internal 157169689Skan In ARM state a valid VFP load/store address." 158169689Skan (and (match_code "mem") 159169689Skan (match_test "TARGET_ARM && arm_coproc_mem_operand (op, FALSE)"))) 160169689Skan 161169689Skan(define_memory_constraint "Uy" 162169689Skan "@internal 163169689Skan In ARM state a valid iWMMX load/store address." 164169689Skan (and (match_code "mem") 165169689Skan (match_test "TARGET_ARM && arm_coproc_mem_operand (op, TRUE)"))) 166169689Skan 167169689Skan(define_memory_constraint "Uq" 168169689Skan "@internal 169169689Skan In ARM state an address valid in ldrsb instructions." 170169689Skan (and (match_code "mem") 171169689Skan (match_test "TARGET_ARM 172169689Skan && arm_legitimate_address_p (GET_MODE (op), XEXP (op, 0), 173169689Skan SIGN_EXTEND, 0)"))) 174169689Skan 175169689Skan(define_memory_constraint "Q" 176169689Skan "@internal 177169689Skan In ARM state an address that is a single base register." 178169689Skan (and (match_code "mem") 179169689Skan (match_test "REG_P (XEXP (op, 0))"))) 180169689Skan 181169689Skan;; We used to have constraint letters for S and R in ARM state, but 182169689Skan;; all uses of these now appear to have been removed. 183169689Skan 184169689Skan;; Additionally, we used to have a Q constraint in Thumb state, but 185169689Skan;; this wasn't really a valid memory constraint. Again, all uses of 186169689Skan;; this now seem to have been removed. 187