i386.h revision 61843
1/* opcode/i386.h -- Intel 80386 opcode table 2 Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 3 Free Software Foundation. 4 5This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. 6 7This program is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 2 of the License, or 10(at your option) any later version. 11 12This program is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this program; if not, write to the Free Software 19Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 20 21/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived 22 ix86 Unix assemblers, generate floating point instructions with 23 reversed source and destination registers in certain cases. 24 Unfortunately, gcc and possibly many other programs use this 25 reversed syntax, so we're stuck with it. 26 27 eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but 28 `fsub %st,%st(3)' results in st(3) = st - st(3), rather than 29 the expected st(3) = st(3) - st 30 31 This happens with all the non-commutative arithmetic floating point 32 operations with two register operands, where the source register is 33 %st, and destination register is %st(i). See FloatDR below. 34 35 The affected opcode map is dceX, dcfX, deeX, defX. */ 36 37#ifndef SYSV386_COMPAT 38/* Set non-zero for broken, compatible instructions. Set to zero for 39 non-broken opcodes at your peril. gcc generates SystemV/386 40 compatible instructions. */ 41#define SYSV386_COMPAT 1 42#endif 43#ifndef OLDGCC_COMPAT 44/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could 45 generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands 46 reversed. */ 47#define OLDGCC_COMPAT SYSV386_COMPAT 48#endif 49 50static const template i386_optab[] = { 51 52#define X None 53#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) 54#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) 55#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) 56#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf) 57#define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) 58#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf) 59#define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf) 60#define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf) 61#define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf) 62#define wld_Suf (No_bSuf|No_sSuf|No_xSuf) 63#define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf) 64#define sld_Suf (No_bSuf|No_wSuf|No_xSuf) 65#define sldx_Suf (No_bSuf|No_wSuf) 66#define bwl_Suf (No_sSuf|No_dSuf|No_xSuf) 67#define bwld_Suf (No_sSuf|No_xSuf) 68#define FP (NoSuf|IgnoreSize) 69#define l_FP (l_Suf|IgnoreSize) 70#define d_FP (d_Suf|IgnoreSize) 71#define x_FP (x_Suf|IgnoreSize) 72#define sl_FP (sl_Suf|IgnoreSize) 73#define sld_FP (sld_Suf|IgnoreSize) 74#define sldx_FP (sldx_Suf|IgnoreSize) 75#if SYSV386_COMPAT 76/* Someone forgot that the FloatR bit reverses the operation when not 77 equal to the FloatD bit. ie. Changing only FloatD results in the 78 destination being swapped *and* the direction being reversed. */ 79#define FloatDR FloatD 80#else 81#define FloatDR (FloatD|FloatR) 82#endif 83 84/* Move instructions. */ 85#define MOV_AX_DISP32 0xa0 86{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, 87{ "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 88{ "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } }, 89{ "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } }, 90/* The next two instructions accept WordReg so that a segment register 91 can be copied to a 32 bit register, and vice versa, without using a 92 size prefix. When moving to a 32 bit register, the upper 16 bits 93 are set to an implementation defined value (on the Pentium Pro, 94 the implementation defined value is zero). */ 95{ "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, 96{ "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, 97/* Move to/from control debug registers. */ 98{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, 99{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, 100{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, 101 102/* Move with sign extend. */ 103/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid 104 conflict with the "movs" string move instruction. */ 105{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, 106{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, 107{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 108/* Intel Syntax next 2 insns */ 109{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, 110{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 111 112/* Move with zero extend. */ 113{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 114{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, 115/* Intel Syntax next 2 insns */ 116{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, 117{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, 118 119/* Push instructions. */ 120{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 121{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 122{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, 123{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, 124{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 125{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 126{"pusha", 0, 0x60, X, wld_Suf|DefaultSize, { 0, 0, 0 } }, 127 128/* Pop instructions. */ 129{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, 130{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, 131#define POP_SEG_SHORT 0x07 132{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, 133{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, 134{"popa", 0, 0x61, X, wld_Suf|DefaultSize, { 0, 0, 0 } }, 135 136/* Exchange instructions. 137 xchg commutes: we allow both operand orders. */ 138{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, 139{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, 140{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 141{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, 142 143/* In/out from ports. */ 144{"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } }, 145{"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, 146{"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } }, 147{"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 148{"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } }, 149{"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, 150{"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } }, 151{"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, 152 153/* Load effective address. */ 154{"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, 155 156/* Load segment registers from memory. */ 157{"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 158{"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 159{"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 160{"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 161{"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, 162 163/* Flags register instructions. */ 164{"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} }, 165{"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} }, 166{"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} }, 167{"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} }, 168{"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} }, 169{"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} }, 170{"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} }, 171{"pushf", 0, 0x9c, X, wld_Suf|DefaultSize, { 0, 0, 0} }, 172{"popf", 0, 0x9d, X, wld_Suf|DefaultSize, { 0, 0, 0} }, 173{"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} }, 174{"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, 175{"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, 176 177/* Arithmetic. */ 178{"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 179{"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 180{"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} }, 181{"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 182 183{"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, 184{"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 185 186{"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 187{"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 188{"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} }, 189{"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 190 191{"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, 192{"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 193 194{"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 195{"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 196{"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} }, 197{"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 198 199{"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 200{"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 201{"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} }, 202{"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 203 204{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, 205{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, 206{"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} }, 207{"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 208 209{"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 210{"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 211{"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} }, 212{"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 213 214{"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 215{"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 216{"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} }, 217{"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 218 219{"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 220{"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 221{"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} }, 222{"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 223 224/* clr with 1 operand is really xor with 2 operands. */ 225{"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, 226 227{"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, 228{"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, 229{"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} }, 230{"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, 231 232{"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 233{"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 234 235{"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} }, 236{"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} }, 237{"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} }, 238{"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} }, 239{"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} }, 240{"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} }, 241{"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} }, 242{"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} }, 243 244/* Conversion insns. */ 245/* Intel naming */ 246{"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, 247{"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, 248{"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, 249{"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, 250/* AT&T naming */ 251{"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, 252{"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, 253{"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, 254{"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, 255 256/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are 257 expanding 64-bit multiplies, and *cannot* be selected to accomplish 258 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) 259 These multiplies can only be selected with single operand forms. */ 260{"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 261{"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 262{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 263{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, 264{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, 265/* imul with 2 operands mimics imul with 3 by putting the register in 266 both i.rm.reg & i.rm.regmem fields. regKludge enables this 267 transformation. */ 268{"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, 269{"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} }, 270 271{"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 272{"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 273{"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 274{"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, 275 276{"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 277{"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 278{"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 279{"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 280 281{"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 282{"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 283{"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 284{"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 285 286{"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 287{"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 288{"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 289{"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 290 291{"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 292{"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 293{"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 294{"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 295 296{"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 297{"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 298{"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 299{"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 300{"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 301{"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 302{"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 303{"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 304 305{"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 306{"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 307{"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 308{"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 309 310{"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, 311{"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, 312{"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, 313{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, 314 315{"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 316{"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 317{"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 318 319{"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, 320{"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, 321{"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 322 323/* Control transfer instructions. */ 324{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, 325{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 326/* Intel Syntax */ 327{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, 328/* Intel Syntax */ 329{"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, 330{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, 331{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, 332 333#define JUMP_PC_RELATIVE 0xeb 334{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, 335{"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, 336/* Intel Syntax */ 337{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 338/* Intel Syntax */ 339{"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} }, 340{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, 341{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, 342 343{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} }, 344{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, 345{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} }, 346{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, 347{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, 348{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, 349 350/* Conditional jumps. */ 351{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, 352{"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} }, 353{"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, 354{"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, 355{"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, 356{"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, 357{"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, 358{"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, 359{"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, 360{"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, 361{"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, 362{"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, 363{"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, 364{"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, 365{"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, 366{"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, 367{"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} }, 368{"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} }, 369{"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, 370{"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, 371{"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, 372{"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, 373{"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, 374{"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, 375{"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, 376{"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, 377{"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, 378{"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, 379{"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, 380{"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, 381 382/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ 383{"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, 384{"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, 385 386/* The loop instructions also use the address size prefix to select 387 %cx rather than %ecx for the loop count, so the `w' form of these 388 instructions emit an address size prefix rather than a data size 389 prefix. */ 390{"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} }, 391{"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, 392{"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, 393{"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, 394{"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, 395 396/* Set byte on flag instructions. */ 397{"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 398{"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 399{"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 400{"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 401{"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 402{"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 403{"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 404{"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 405{"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 406{"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 407{"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 408{"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 409{"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 410{"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 411{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 412{"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 413{"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 414{"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 415{"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 416{"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 417{"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 418{"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 419{"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 420{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 421{"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 422{"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 423{"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 424{"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 425{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 426{"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, 427 428/* String manipulation. */ 429{"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 430{"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 431{"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 432{"scmp", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, 433{"ins", 0, 0x6c, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 434{"ins", 2, 0x6c, X, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, 435{"outs", 0, 0x6e, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 436{"outs", 2, 0x6e, X, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, 437{"lods", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 438{"lods", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, 439{"lods", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, 440{"slod", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 441{"slod", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, 442{"slod", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, 443{"movs", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 444{"movs", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 445{"smov", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 446{"smov", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, 447{"scas", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 448{"scas", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 449{"scas", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 450{"ssca", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 451{"ssca", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 452{"ssca", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, 453{"stos", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 454{"stos", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 455{"stos", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 456{"ssto", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, 457{"ssto", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, 458{"ssto", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, 459{"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} }, 460{"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, 461 462/* Bit manipulation. */ 463{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 464{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 465{"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 466{"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 467{"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 468{"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 469{"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 470{"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 471{"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, 472{"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, 473 474/* Interrupts & op. sys insns. */ 475/* See gas/config/tc-i386.c for conversion of 'int $3' into the special 476 int 3 insn. */ 477#define INT_OPCODE 0xcd 478#define INT3_OPCODE 0xcc 479{"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} }, 480{"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} }, 481{"into", 0, 0xce, X, NoSuf, { 0, 0, 0} }, 482{"iret", 0, 0xcf, X, wld_Suf|DefaultSize, { 0, 0, 0} }, 483/* i386sl, i486sl, later 486, and Pentium. */ 484{"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} }, 485 486{"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} }, 487 488{"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} }, 489/* nop is actually 'xchgl %eax, %eax'. */ 490{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, 491 492/* Protection control. */ 493{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, 494{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 495{"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, 496{"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, 497{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 498{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 499{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 500{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 501 502{"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, 503{"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, 504{"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, 505{"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, 506{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 507 508{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 509{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, 510 511/* Floating point instructions. */ 512 513/* load */ 514{"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, 515{"fld", 1, 0xd9, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 516{"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 517/* Intel Syntax */ 518{"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, 519{"fild", 1, 0xdf, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 520/* Intel Syntax */ 521{"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, 522{"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, 523{"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, 524{"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, 525{"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, 526 527/* store (no pop) */ 528{"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, 529{"fst", 1, 0xd9, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 530{"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 531{"fist", 1, 0xdf, 2, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 532 533/* store (with pop) */ 534{"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, 535{"fstp", 1, 0xd9, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 536{"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 537/* Intel Syntax */ 538{"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, 539{"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 540/* Intel Syntax */ 541{"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, 542{"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, 543{"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, 544{"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, 545{"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, 546 547/* exchange %st<n> with %st0 */ 548{"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} }, 549/* alias for fxch %st(1) */ 550{"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, 551 552/* comparison (without pop) */ 553{"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} }, 554/* alias for fcom %st(1) */ 555{"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, 556{"fcom", 1, 0xd8, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 557{"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 558{"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 559 560/* comparison (with pop) */ 561{"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} }, 562/* alias for fcomp %st(1) */ 563{"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, 564{"fcomp", 1, 0xd8, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 565{"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, 566{"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 567{"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, 568 569/* unordered comparison (with pop) */ 570{"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} }, 571/* alias for fucom %st(1) */ 572{"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, 573{"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} }, 574/* alias for fucomp %st(1) */ 575{"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, 576{"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, 577 578{"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, 579{"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, 580 581/* load constants into %st0 */ 582{"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, 583{"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, 584{"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, 585{"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, 586{"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, 587{"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, 588{"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, 589 590/* arithmetic */ 591 592/* add */ 593{"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 594/* alias for fadd %st(i), %st */ 595{"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, 596#if SYSV386_COMPAT 597/* alias for faddp */ 598{"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, 599#endif 600{"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 601{"fiadd", 1, 0xde, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 602 603{"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 604{"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} }, 605/* alias for faddp %st, %st(1) */ 606{"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, 607{"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 608 609/* subtract */ 610{"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 611{"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} }, 612#if SYSV386_COMPAT 613/* alias for fsubp */ 614{"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, 615#endif 616{"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 617{"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 618 619#if SYSV386_COMPAT 620{"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 621{"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, 622{"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} }, 623#if OLDGCC_COMPAT 624{"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 625#endif 626#else 627{"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 628{"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, 629{"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} }, 630#endif 631 632/* subtract reverse */ 633{"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 634{"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} }, 635#if SYSV386_COMPAT 636/* alias for fsubrp */ 637{"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, 638#endif 639{"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 640{"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 641 642#if SYSV386_COMPAT 643{"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 644{"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, 645{"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} }, 646#if OLDGCC_COMPAT 647{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 648#endif 649#else 650{"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 651{"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, 652{"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} }, 653#endif 654 655/* multiply */ 656{"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, 657{"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} }, 658#if SYSV386_COMPAT 659/* alias for fmulp */ 660{"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, 661#endif 662{"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 663{"fimul", 1, 0xde, 1, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 664 665{"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 666{"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} }, 667{"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} }, 668{"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 669 670/* divide */ 671{"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 672{"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} }, 673#if SYSV386_COMPAT 674/* alias for fdivp */ 675{"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, 676#endif 677{"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 678{"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 679 680#if SYSV386_COMPAT 681{"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 682{"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, 683{"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} }, 684#if OLDGCC_COMPAT 685{"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 686#endif 687#else 688{"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 689{"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, 690{"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} }, 691#endif 692 693/* divide reverse */ 694{"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, 695{"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} }, 696#if SYSV386_COMPAT 697/* alias for fdivrp */ 698{"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, 699#endif 700{"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, 701{"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, 702 703#if SYSV386_COMPAT 704{"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 705{"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, 706{"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} }, 707#if OLDGCC_COMPAT 708{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, 709#endif 710#else 711{"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, 712{"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, 713{"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} }, 714#endif 715 716{"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} }, 717{"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} }, 718{"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} }, 719{"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} }, 720{"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} }, 721{"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} }, 722{"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} }, 723{"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} }, 724{"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} }, 725{"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} }, 726{"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} }, 727{"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} }, 728{"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} }, 729{"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} }, 730{"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} }, 731{"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} }, 732{"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} }, 733{"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} }, 734 735/* processor control */ 736{"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} }, 737{"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} }, 738{"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} }, 739{"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} }, 740{"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, 741{"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} }, 742{"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} }, 743{"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} }, 744{"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} }, 745{"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, 746{"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} }, 747{"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} }, 748{"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} }, 749/* Short forms of fldenv, fstenv use data size prefix. */ 750{"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, 751{"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, 752{"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, 753{"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, 754{"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, 755{"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, 756 757{"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} }, 758/* P6:free st(i), pop st */ 759{"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} }, 760{"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} }, 761#define FWAIT_OPCODE 0x9b 762{"fwait", 0, 0x9b, X, FP, { 0, 0, 0} }, 763 764/* Opcode prefixes; we allow them as separate insns too. */ 765 766#define ADDR_PREFIX_OPCODE 0x67 767{"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 768{"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 769{"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 770{"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 771#define DATA_PREFIX_OPCODE 0x66 772{"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 773{"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 774{"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, 775{"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, 776#define LOCK_PREFIX_OPCODE 0xf0 777{"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} }, 778{"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} }, 779#define CS_PREFIX_OPCODE 0x2e 780{"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} }, 781#define DS_PREFIX_OPCODE 0x3e 782{"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} }, 783#define ES_PREFIX_OPCODE 0x26 784{"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} }, 785#define FS_PREFIX_OPCODE 0x64 786{"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} }, 787#define GS_PREFIX_OPCODE 0x65 788{"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} }, 789#define SS_PREFIX_OPCODE 0x36 790{"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} }, 791#define REPNE_PREFIX_OPCODE 0xf2 792#define REPE_PREFIX_OPCODE 0xf3 793{"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, 794{"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, 795{"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, 796{"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, 797{"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, 798 799/* 486 extensions. */ 800 801{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, 802{"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 803{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, 804{"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, 805{"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} }, 806{"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} }, 807 808/* 586 and late 486 extensions. */ 809{"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} }, 810 811/* Pentium extensions. */ 812{"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} }, 813{"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, 814{"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, 815{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, 816 817/* Pentium II/Pentium Pro extensions. */ 818{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, 819{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, 820{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, 821{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, 822{"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, 823/* official undefined instr. */ 824{"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, 825/* alias for ud2 */ 826{"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, 827/* 2nd. official undefined instr. */ 828{"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, 829 830{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 831{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 832{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 833{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 834{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 835{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 836{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 837{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 838{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 839{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 840{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 841{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 842{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 843{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 844{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 845{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 846{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 847{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 848{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 849{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 850{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 851{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 852{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 853{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 854{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 855{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 856{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 857{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, 858 859{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 860{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 861{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 862{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 863{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 864{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 865{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 866{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 867{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 868{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 869{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 870{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 871 872{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 873{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, 874{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, 875{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 876{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, 877{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, 878{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 879{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 880{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, 881{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, 882{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 883{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, 884{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, 885{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, 886 887/* MMX instructions. */ 888 889{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, 890{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, 891{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, 892{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 893{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, 894{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 895{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 896{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 897{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 898{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 899{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 900{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 901{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 902{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 903{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 904{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 905{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 906{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 907{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 908{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 909{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 910{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 911{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 912{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 913{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 914{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 915{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 916{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 917{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, 918{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 919{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, 920{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 921{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, 922{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 923{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, 924{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 925{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, 926{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 927{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, 928{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 929{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, 930{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 931{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, 932{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 933{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 934{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 935{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 936{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 937{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 938{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 939{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 940{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 941{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 942{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 943{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 944{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 945{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, 946 947 948/* PIII Katmai New Instructions / SIMD instructions. */ 949 950{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 951{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 952{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 953{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 954{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 955{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 956{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 957{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 958{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 959{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 960{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 961{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 962{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 963{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 964{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 965{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 966{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 967{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 968{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, 969{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, 970{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 971{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, 972{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 973{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, 974{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 975{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, 976{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, 977{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, 978{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, 979{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 980{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 981{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, 982{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, 983{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 984{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 985{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 986{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 987{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 988{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 989{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 990{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, 991{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, 992{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, 993{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, 994{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, 995{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, 996{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, 997{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, 998{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 999{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, 1000{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1001{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, 1002{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1003{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1004{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1005{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1006{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1007{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, 1008{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, 1009{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1010{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1011{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1012{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1013{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, 1014{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1015{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, 1016{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, 1017{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, 1018{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, 1019{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, 1020{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, 1021{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1022{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1023{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1024{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1025{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, 1026{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, 1027{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1028{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1029{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, 1030{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1031{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1032{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, 1033{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1034{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1035{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, 1036 1037/* AMD 3DNow! instructions. */ 1038 1039{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, 1040{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, 1041{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, 1042{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1043{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1044{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ 1045{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1046{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1047{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1048{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1049{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1050{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1051{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1052{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1053{"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ 1054{"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ 1055{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1056{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1057{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1058{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1059{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1060{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1061{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1062{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1063{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ 1064{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, 1065{"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ 1066 1067/* sentinel */ 1068{NULL, 0, 0, 0, 0, { 0, 0, 0} } 1069}; 1070#undef X 1071#undef NoSuf 1072#undef b_Suf 1073#undef w_Suf 1074#undef l_Suf 1075#undef d_Suf 1076#undef x_Suf 1077#undef bw_Suf 1078#undef bl_Suf 1079#undef wl_Suf 1080#undef wld_Suf 1081#undef sl_Suf 1082#undef sld_Suf 1083#undef sldx_Suf 1084#undef bwl_Suf 1085#undef bwld_Suf 1086#undef FP 1087#undef l_FP 1088#undef d_FP 1089#undef x_FP 1090#undef sl_FP 1091#undef sld_FP 1092#undef sldx_FP 1093 1094#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ 1095 1096 1097/* 386 register table. */ 1098 1099static const reg_entry i386_regtab[] = { 1100 /* make %st first as we test for it */ 1101 {"st", FloatReg|FloatAcc, 0}, 1102 /* 8 bit regs */ 1103 {"al", Reg8|Acc, 0}, 1104 {"cl", Reg8|ShiftCount, 1}, 1105 {"dl", Reg8, 2}, 1106 {"bl", Reg8, 3}, 1107 {"ah", Reg8, 4}, 1108 {"ch", Reg8, 5}, 1109 {"dh", Reg8, 6}, 1110 {"bh", Reg8, 7}, 1111 /* 16 bit regs */ 1112 {"ax", Reg16|Acc, 0}, 1113 {"cx", Reg16, 1}, 1114 {"dx", Reg16|InOutPortReg, 2}, 1115 {"bx", Reg16|BaseIndex, 3}, 1116 {"sp", Reg16, 4}, 1117 {"bp", Reg16|BaseIndex, 5}, 1118 {"si", Reg16|BaseIndex, 6}, 1119 {"di", Reg16|BaseIndex, 7}, 1120 /* 32 bit regs */ 1121 {"eax", Reg32|BaseIndex|Acc, 0}, 1122 {"ecx", Reg32|BaseIndex, 1}, 1123 {"edx", Reg32|BaseIndex, 2}, 1124 {"ebx", Reg32|BaseIndex, 3}, 1125 {"esp", Reg32, 4}, 1126 {"ebp", Reg32|BaseIndex, 5}, 1127 {"esi", Reg32|BaseIndex, 6}, 1128 {"edi", Reg32|BaseIndex, 7}, 1129 /* segment registers */ 1130 {"es", SReg2, 0}, 1131 {"cs", SReg2, 1}, 1132 {"ss", SReg2, 2}, 1133 {"ds", SReg2, 3}, 1134 {"fs", SReg3, 4}, 1135 {"gs", SReg3, 5}, 1136 /* control registers */ 1137 {"cr0", Control, 0}, 1138 {"cr1", Control, 1}, 1139 {"cr2", Control, 2}, 1140 {"cr3", Control, 3}, 1141 {"cr4", Control, 4}, 1142 {"cr5", Control, 5}, 1143 {"cr6", Control, 6}, 1144 {"cr7", Control, 7}, 1145 /* debug registers */ 1146 {"db0", Debug, 0}, 1147 {"db1", Debug, 1}, 1148 {"db2", Debug, 2}, 1149 {"db3", Debug, 3}, 1150 {"db4", Debug, 4}, 1151 {"db5", Debug, 5}, 1152 {"db6", Debug, 6}, 1153 {"db7", Debug, 7}, 1154 {"dr0", Debug, 0}, 1155 {"dr1", Debug, 1}, 1156 {"dr2", Debug, 2}, 1157 {"dr3", Debug, 3}, 1158 {"dr4", Debug, 4}, 1159 {"dr5", Debug, 5}, 1160 {"dr6", Debug, 6}, 1161 {"dr7", Debug, 7}, 1162 /* test registers */ 1163 {"tr0", Test, 0}, 1164 {"tr1", Test, 1}, 1165 {"tr2", Test, 2}, 1166 {"tr3", Test, 3}, 1167 {"tr4", Test, 4}, 1168 {"tr5", Test, 5}, 1169 {"tr6", Test, 6}, 1170 {"tr7", Test, 7}, 1171 /* mmx and simd registers */ 1172 {"mm0", RegMMX, 0}, 1173 {"mm1", RegMMX, 1}, 1174 {"mm2", RegMMX, 2}, 1175 {"mm3", RegMMX, 3}, 1176 {"mm4", RegMMX, 4}, 1177 {"mm5", RegMMX, 5}, 1178 {"mm6", RegMMX, 6}, 1179 {"mm7", RegMMX, 7}, 1180 {"xmm0", RegXMM, 0}, 1181 {"xmm1", RegXMM, 1}, 1182 {"xmm2", RegXMM, 2}, 1183 {"xmm3", RegXMM, 3}, 1184 {"xmm4", RegXMM, 4}, 1185 {"xmm5", RegXMM, 5}, 1186 {"xmm6", RegXMM, 6}, 1187 {"xmm7", RegXMM, 7} 1188}; 1189 1190static const reg_entry i386_float_regtab[] = { 1191 {"st(0)", FloatReg|FloatAcc, 0}, 1192 {"st(1)", FloatReg, 1}, 1193 {"st(2)", FloatReg, 2}, 1194 {"st(3)", FloatReg, 3}, 1195 {"st(4)", FloatReg, 4}, 1196 {"st(5)", FloatReg, 5}, 1197 {"st(6)", FloatReg, 6}, 1198 {"st(7)", FloatReg, 7} 1199}; 1200 1201#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ 1202 1203/* segment stuff */ 1204static const seg_entry cs = { "cs", 0x2e }; 1205static const seg_entry ds = { "ds", 0x3e }; 1206static const seg_entry ss = { "ss", 0x36 }; 1207static const seg_entry es = { "es", 0x26 }; 1208static const seg_entry fs = { "fs", 0x64 }; 1209static const seg_entry gs = { "gs", 0x65 }; 1210 1211/* end of opcode/i386.h */ 1212