xmsr.c revision 276403
1228753Smm/*-
2228753Smm * Copyright (c) 2011 NetApp, Inc.
3228753Smm * All rights reserved.
4228753Smm *
5228753Smm * Redistribution and use in source and binary forms, with or without
6228753Smm * modification, are permitted provided that the following conditions
7228753Smm * are met:
8228753Smm * 1. Redistributions of source code must retain the above copyright
9228753Smm *    notice, this list of conditions and the following disclaimer.
10228753Smm * 2. Redistributions in binary form must reproduce the above copyright
11228753Smm *    notice, this list of conditions and the following disclaimer in the
12228753Smm *    documentation and/or other materials provided with the distribution.
13228753Smm *
14228753Smm * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15228753Smm * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16228753Smm * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17228753Smm * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18228753Smm * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19228753Smm * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20228753Smm * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21228753Smm * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22228753Smm * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23228753Smm * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24228753Smm * SUCH DAMAGE.
25228753Smm *
26228753Smm * $FreeBSD: stable/10/usr.sbin/bhyve/xmsr.c 276403 2014-12-30 08:24:14Z neel $
27231200Smm */
28228753Smm
29228753Smm#include <sys/cdefs.h>
30231200Smm__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/xmsr.c 276403 2014-12-30 08:24:14Z neel $");
31228753Smm
32231200Smm#include <sys/types.h>
33231200Smm
34231200Smm#include <machine/cpufunc.h>
35231200Smm#include <machine/vmm.h>
36231200Smm#include <machine/specialreg.h>
37231200Smm
38231200Smm#include <vmmapi.h>
39231200Smm
40231200Smm#include <stdio.h>
41228753Smm#include <stdlib.h>
42228753Smm#include <string.h>
43228753Smm
44228753Smm#include "xmsr.h"
45228753Smm
46231200Smmstatic int cpu_vendor_intel, cpu_vendor_amd;
47228753Smm
48231200Smmint
49231200Smmemulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t val)
50231200Smm{
51228753Smm
52228753Smm	if (cpu_vendor_intel) {
53		switch (num) {
54		case 0xd04:		/* Sandy Bridge uncore PMCs */
55		case 0xc24:
56			return (0);
57		case MSR_BIOS_UPDT_TRIG:
58			return (0);
59		case MSR_BIOS_SIGN:
60			return (0);
61		default:
62			break;
63		}
64	} else if (cpu_vendor_amd) {
65		switch (num) {
66		case MSR_HWCR:
67			/*
68			 * Ignore writes to hardware configuration MSR.
69			 */
70			return (0);
71
72		case MSR_NB_CFG1:
73		case MSR_IC_CFG:
74			return (0);	/* Ignore writes */
75
76		case MSR_PERFEVSEL0:
77		case MSR_PERFEVSEL1:
78		case MSR_PERFEVSEL2:
79		case MSR_PERFEVSEL3:
80			/* Ignore writes to the PerfEvtSel MSRs */
81			return (0);
82
83		case MSR_K7_PERFCTR0:
84		case MSR_K7_PERFCTR1:
85		case MSR_K7_PERFCTR2:
86		case MSR_K7_PERFCTR3:
87			/* Ignore writes to the PerfCtr MSRs */
88			return (0);
89
90		case MSR_P_STATE_CONTROL:
91			/* Ignore write to change the P-state */
92			return (0);
93
94		default:
95			break;
96		}
97	}
98	return (-1);
99}
100
101int
102emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val)
103{
104	int error = 0;
105
106	if (cpu_vendor_intel) {
107		switch (num) {
108		case MSR_BIOS_SIGN:
109		case MSR_IA32_PLATFORM_ID:
110		case MSR_PKG_ENERGY_STATUS:
111		case MSR_PP0_ENERGY_STATUS:
112		case MSR_PP1_ENERGY_STATUS:
113		case MSR_DRAM_ENERGY_STATUS:
114			*val = 0;
115			break;
116		case MSR_RAPL_POWER_UNIT:
117			/*
118			 * Use the default value documented in section
119			 * "RAPL Interfaces" in Intel SDM vol3.
120			 */
121			*val = 0x000a1003;
122			break;
123		default:
124			error = -1;
125			break;
126		}
127	} else if (cpu_vendor_amd) {
128		switch (num) {
129		case MSR_BIOS_SIGN:
130			*val = 0;
131			break;
132		case MSR_HWCR:
133			/*
134			 * Bios and Kernel Developer's Guides for AMD Families
135			 * 12H, 14H, 15H and 16H.
136			 */
137			*val = 0x01000010;	/* Reset value */
138			*val |= 1 << 9;		/* MONITOR/MWAIT disable */
139			break;
140
141		case MSR_NB_CFG1:
142		case MSR_IC_CFG:
143			/*
144			 * The reset value is processor family dependent so
145			 * just return 0.
146			 */
147			*val = 0;
148			break;
149
150		case MSR_PERFEVSEL0:
151		case MSR_PERFEVSEL1:
152		case MSR_PERFEVSEL2:
153		case MSR_PERFEVSEL3:
154			/*
155			 * PerfEvtSel MSRs are not properly virtualized so just
156			 * return zero.
157			 */
158			*val = 0;
159			break;
160
161		case MSR_K7_PERFCTR0:
162		case MSR_K7_PERFCTR1:
163		case MSR_K7_PERFCTR2:
164		case MSR_K7_PERFCTR3:
165			/*
166			 * PerfCtr MSRs are not properly virtualized so just
167			 * return zero.
168			 */
169			*val = 0;
170			break;
171
172		case MSR_SMM_ADDR:
173		case MSR_SMM_MASK:
174			/*
175			 * Return the reset value defined in the AMD Bios and
176			 * Kernel Developer's Guide.
177			 */
178			*val = 0;
179			break;
180
181		case MSR_P_STATE_LIMIT:
182		case MSR_P_STATE_CONTROL:
183		case MSR_P_STATE_STATUS:
184		case MSR_P_STATE_CONFIG(0):	/* P0 configuration */
185			*val = 0;
186			break;
187
188		default:
189			error = -1;
190			break;
191		}
192	} else {
193		error = -1;
194	}
195	return (error);
196}
197
198int
199init_msr(void)
200{
201	int error;
202	u_int regs[4];
203	char cpu_vendor[13];
204
205	do_cpuid(0, regs);
206	((u_int *)&cpu_vendor)[0] = regs[1];
207	((u_int *)&cpu_vendor)[1] = regs[3];
208	((u_int *)&cpu_vendor)[2] = regs[2];
209	cpu_vendor[12] = '\0';
210
211	error = 0;
212	if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
213		cpu_vendor_amd = 1;
214	} else if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
215		cpu_vendor_intel = 1;
216	} else {
217		fprintf(stderr, "Unknown cpu vendor \"%s\"\n", cpu_vendor);
218		error = -1;
219	}
220	return (error);
221}
222