pci_ahci.c revision 280732
1/*- 2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280732 2015-03-27 08:42:55Z mav $ 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/usr.sbin/bhyve/pci_ahci.c 280732 2015-03-27 08:42:55Z mav $"); 31 32#include <sys/param.h> 33#include <sys/linker_set.h> 34#include <sys/stat.h> 35#include <sys/uio.h> 36#include <sys/ioctl.h> 37#include <sys/disk.h> 38#include <sys/ata.h> 39#include <sys/endian.h> 40 41#include <errno.h> 42#include <fcntl.h> 43#include <stdio.h> 44#include <stdlib.h> 45#include <stdint.h> 46#include <string.h> 47#include <strings.h> 48#include <unistd.h> 49#include <assert.h> 50#include <pthread.h> 51#include <pthread_np.h> 52#include <inttypes.h> 53 54#include "bhyverun.h" 55#include "pci_emul.h" 56#include "ahci.h" 57#include "block_if.h" 58 59#define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 60 61#define PxSIG_ATA 0x00000101 /* ATA drive */ 62#define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 63 64enum sata_fis_type { 65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 73}; 74 75/* 76 * SCSI opcodes 77 */ 78#define TEST_UNIT_READY 0x00 79#define REQUEST_SENSE 0x03 80#define INQUIRY 0x12 81#define START_STOP_UNIT 0x1B 82#define PREVENT_ALLOW 0x1E 83#define READ_CAPACITY 0x25 84#define READ_10 0x28 85#define POSITION_TO_ELEMENT 0x2B 86#define READ_TOC 0x43 87#define GET_EVENT_STATUS_NOTIFICATION 0x4A 88#define MODE_SENSE_10 0x5A 89#define READ_12 0xA8 90#define READ_CD 0xBE 91 92/* 93 * SCSI mode page codes 94 */ 95#define MODEPAGE_RW_ERROR_RECOVERY 0x01 96#define MODEPAGE_CD_CAPABILITIES 0x2A 97 98/* 99 * ATA commands 100 */ 101#define ATA_SF_ENAB_SATA_SF 0x10 102#define ATA_SATA_SF_AN 0x05 103#define ATA_SF_DIS_SATA_SF 0x90 104 105/* 106 * Debug printf 107 */ 108#ifdef AHCI_DEBUG 109static FILE *dbg; 110#define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 111#else 112#define DPRINTF(format, arg...) 113#endif 114#define WPRINTF(format, arg...) printf(format, ##arg) 115 116struct ahci_ioreq { 117 struct blockif_req io_req; 118 struct ahci_port *io_pr; 119 STAILQ_ENTRY(ahci_ioreq) io_flist; 120 TAILQ_ENTRY(ahci_ioreq) io_blist; 121 uint8_t *cfis; 122 uint32_t len; 123 uint32_t done; 124 int slot; 125 int prdtl; 126}; 127 128struct ahci_port { 129 struct blockif_ctxt *bctx; 130 struct pci_ahci_softc *pr_sc; 131 uint8_t *cmd_lst; 132 uint8_t *rfis; 133 int atapi; 134 int reset; 135 int mult_sectors; 136 uint8_t xfermode; 137 uint8_t sense_key; 138 uint8_t asc; 139 uint32_t pending; 140 141 uint32_t clb; 142 uint32_t clbu; 143 uint32_t fb; 144 uint32_t fbu; 145 uint32_t is; 146 uint32_t ie; 147 uint32_t cmd; 148 uint32_t unused0; 149 uint32_t tfd; 150 uint32_t sig; 151 uint32_t ssts; 152 uint32_t sctl; 153 uint32_t serr; 154 uint32_t sact; 155 uint32_t ci; 156 uint32_t sntf; 157 uint32_t fbs; 158 159 /* 160 * i/o request info 161 */ 162 struct ahci_ioreq *ioreq; 163 int ioqsz; 164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 166}; 167 168struct ahci_cmd_hdr { 169 uint16_t flags; 170 uint16_t prdtl; 171 uint32_t prdbc; 172 uint64_t ctba; 173 uint32_t reserved[4]; 174}; 175 176struct ahci_prdt_entry { 177 uint64_t dba; 178 uint32_t reserved; 179#define DBCMASK 0x3fffff 180 uint32_t dbc; 181}; 182 183struct pci_ahci_softc { 184 struct pci_devinst *asc_pi; 185 pthread_mutex_t mtx; 186 int ports; 187 uint32_t cap; 188 uint32_t ghc; 189 uint32_t is; 190 uint32_t pi; 191 uint32_t vs; 192 uint32_t ccc_ctl; 193 uint32_t ccc_pts; 194 uint32_t em_loc; 195 uint32_t em_ctl; 196 uint32_t cap2; 197 uint32_t bohc; 198 uint32_t lintr; 199 struct ahci_port port[MAX_PORTS]; 200}; 201#define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 202 203static inline void lba_to_msf(uint8_t *buf, int lba) 204{ 205 lba += 150; 206 buf[0] = (lba / 75) / 60; 207 buf[1] = (lba / 75) % 60; 208 buf[2] = lba % 75; 209} 210 211/* 212 * generate HBA intr depending on whether or not ports within 213 * the controller have an interrupt pending. 214 */ 215static void 216ahci_generate_intr(struct pci_ahci_softc *sc) 217{ 218 struct pci_devinst *pi; 219 int i; 220 221 pi = sc->asc_pi; 222 223 for (i = 0; i < sc->ports; i++) { 224 struct ahci_port *pr; 225 pr = &sc->port[i]; 226 if (pr->is & pr->ie) 227 sc->is |= (1 << i); 228 } 229 230 DPRINTF("%s %x\n", __func__, sc->is); 231 232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) { 233 if (pci_msi_enabled(pi)) { 234 /* 235 * Generate an MSI interrupt on every edge 236 */ 237 pci_generate_msi(pi, 0); 238 } else if (!sc->lintr) { 239 /* 240 * Only generate a pin-based interrupt if one wasn't 241 * in progress 242 */ 243 sc->lintr = 1; 244 pci_lintr_assert(pi); 245 } 246 } else if (sc->lintr) { 247 /* 248 * No interrupts: deassert pin-based signal if it had 249 * been asserted 250 */ 251 pci_lintr_deassert(pi); 252 sc->lintr = 0; 253 } 254} 255 256static void 257ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 258{ 259 int offset, len, irq; 260 261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 262 return; 263 264 switch (ft) { 265 case FIS_TYPE_REGD2H: 266 offset = 0x40; 267 len = 20; 268 irq = AHCI_P_IX_DHR; 269 break; 270 case FIS_TYPE_SETDEVBITS: 271 offset = 0x58; 272 len = 8; 273 irq = AHCI_P_IX_SDB; 274 break; 275 case FIS_TYPE_PIOSETUP: 276 offset = 0x20; 277 len = 20; 278 irq = 0; 279 break; 280 default: 281 WPRINTF("unsupported fis type %d\n", ft); 282 return; 283 } 284 memcpy(p->rfis + offset, fis, len); 285 if (irq) { 286 p->is |= irq; 287 ahci_generate_intr(p->pr_sc); 288 } 289} 290 291static void 292ahci_write_fis_piosetup(struct ahci_port *p) 293{ 294 uint8_t fis[20]; 295 296 memset(fis, 0, sizeof(fis)); 297 fis[0] = FIS_TYPE_PIOSETUP; 298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 299} 300 301static void 302ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd) 303{ 304 uint8_t fis[8]; 305 uint8_t error; 306 307 error = (tfd >> 8) & 0xff; 308 memset(fis, 0, sizeof(fis)); 309 fis[0] = error; 310 fis[2] = tfd & 0x77; 311 *(uint32_t *)(fis + 4) = (1 << slot); 312 if (fis[2] & ATA_S_ERROR) 313 p->is |= AHCI_P_IX_TFE; 314 p->tfd = tfd; 315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 316} 317 318static void 319ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 320{ 321 uint8_t fis[20]; 322 uint8_t error; 323 324 error = (tfd >> 8) & 0xff; 325 memset(fis, 0, sizeof(fis)); 326 fis[0] = FIS_TYPE_REGD2H; 327 fis[1] = (1 << 6); 328 fis[2] = tfd & 0xff; 329 fis[3] = error; 330 fis[4] = cfis[4]; 331 fis[5] = cfis[5]; 332 fis[6] = cfis[6]; 333 fis[7] = cfis[7]; 334 fis[8] = cfis[8]; 335 fis[9] = cfis[9]; 336 fis[10] = cfis[10]; 337 fis[11] = cfis[11]; 338 fis[12] = cfis[12]; 339 fis[13] = cfis[13]; 340 if (fis[2] & ATA_S_ERROR) 341 p->is |= AHCI_P_IX_TFE; 342 else 343 p->ci &= ~(1 << slot); 344 p->tfd = tfd; 345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 346} 347 348static void 349ahci_write_reset_fis_d2h(struct ahci_port *p) 350{ 351 uint8_t fis[20]; 352 353 memset(fis, 0, sizeof(fis)); 354 fis[0] = FIS_TYPE_REGD2H; 355 fis[3] = 1; 356 fis[4] = 1; 357 if (p->atapi) { 358 fis[5] = 0x14; 359 fis[6] = 0xeb; 360 } 361 fis[12] = 1; 362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 363} 364 365static void 366ahci_check_stopped(struct ahci_port *p) 367{ 368 /* 369 * If we are no longer processing the command list and nothing 370 * is in-flight, clear the running bit, the current command 371 * slot, the command issue and active bits. 372 */ 373 if (!(p->cmd & AHCI_P_CMD_ST)) { 374 if (p->pending == 0) { 375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 376 p->ci = 0; 377 p->sact = 0; 378 } 379 } 380} 381 382static void 383ahci_port_stop(struct ahci_port *p) 384{ 385 struct ahci_ioreq *aior; 386 uint8_t *cfis; 387 int slot; 388 int ncq; 389 int error; 390 391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 392 393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 394 /* 395 * Try to cancel the outstanding blockif request. 396 */ 397 error = blockif_cancel(p->bctx, &aior->io_req); 398 if (error != 0) 399 continue; 400 401 slot = aior->slot; 402 cfis = aior->cfis; 403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 404 cfis[2] == ATA_READ_FPDMA_QUEUED) 405 ncq = 1; 406 407 if (ncq) 408 p->sact &= ~(1 << slot); 409 else 410 p->ci &= ~(1 << slot); 411 412 /* 413 * This command is now done. 414 */ 415 p->pending &= ~(1 << slot); 416 417 /* 418 * Delete the blockif request from the busy list 419 */ 420 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 421 422 /* 423 * Move the blockif request back to the free list 424 */ 425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 426 } 427 428 ahci_check_stopped(p); 429} 430 431static void 432ahci_port_reset(struct ahci_port *pr) 433{ 434 pr->sctl = 0; 435 pr->serr = 0; 436 pr->sact = 0; 437 pr->xfermode = ATA_UDMA6; 438 pr->mult_sectors = 128; 439 440 if (!pr->bctx) { 441 pr->ssts = ATA_SS_DET_NO_DEVICE; 442 pr->sig = 0xFFFFFFFF; 443 pr->tfd = 0x7F; 444 return; 445 } 446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 | 447 ATA_SS_IPM_ACTIVE; 448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 449 if (!pr->atapi) { 450 pr->sig = PxSIG_ATA; 451 pr->tfd |= ATA_S_READY; 452 } else 453 pr->sig = PxSIG_ATAPI; 454 ahci_write_reset_fis_d2h(pr); 455} 456 457static void 458ahci_reset(struct pci_ahci_softc *sc) 459{ 460 int i; 461 462 sc->ghc = AHCI_GHC_AE; 463 sc->is = 0; 464 465 if (sc->lintr) { 466 pci_lintr_deassert(sc->asc_pi); 467 sc->lintr = 0; 468 } 469 470 for (i = 0; i < sc->ports; i++) { 471 sc->port[i].ie = 0; 472 sc->port[i].is = 0; 473 ahci_port_reset(&sc->port[i]); 474 } 475} 476 477static void 478ata_string(uint8_t *dest, const char *src, int len) 479{ 480 int i; 481 482 for (i = 0; i < len; i++) { 483 if (*src) 484 dest[i ^ 1] = *src++; 485 else 486 dest[i ^ 1] = ' '; 487 } 488} 489 490static void 491atapi_string(uint8_t *dest, const char *src, int len) 492{ 493 int i; 494 495 for (i = 0; i < len; i++) { 496 if (*src) 497 dest[i] = *src++; 498 else 499 dest[i] = ' '; 500 } 501} 502 503static void 504ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done, 505 int seek) 506{ 507 struct ahci_ioreq *aior; 508 struct blockif_req *breq; 509 struct pci_ahci_softc *sc; 510 struct ahci_prdt_entry *prdt; 511 struct ahci_cmd_hdr *hdr; 512 uint64_t lba; 513 uint32_t len; 514 int i, err, iovcnt, ncq, readop; 515 516 sc = p->pr_sc; 517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 519 ncq = 0; 520 readop = 1; 521 522 prdt += seek; 523 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 524 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 525 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 526 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 527 readop = 0; 528 529 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 530 cfis[2] == ATA_READ_FPDMA_QUEUED) { 531 lba = ((uint64_t)cfis[10] << 40) | 532 ((uint64_t)cfis[9] << 32) | 533 ((uint64_t)cfis[8] << 24) | 534 ((uint64_t)cfis[6] << 16) | 535 ((uint64_t)cfis[5] << 8) | 536 cfis[4]; 537 len = cfis[11] << 8 | cfis[3]; 538 if (!len) 539 len = 65536; 540 ncq = 1; 541 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 542 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 543 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 544 lba = ((uint64_t)cfis[10] << 40) | 545 ((uint64_t)cfis[9] << 32) | 546 ((uint64_t)cfis[8] << 24) | 547 ((uint64_t)cfis[6] << 16) | 548 ((uint64_t)cfis[5] << 8) | 549 cfis[4]; 550 len = cfis[13] << 8 | cfis[12]; 551 if (!len) 552 len = 65536; 553 } else { 554 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 555 (cfis[5] << 8) | cfis[4]; 556 len = cfis[12]; 557 if (!len) 558 len = 256; 559 } 560 lba *= blockif_sectsz(p->bctx); 561 len *= blockif_sectsz(p->bctx); 562 563 /* 564 * Pull request off free list 565 */ 566 aior = STAILQ_FIRST(&p->iofhd); 567 assert(aior != NULL); 568 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 569 aior->cfis = cfis; 570 aior->slot = slot; 571 aior->len = len; 572 aior->done = done; 573 breq = &aior->io_req; 574 breq->br_offset = lba + done; 575 iovcnt = hdr->prdtl - seek; 576 if (iovcnt > BLOCKIF_IOV_MAX) { 577 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 578 iovcnt = BLOCKIF_IOV_MAX; 579 } else 580 aior->prdtl = 0; 581 breq->br_iovcnt = iovcnt; 582 583 /* 584 * Mark this command in-flight. 585 */ 586 p->pending |= 1 << slot; 587 588 /* 589 * Stuff request onto busy list 590 */ 591 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 592 593 /* 594 * Build up the iovec based on the prdt 595 */ 596 for (i = 0; i < iovcnt; i++) { 597 uint32_t dbcsz; 598 599 dbcsz = (prdt->dbc & DBCMASK) + 1; 600 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 601 prdt->dba, dbcsz); 602 breq->br_iov[i].iov_len = dbcsz; 603 aior->done += dbcsz; 604 prdt++; 605 } 606 if (readop) 607 err = blockif_read(p->bctx, breq); 608 else 609 err = blockif_write(p->bctx, breq); 610 assert(err == 0); 611 612 if (ncq) 613 p->ci &= ~(1 << slot); 614} 615 616static void 617ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 618{ 619 struct ahci_ioreq *aior; 620 struct blockif_req *breq; 621 int err; 622 623 /* 624 * Pull request off free list 625 */ 626 aior = STAILQ_FIRST(&p->iofhd); 627 assert(aior != NULL); 628 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 629 aior->cfis = cfis; 630 aior->slot = slot; 631 aior->len = 0; 632 aior->done = 0; 633 aior->prdtl = 0; 634 breq = &aior->io_req; 635 636 /* 637 * Mark this command in-flight. 638 */ 639 p->pending |= 1 << slot; 640 641 /* 642 * Stuff request onto busy list 643 */ 644 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 645 646 err = blockif_flush(p->bctx, breq); 647 assert(err == 0); 648} 649 650static inline void 651read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 652 void *buf, int size) 653{ 654 struct ahci_cmd_hdr *hdr; 655 struct ahci_prdt_entry *prdt; 656 void *to; 657 int i, len; 658 659 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 660 len = size; 661 to = buf; 662 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 663 for (i = 0; i < hdr->prdtl && len; i++) { 664 uint8_t *ptr; 665 uint32_t dbcsz; 666 int sublen; 667 668 dbcsz = (prdt->dbc & DBCMASK) + 1; 669 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 670 sublen = len < dbcsz ? len : dbcsz; 671 memcpy(to, ptr, sublen); 672 len -= sublen; 673 to += sublen; 674 prdt++; 675 } 676} 677 678static void 679ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 680{ 681 struct ahci_ioreq *aior; 682 struct blockif_req *breq; 683 uint8_t *entry; 684 uint64_t elba; 685 uint32_t len, elen; 686 int err; 687 uint8_t buf[512]; 688 689 len = (uint16_t)cfis[13] << 8 | cfis[12]; 690 len *= 512; 691 read_prdt(p, slot, cfis, buf, sizeof(buf)); 692 693next: 694 entry = &buf[done]; 695 elba = ((uint64_t)entry[5] << 40) | 696 ((uint64_t)entry[4] << 32) | 697 ((uint64_t)entry[3] << 24) | 698 ((uint64_t)entry[2] << 16) | 699 ((uint64_t)entry[1] << 8) | 700 entry[0]; 701 elen = (uint16_t)entry[7] << 8 | entry[6]; 702 done += 8; 703 if (elen == 0) { 704 if (done >= len) { 705 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 706 p->pending &= ~(1 << slot); 707 ahci_check_stopped(p); 708 return; 709 } 710 goto next; 711 } 712 713 /* 714 * Pull request off free list 715 */ 716 aior = STAILQ_FIRST(&p->iofhd); 717 assert(aior != NULL); 718 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 719 aior->cfis = cfis; 720 aior->slot = slot; 721 aior->len = len; 722 aior->done = done; 723 aior->prdtl = 0; 724 725 breq = &aior->io_req; 726 breq->br_offset = elba * blockif_sectsz(p->bctx); 727 breq->br_iovcnt = 1; 728 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx); 729 730 /* 731 * Mark this command in-flight. 732 */ 733 p->pending |= 1 << slot; 734 735 /* 736 * Stuff request onto busy list 737 */ 738 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 739 740 err = blockif_delete(p->bctx, breq); 741 assert(err == 0); 742} 743 744static inline void 745write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, 746 void *buf, int size) 747{ 748 struct ahci_cmd_hdr *hdr; 749 struct ahci_prdt_entry *prdt; 750 void *from; 751 int i, len; 752 753 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 754 len = size; 755 from = buf; 756 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 757 for (i = 0; i < hdr->prdtl && len; i++) { 758 uint8_t *ptr; 759 uint32_t dbcsz; 760 int sublen; 761 762 dbcsz = (prdt->dbc & DBCMASK) + 1; 763 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 764 sublen = len < dbcsz ? len : dbcsz; 765 memcpy(ptr, from, sublen); 766 len -= sublen; 767 from += sublen; 768 prdt++; 769 } 770 hdr->prdbc = size - len; 771} 772 773static void 774handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 775{ 776 struct ahci_cmd_hdr *hdr; 777 778 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 779 if (p->atapi || hdr->prdtl == 0) { 780 ahci_write_fis_d2h(p, slot, cfis, 781 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 782 } else { 783 uint16_t buf[256]; 784 uint64_t sectors; 785 int sectsz, psectsz, psectoff, candelete, ro; 786 uint16_t cyl; 787 uint8_t sech, heads; 788 789 ro = blockif_is_ro(p->bctx); 790 candelete = blockif_candelete(p->bctx); 791 sectsz = blockif_sectsz(p->bctx); 792 sectors = blockif_size(p->bctx) / sectsz; 793 blockif_chs(p->bctx, &cyl, &heads, &sech); 794 blockif_psectsz(p->bctx, &psectsz, &psectoff); 795 memset(buf, 0, sizeof(buf)); 796 buf[0] = 0x0040; 797 buf[1] = cyl; 798 buf[3] = heads; 799 buf[6] = sech; 800 /* TODO emulate different serial? */ 801 ata_string((uint8_t *)(buf+10), "123456", 20); 802 ata_string((uint8_t *)(buf+23), "001", 8); 803 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40); 804 buf[47] = (0x8000 | 128); 805 buf[48] = 0x1; 806 buf[49] = (1 << 8 | 1 << 9 | 1 << 11); 807 buf[50] = (1 << 14); 808 buf[53] = (1 << 1 | 1 << 2); 809 if (p->mult_sectors) 810 buf[59] = (0x100 | p->mult_sectors); 811 buf[60] = sectors; 812 buf[61] = (sectors >> 16); 813 buf[63] = 0x7; 814 if (p->xfermode & ATA_WDMA0) 815 buf[63] |= (1 << ((p->xfermode & 7) + 8)); 816 buf[64] = 0x3; 817 buf[65] = 100; 818 buf[66] = 100; 819 buf[67] = 100; 820 buf[68] = 100; 821 buf[69] = 0; 822 buf[75] = 31; 823 buf[76] = (1 << 8 | 1 << 2); 824 buf[80] = 0x1f0; 825 buf[81] = 0x28; 826 buf[82] = (1 << 5 | 1 << 14); 827 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14); 828 buf[84] = (1 << 14); 829 buf[85] = (1 << 5 | 1 << 14); 830 buf[86] = (1 << 10 | 1 << 12 | 1 << 13); 831 buf[87] = (1 << 14); 832 buf[88] = 0x7f; 833 if (p->xfermode & ATA_UDMA0) 834 buf[88] |= (1 << ((p->xfermode & 7) + 8)); 835 buf[93] = (1 | 1 <<14); 836 buf[100] = sectors; 837 buf[101] = (sectors >> 16); 838 buf[102] = (sectors >> 32); 839 buf[103] = (sectors >> 48); 840 if (candelete && !ro) { 841 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 842 buf[105] = 1; 843 buf[169] = ATA_SUPPORT_DSM_TRIM; 844 } 845 buf[106] = 0x4000; 846 buf[209] = 0x4000; 847 if (psectsz > sectsz) { 848 buf[106] |= 0x2000; 849 buf[106] |= ffsl(psectsz / sectsz) - 1; 850 buf[209] |= (psectoff / sectsz); 851 } 852 if (sectsz > 512) { 853 buf[106] |= 0x1000; 854 buf[117] = sectsz / 2; 855 buf[118] = ((sectsz / 2) >> 16); 856 } 857 ahci_write_fis_piosetup(p); 858 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 859 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 860 } 861} 862 863static void 864handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 865{ 866 if (!p->atapi) { 867 ahci_write_fis_d2h(p, slot, cfis, 868 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 869 } else { 870 uint16_t buf[256]; 871 872 memset(buf, 0, sizeof(buf)); 873 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5); 874 /* TODO emulate different serial? */ 875 ata_string((uint8_t *)(buf+10), "123456", 20); 876 ata_string((uint8_t *)(buf+23), "001", 8); 877 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40); 878 buf[49] = (1 << 9 | 1 << 8); 879 buf[50] = (1 << 14 | 1); 880 buf[53] = (1 << 2 | 1 << 1); 881 buf[62] = 0x3f; 882 buf[63] = 7; 883 buf[64] = 3; 884 buf[65] = 100; 885 buf[66] = 100; 886 buf[67] = 100; 887 buf[68] = 100; 888 buf[76] = (1 << 2 | 1 << 1); 889 buf[78] = (1 << 5); 890 buf[80] = (0x1f << 4); 891 buf[82] = (1 << 4); 892 buf[83] = (1 << 14); 893 buf[84] = (1 << 14); 894 buf[85] = (1 << 4); 895 buf[87] = (1 << 14); 896 buf[88] = (1 << 14 | 0x7f); 897 ahci_write_fis_piosetup(p); 898 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 899 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 900 } 901} 902 903static void 904atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 905{ 906 uint8_t buf[36]; 907 uint8_t *acmd; 908 int len; 909 910 acmd = cfis + 0x40; 911 912 buf[0] = 0x05; 913 buf[1] = 0x80; 914 buf[2] = 0x00; 915 buf[3] = 0x21; 916 buf[4] = 31; 917 buf[5] = 0; 918 buf[6] = 0; 919 buf[7] = 0; 920 atapi_string(buf + 8, "BHYVE", 8); 921 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 922 atapi_string(buf + 32, "001", 4); 923 924 len = sizeof(buf); 925 if (len > acmd[4]) 926 len = acmd[4]; 927 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 928 write_prdt(p, slot, cfis, buf, len); 929 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 930} 931 932static void 933atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 934{ 935 uint8_t buf[8]; 936 uint64_t sectors; 937 938 sectors = blockif_size(p->bctx) / 2048; 939 be32enc(buf, sectors - 1); 940 be32enc(buf + 4, 2048); 941 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 942 write_prdt(p, slot, cfis, buf, sizeof(buf)); 943 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 944} 945 946static void 947atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 948{ 949 uint8_t *acmd; 950 uint8_t format; 951 int len; 952 953 acmd = cfis + 0x40; 954 955 len = be16dec(acmd + 7); 956 format = acmd[9] >> 6; 957 switch (format) { 958 case 0: 959 { 960 int msf, size; 961 uint64_t sectors; 962 uint8_t start_track, buf[20], *bp; 963 964 msf = (acmd[1] >> 1) & 1; 965 start_track = acmd[6]; 966 if (start_track > 1 && start_track != 0xaa) { 967 uint32_t tfd; 968 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 969 p->asc = 0x24; 970 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 971 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 972 ahci_write_fis_d2h(p, slot, cfis, tfd); 973 return; 974 } 975 bp = buf + 2; 976 *bp++ = 1; 977 *bp++ = 1; 978 if (start_track <= 1) { 979 *bp++ = 0; 980 *bp++ = 0x14; 981 *bp++ = 1; 982 *bp++ = 0; 983 if (msf) { 984 *bp++ = 0; 985 lba_to_msf(bp, 0); 986 bp += 3; 987 } else { 988 *bp++ = 0; 989 *bp++ = 0; 990 *bp++ = 0; 991 *bp++ = 0; 992 } 993 } 994 *bp++ = 0; 995 *bp++ = 0x14; 996 *bp++ = 0xaa; 997 *bp++ = 0; 998 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 999 sectors >>= 2; 1000 if (msf) { 1001 *bp++ = 0; 1002 lba_to_msf(bp, sectors); 1003 bp += 3; 1004 } else { 1005 be32enc(bp, sectors); 1006 bp += 4; 1007 } 1008 size = bp - buf; 1009 be16enc(buf, size - 2); 1010 if (len > size) 1011 len = size; 1012 write_prdt(p, slot, cfis, buf, len); 1013 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1014 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1015 break; 1016 } 1017 case 1: 1018 { 1019 uint8_t buf[12]; 1020 1021 memset(buf, 0, sizeof(buf)); 1022 buf[1] = 0xa; 1023 buf[2] = 0x1; 1024 buf[3] = 0x1; 1025 if (len > sizeof(buf)) 1026 len = sizeof(buf); 1027 write_prdt(p, slot, cfis, buf, len); 1028 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1029 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1030 break; 1031 } 1032 case 2: 1033 { 1034 int msf, size; 1035 uint64_t sectors; 1036 uint8_t start_track, *bp, buf[50]; 1037 1038 msf = (acmd[1] >> 1) & 1; 1039 start_track = acmd[6]; 1040 bp = buf + 2; 1041 *bp++ = 1; 1042 *bp++ = 1; 1043 1044 *bp++ = 1; 1045 *bp++ = 0x14; 1046 *bp++ = 0; 1047 *bp++ = 0xa0; 1048 *bp++ = 0; 1049 *bp++ = 0; 1050 *bp++ = 0; 1051 *bp++ = 0; 1052 *bp++ = 1; 1053 *bp++ = 0; 1054 *bp++ = 0; 1055 1056 *bp++ = 1; 1057 *bp++ = 0x14; 1058 *bp++ = 0; 1059 *bp++ = 0xa1; 1060 *bp++ = 0; 1061 *bp++ = 0; 1062 *bp++ = 0; 1063 *bp++ = 0; 1064 *bp++ = 1; 1065 *bp++ = 0; 1066 *bp++ = 0; 1067 1068 *bp++ = 1; 1069 *bp++ = 0x14; 1070 *bp++ = 0; 1071 *bp++ = 0xa2; 1072 *bp++ = 0; 1073 *bp++ = 0; 1074 *bp++ = 0; 1075 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1076 sectors >>= 2; 1077 if (msf) { 1078 *bp++ = 0; 1079 lba_to_msf(bp, sectors); 1080 bp += 3; 1081 } else { 1082 be32enc(bp, sectors); 1083 bp += 4; 1084 } 1085 1086 *bp++ = 1; 1087 *bp++ = 0x14; 1088 *bp++ = 0; 1089 *bp++ = 1; 1090 *bp++ = 0; 1091 *bp++ = 0; 1092 *bp++ = 0; 1093 if (msf) { 1094 *bp++ = 0; 1095 lba_to_msf(bp, 0); 1096 bp += 3; 1097 } else { 1098 *bp++ = 0; 1099 *bp++ = 0; 1100 *bp++ = 0; 1101 *bp++ = 0; 1102 } 1103 1104 size = bp - buf; 1105 be16enc(buf, size - 2); 1106 if (len > size) 1107 len = size; 1108 write_prdt(p, slot, cfis, buf, len); 1109 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1110 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1111 break; 1112 } 1113 default: 1114 { 1115 uint32_t tfd; 1116 1117 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1118 p->asc = 0x24; 1119 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1120 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1121 ahci_write_fis_d2h(p, slot, cfis, tfd); 1122 break; 1123 } 1124 } 1125} 1126 1127static void 1128atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, 1129 uint32_t done, int seek) 1130{ 1131 struct ahci_ioreq *aior; 1132 struct ahci_cmd_hdr *hdr; 1133 struct ahci_prdt_entry *prdt; 1134 struct blockif_req *breq; 1135 struct pci_ahci_softc *sc; 1136 uint8_t *acmd; 1137 uint64_t lba; 1138 uint32_t len; 1139 int i, err, iovcnt; 1140 1141 sc = p->pr_sc; 1142 acmd = cfis + 0x40; 1143 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1144 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1145 1146 prdt += seek; 1147 lba = be32dec(acmd + 2); 1148 if (acmd[0] == READ_10) 1149 len = be16dec(acmd + 7); 1150 else 1151 len = be32dec(acmd + 6); 1152 if (len == 0) { 1153 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1154 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1155 } 1156 lba *= 2048; 1157 len *= 2048; 1158 1159 /* 1160 * Pull request off free list 1161 */ 1162 aior = STAILQ_FIRST(&p->iofhd); 1163 assert(aior != NULL); 1164 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1165 aior->cfis = cfis; 1166 aior->slot = slot; 1167 aior->len = len; 1168 aior->done = done; 1169 breq = &aior->io_req; 1170 breq->br_offset = lba + done; 1171 iovcnt = hdr->prdtl - seek; 1172 if (iovcnt > BLOCKIF_IOV_MAX) { 1173 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX; 1174 iovcnt = BLOCKIF_IOV_MAX; 1175 } else 1176 aior->prdtl = 0; 1177 breq->br_iovcnt = iovcnt; 1178 1179 /* 1180 * Mark this command in-flight. 1181 */ 1182 p->pending |= 1 << slot; 1183 1184 /* 1185 * Stuff request onto busy list 1186 */ 1187 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1188 1189 /* 1190 * Build up the iovec based on the prdt 1191 */ 1192 for (i = 0; i < iovcnt; i++) { 1193 uint32_t dbcsz; 1194 1195 dbcsz = (prdt->dbc & DBCMASK) + 1; 1196 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc), 1197 prdt->dba, dbcsz); 1198 breq->br_iov[i].iov_len = dbcsz; 1199 aior->done += dbcsz; 1200 prdt++; 1201 } 1202 err = blockif_read(p->bctx, breq); 1203 assert(err == 0); 1204} 1205 1206static void 1207atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1208{ 1209 uint8_t buf[64]; 1210 uint8_t *acmd; 1211 int len; 1212 1213 acmd = cfis + 0x40; 1214 len = acmd[4]; 1215 if (len > sizeof(buf)) 1216 len = sizeof(buf); 1217 memset(buf, 0, len); 1218 buf[0] = 0x70 | (1 << 7); 1219 buf[2] = p->sense_key; 1220 buf[7] = 10; 1221 buf[12] = p->asc; 1222 write_prdt(p, slot, cfis, buf, len); 1223 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1224 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1225} 1226 1227static void 1228atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1229{ 1230 uint8_t *acmd = cfis + 0x40; 1231 uint32_t tfd; 1232 1233 switch (acmd[4] & 3) { 1234 case 0: 1235 case 1: 1236 case 3: 1237 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1238 tfd = ATA_S_READY | ATA_S_DSC; 1239 break; 1240 case 2: 1241 /* TODO eject media */ 1242 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1243 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1244 p->asc = 0x53; 1245 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1246 break; 1247 } 1248 ahci_write_fis_d2h(p, slot, cfis, tfd); 1249} 1250 1251static void 1252atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1253{ 1254 uint8_t *acmd; 1255 uint32_t tfd; 1256 uint8_t pc, code; 1257 int len; 1258 1259 acmd = cfis + 0x40; 1260 len = be16dec(acmd + 7); 1261 pc = acmd[2] >> 6; 1262 code = acmd[2] & 0x3f; 1263 1264 switch (pc) { 1265 case 0: 1266 switch (code) { 1267 case MODEPAGE_RW_ERROR_RECOVERY: 1268 { 1269 uint8_t buf[16]; 1270 1271 if (len > sizeof(buf)) 1272 len = sizeof(buf); 1273 1274 memset(buf, 0, sizeof(buf)); 1275 be16enc(buf, 16 - 2); 1276 buf[2] = 0x70; 1277 buf[8] = 0x01; 1278 buf[9] = 16 - 10; 1279 buf[11] = 0x05; 1280 write_prdt(p, slot, cfis, buf, len); 1281 tfd = ATA_S_READY | ATA_S_DSC; 1282 break; 1283 } 1284 case MODEPAGE_CD_CAPABILITIES: 1285 { 1286 uint8_t buf[30]; 1287 1288 if (len > sizeof(buf)) 1289 len = sizeof(buf); 1290 1291 memset(buf, 0, sizeof(buf)); 1292 be16enc(buf, 30 - 2); 1293 buf[2] = 0x70; 1294 buf[8] = 0x2A; 1295 buf[9] = 30 - 10; 1296 buf[10] = 0x08; 1297 buf[12] = 0x71; 1298 be16enc(&buf[18], 2); 1299 be16enc(&buf[20], 512); 1300 write_prdt(p, slot, cfis, buf, len); 1301 tfd = ATA_S_READY | ATA_S_DSC; 1302 break; 1303 } 1304 default: 1305 goto error; 1306 break; 1307 } 1308 break; 1309 case 3: 1310 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1311 p->asc = 0x39; 1312 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1313 break; 1314error: 1315 case 1: 1316 case 2: 1317 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1318 p->asc = 0x24; 1319 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1320 break; 1321 } 1322 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1323 ahci_write_fis_d2h(p, slot, cfis, tfd); 1324} 1325 1326static void 1327atapi_get_event_status_notification(struct ahci_port *p, int slot, 1328 uint8_t *cfis) 1329{ 1330 uint8_t *acmd; 1331 uint32_t tfd; 1332 1333 acmd = cfis + 0x40; 1334 1335 /* we don't support asynchronous operation */ 1336 if (!(acmd[1] & 1)) { 1337 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1338 p->asc = 0x24; 1339 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1340 } else { 1341 uint8_t buf[8]; 1342 int len; 1343 1344 len = be16dec(acmd + 7); 1345 if (len > sizeof(buf)) 1346 len = sizeof(buf); 1347 1348 memset(buf, 0, sizeof(buf)); 1349 be16enc(buf, 8 - 2); 1350 buf[2] = 0x04; 1351 buf[3] = 0x10; 1352 buf[5] = 0x02; 1353 write_prdt(p, slot, cfis, buf, len); 1354 tfd = ATA_S_READY | ATA_S_DSC; 1355 } 1356 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1357 ahci_write_fis_d2h(p, slot, cfis, tfd); 1358} 1359 1360static void 1361handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1362{ 1363 uint8_t *acmd; 1364 1365 acmd = cfis + 0x40; 1366 1367#ifdef AHCI_DEBUG 1368 { 1369 int i; 1370 DPRINTF("ACMD:"); 1371 for (i = 0; i < 16; i++) 1372 DPRINTF("%02x ", acmd[i]); 1373 DPRINTF("\n"); 1374 } 1375#endif 1376 1377 switch (acmd[0]) { 1378 case TEST_UNIT_READY: 1379 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1380 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1381 break; 1382 case INQUIRY: 1383 atapi_inquiry(p, slot, cfis); 1384 break; 1385 case READ_CAPACITY: 1386 atapi_read_capacity(p, slot, cfis); 1387 break; 1388 case PREVENT_ALLOW: 1389 /* TODO */ 1390 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1391 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1392 break; 1393 case READ_TOC: 1394 atapi_read_toc(p, slot, cfis); 1395 break; 1396 case READ_10: 1397 case READ_12: 1398 atapi_read(p, slot, cfis, 0, 0); 1399 break; 1400 case REQUEST_SENSE: 1401 atapi_request_sense(p, slot, cfis); 1402 break; 1403 case START_STOP_UNIT: 1404 atapi_start_stop_unit(p, slot, cfis); 1405 break; 1406 case MODE_SENSE_10: 1407 atapi_mode_sense(p, slot, cfis); 1408 break; 1409 case GET_EVENT_STATUS_NOTIFICATION: 1410 atapi_get_event_status_notification(p, slot, cfis); 1411 break; 1412 default: 1413 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1414 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1415 p->asc = 0x20; 1416 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1417 ATA_S_READY | ATA_S_ERROR); 1418 break; 1419 } 1420} 1421 1422static void 1423ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1424{ 1425 1426 switch (cfis[2]) { 1427 case ATA_ATA_IDENTIFY: 1428 handle_identify(p, slot, cfis); 1429 break; 1430 case ATA_SETFEATURES: 1431 { 1432 switch (cfis[3]) { 1433 case ATA_SF_ENAB_SATA_SF: 1434 switch (cfis[12]) { 1435 case ATA_SATA_SF_AN: 1436 p->tfd = ATA_S_DSC | ATA_S_READY; 1437 break; 1438 default: 1439 p->tfd = ATA_S_ERROR | ATA_S_READY; 1440 p->tfd |= (ATA_ERROR_ABORT << 8); 1441 break; 1442 } 1443 break; 1444 case ATA_SF_ENAB_WCACHE: 1445 case ATA_SF_DIS_WCACHE: 1446 case ATA_SF_ENAB_RCACHE: 1447 case ATA_SF_DIS_RCACHE: 1448 p->tfd = ATA_S_DSC | ATA_S_READY; 1449 break; 1450 case ATA_SF_SETXFER: 1451 { 1452 switch (cfis[12] & 0xf8) { 1453 case ATA_PIO: 1454 case ATA_PIO0: 1455 break; 1456 case ATA_WDMA0: 1457 case ATA_UDMA0: 1458 p->xfermode = (cfis[12] & 0x7); 1459 break; 1460 } 1461 p->tfd = ATA_S_DSC | ATA_S_READY; 1462 break; 1463 } 1464 default: 1465 p->tfd = ATA_S_ERROR | ATA_S_READY; 1466 p->tfd |= (ATA_ERROR_ABORT << 8); 1467 break; 1468 } 1469 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1470 break; 1471 } 1472 case ATA_SET_MULTI: 1473 if (cfis[12] != 0 && 1474 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1475 p->tfd = ATA_S_ERROR | ATA_S_READY; 1476 p->tfd |= (ATA_ERROR_ABORT << 8); 1477 } else { 1478 p->mult_sectors = cfis[12]; 1479 p->tfd = ATA_S_DSC | ATA_S_READY; 1480 } 1481 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1482 break; 1483 case ATA_READ: 1484 case ATA_WRITE: 1485 case ATA_READ48: 1486 case ATA_WRITE48: 1487 case ATA_READ_MUL: 1488 case ATA_WRITE_MUL: 1489 case ATA_READ_MUL48: 1490 case ATA_WRITE_MUL48: 1491 case ATA_READ_DMA: 1492 case ATA_WRITE_DMA: 1493 case ATA_READ_DMA48: 1494 case ATA_WRITE_DMA48: 1495 case ATA_READ_FPDMA_QUEUED: 1496 case ATA_WRITE_FPDMA_QUEUED: 1497 ahci_handle_dma(p, slot, cfis, 0, 0); 1498 break; 1499 case ATA_FLUSHCACHE: 1500 case ATA_FLUSHCACHE48: 1501 ahci_handle_flush(p, slot, cfis); 1502 break; 1503 case ATA_DATA_SET_MANAGEMENT: 1504 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1505 cfis[13] == 0 && cfis[12] == 1) { 1506 ahci_handle_dsm_trim(p, slot, cfis, 0); 1507 break; 1508 } 1509 ahci_write_fis_d2h(p, slot, cfis, 1510 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1511 break; 1512 case ATA_STANDBY_CMD: 1513 break; 1514 case ATA_NOP: 1515 case ATA_STANDBY_IMMEDIATE: 1516 case ATA_IDLE_IMMEDIATE: 1517 case ATA_SLEEP: 1518 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1519 break; 1520 case ATA_ATAPI_IDENTIFY: 1521 handle_atapi_identify(p, slot, cfis); 1522 break; 1523 case ATA_PACKET_CMD: 1524 if (!p->atapi) { 1525 ahci_write_fis_d2h(p, slot, cfis, 1526 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1527 } else 1528 handle_packet_cmd(p, slot, cfis); 1529 break; 1530 default: 1531 WPRINTF("Unsupported cmd:%02x\n", cfis[2]); 1532 ahci_write_fis_d2h(p, slot, cfis, 1533 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1534 break; 1535 } 1536} 1537 1538static void 1539ahci_handle_slot(struct ahci_port *p, int slot) 1540{ 1541 struct ahci_cmd_hdr *hdr; 1542 struct ahci_prdt_entry *prdt; 1543 struct pci_ahci_softc *sc; 1544 uint8_t *cfis; 1545 int cfl; 1546 1547 sc = p->pr_sc; 1548 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1549 cfl = (hdr->flags & 0x1f) * 4; 1550 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1551 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1552 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1553 1554#ifdef AHCI_DEBUG 1555 DPRINTF("\ncfis:"); 1556 for (i = 0; i < cfl; i++) { 1557 if (i % 10 == 0) 1558 DPRINTF("\n"); 1559 DPRINTF("%02x ", cfis[i]); 1560 } 1561 DPRINTF("\n"); 1562 1563 for (i = 0; i < hdr->prdtl; i++) { 1564 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba); 1565 prdt++; 1566 } 1567#endif 1568 1569 if (cfis[0] != FIS_TYPE_REGH2D) { 1570 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]); 1571 return; 1572 } 1573 1574 if (cfis[1] & 0x80) { 1575 ahci_handle_cmd(p, slot, cfis); 1576 } else { 1577 if (cfis[15] & (1 << 2)) 1578 p->reset = 1; 1579 else if (p->reset) { 1580 p->reset = 0; 1581 ahci_port_reset(p); 1582 } 1583 p->ci &= ~(1 << slot); 1584 } 1585} 1586 1587static void 1588ahci_handle_port(struct ahci_port *p) 1589{ 1590 int i; 1591 1592 if (!(p->cmd & AHCI_P_CMD_ST)) 1593 return; 1594 1595 /* 1596 * Search for any new commands to issue ignoring those that 1597 * are already in-flight. 1598 */ 1599 for (i = 0; (i < 32) && p->ci; i++) { 1600 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) { 1601 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1602 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT; 1603 ahci_handle_slot(p, i); 1604 } 1605 } 1606} 1607 1608/* 1609 * blockif callback routine - this runs in the context of the blockif 1610 * i/o thread, so the mutex needs to be acquired. 1611 */ 1612static void 1613ata_ioreq_cb(struct blockif_req *br, int err) 1614{ 1615 struct ahci_cmd_hdr *hdr; 1616 struct ahci_ioreq *aior; 1617 struct ahci_port *p; 1618 struct pci_ahci_softc *sc; 1619 uint32_t tfd; 1620 uint8_t *cfis; 1621 int pending, slot, ncq, dsm; 1622 1623 DPRINTF("%s %d\n", __func__, err); 1624 1625 ncq = dsm = 0; 1626 aior = br->br_param; 1627 p = aior->io_pr; 1628 cfis = aior->cfis; 1629 slot = aior->slot; 1630 pending = aior->prdtl; 1631 sc = p->pr_sc; 1632 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1633 1634 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1635 cfis[2] == ATA_READ_FPDMA_QUEUED) 1636 ncq = 1; 1637 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) 1638 dsm = 1; 1639 1640 pthread_mutex_lock(&sc->mtx); 1641 1642 /* 1643 * Delete the blockif request from the busy list 1644 */ 1645 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1646 1647 /* 1648 * Move the blockif request back to the free list 1649 */ 1650 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1651 1652 if (dsm) { 1653 if (aior->done != aior->len && !err) { 1654 ahci_handle_dsm_trim(p, slot, cfis, aior->done); 1655 goto out; 1656 } 1657 } else { 1658 if (pending && !err) { 1659 ahci_handle_dma(p, slot, cfis, aior->done, 1660 hdr->prdtl - pending); 1661 goto out; 1662 } 1663 } 1664 1665 if (!err && aior->done == aior->len) { 1666 tfd = ATA_S_READY | ATA_S_DSC; 1667 if (ncq) 1668 hdr->prdbc = 0; 1669 else 1670 hdr->prdbc = aior->len; 1671 } else { 1672 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 1673 hdr->prdbc = 0; 1674 if (ncq) 1675 p->serr |= (1 << slot); 1676 } 1677 1678 if (ncq) { 1679 p->sact &= ~(1 << slot); 1680 ahci_write_fis_sdb(p, slot, tfd); 1681 } else 1682 ahci_write_fis_d2h(p, slot, cfis, tfd); 1683 1684 /* 1685 * This command is now complete. 1686 */ 1687 p->pending &= ~(1 << slot); 1688 1689 ahci_check_stopped(p); 1690out: 1691 pthread_mutex_unlock(&sc->mtx); 1692 DPRINTF("%s exit\n", __func__); 1693} 1694 1695static void 1696atapi_ioreq_cb(struct blockif_req *br, int err) 1697{ 1698 struct ahci_cmd_hdr *hdr; 1699 struct ahci_ioreq *aior; 1700 struct ahci_port *p; 1701 struct pci_ahci_softc *sc; 1702 uint8_t *cfis; 1703 uint32_t tfd; 1704 int pending, slot; 1705 1706 DPRINTF("%s %d\n", __func__, err); 1707 1708 aior = br->br_param; 1709 p = aior->io_pr; 1710 cfis = aior->cfis; 1711 slot = aior->slot; 1712 pending = aior->prdtl; 1713 sc = p->pr_sc; 1714 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 1715 1716 pthread_mutex_lock(&sc->mtx); 1717 1718 /* 1719 * Delete the blockif request from the busy list 1720 */ 1721 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1722 1723 /* 1724 * Move the blockif request back to the free list 1725 */ 1726 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1727 1728 if (pending && !err) { 1729 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending); 1730 goto out; 1731 } 1732 1733 if (!err && aior->done == aior->len) { 1734 tfd = ATA_S_READY | ATA_S_DSC; 1735 hdr->prdbc = aior->len; 1736 } else { 1737 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1738 p->asc = 0x21; 1739 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1740 hdr->prdbc = 0; 1741 } 1742 1743 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1744 ahci_write_fis_d2h(p, slot, cfis, tfd); 1745 1746 /* 1747 * This command is now complete. 1748 */ 1749 p->pending &= ~(1 << slot); 1750 1751 ahci_check_stopped(p); 1752out: 1753 pthread_mutex_unlock(&sc->mtx); 1754 DPRINTF("%s exit\n", __func__); 1755} 1756 1757static void 1758pci_ahci_ioreq_init(struct ahci_port *pr) 1759{ 1760 struct ahci_ioreq *vr; 1761 int i; 1762 1763 pr->ioqsz = blockif_queuesz(pr->bctx); 1764 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 1765 STAILQ_INIT(&pr->iofhd); 1766 1767 /* 1768 * Add all i/o request entries to the free queue 1769 */ 1770 for (i = 0; i < pr->ioqsz; i++) { 1771 vr = &pr->ioreq[i]; 1772 vr->io_pr = pr; 1773 if (!pr->atapi) 1774 vr->io_req.br_callback = ata_ioreq_cb; 1775 else 1776 vr->io_req.br_callback = atapi_ioreq_cb; 1777 vr->io_req.br_param = vr; 1778 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 1779 } 1780 1781 TAILQ_INIT(&pr->iobhd); 1782} 1783 1784static void 1785pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1786{ 1787 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1788 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1789 struct ahci_port *p = &sc->port[port]; 1790 1791 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1792 port, offset, value); 1793 1794 switch (offset) { 1795 case AHCI_P_CLB: 1796 p->clb = value; 1797 break; 1798 case AHCI_P_CLBU: 1799 p->clbu = value; 1800 break; 1801 case AHCI_P_FB: 1802 p->fb = value; 1803 break; 1804 case AHCI_P_FBU: 1805 p->fbu = value; 1806 break; 1807 case AHCI_P_IS: 1808 p->is &= ~value; 1809 break; 1810 case AHCI_P_IE: 1811 p->ie = value & 0xFDC000FF; 1812 ahci_generate_intr(sc); 1813 break; 1814 case AHCI_P_CMD: 1815 { 1816 p->cmd = value; 1817 1818 if (!(value & AHCI_P_CMD_ST)) { 1819 ahci_port_stop(p); 1820 } else { 1821 uint64_t clb; 1822 1823 p->cmd |= AHCI_P_CMD_CR; 1824 clb = (uint64_t)p->clbu << 32 | p->clb; 1825 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 1826 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 1827 } 1828 1829 if (value & AHCI_P_CMD_FRE) { 1830 uint64_t fb; 1831 1832 p->cmd |= AHCI_P_CMD_FR; 1833 fb = (uint64_t)p->fbu << 32 | p->fb; 1834 /* we don't support FBSCP, so rfis size is 256Bytes */ 1835 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 1836 } else { 1837 p->cmd &= ~AHCI_P_CMD_FR; 1838 } 1839 1840 if (value & AHCI_P_CMD_CLO) { 1841 p->tfd = 0; 1842 p->cmd &= ~AHCI_P_CMD_CLO; 1843 } 1844 1845 ahci_handle_port(p); 1846 break; 1847 } 1848 case AHCI_P_TFD: 1849 case AHCI_P_SIG: 1850 case AHCI_P_SSTS: 1851 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset); 1852 break; 1853 case AHCI_P_SCTL: 1854 if (!(p->cmd & AHCI_P_CMD_ST)) { 1855 if (value & ATA_SC_DET_RESET) 1856 ahci_port_reset(p); 1857 p->sctl = value; 1858 } 1859 break; 1860 case AHCI_P_SERR: 1861 p->serr &= ~value; 1862 break; 1863 case AHCI_P_SACT: 1864 p->sact |= value; 1865 break; 1866 case AHCI_P_CI: 1867 p->ci |= value; 1868 ahci_handle_port(p); 1869 break; 1870 case AHCI_P_SNTF: 1871 case AHCI_P_FBS: 1872 default: 1873 break; 1874 } 1875} 1876 1877static void 1878pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 1879{ 1880 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n", 1881 offset, value); 1882 1883 switch (offset) { 1884 case AHCI_CAP: 1885 case AHCI_PI: 1886 case AHCI_VS: 1887 case AHCI_CAP2: 1888 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset); 1889 break; 1890 case AHCI_GHC: 1891 if (value & AHCI_GHC_HR) 1892 ahci_reset(sc); 1893 else if (value & AHCI_GHC_IE) { 1894 sc->ghc |= AHCI_GHC_IE; 1895 ahci_generate_intr(sc); 1896 } 1897 break; 1898 case AHCI_IS: 1899 sc->is &= ~value; 1900 ahci_generate_intr(sc); 1901 break; 1902 default: 1903 break; 1904 } 1905} 1906 1907static void 1908pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 1909 int baridx, uint64_t offset, int size, uint64_t value) 1910{ 1911 struct pci_ahci_softc *sc = pi->pi_arg; 1912 1913 assert(baridx == 5); 1914 assert(size == 4); 1915 1916 pthread_mutex_lock(&sc->mtx); 1917 1918 if (offset < AHCI_OFFSET) 1919 pci_ahci_host_write(sc, offset, value); 1920 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 1921 pci_ahci_port_write(sc, offset, value); 1922 else 1923 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset); 1924 1925 pthread_mutex_unlock(&sc->mtx); 1926} 1927 1928static uint64_t 1929pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 1930{ 1931 uint32_t value; 1932 1933 switch (offset) { 1934 case AHCI_CAP: 1935 case AHCI_GHC: 1936 case AHCI_IS: 1937 case AHCI_PI: 1938 case AHCI_VS: 1939 case AHCI_CCCC: 1940 case AHCI_CCCP: 1941 case AHCI_EM_LOC: 1942 case AHCI_EM_CTL: 1943 case AHCI_CAP2: 1944 { 1945 uint32_t *p = &sc->cap; 1946 p += (offset - AHCI_CAP) / sizeof(uint32_t); 1947 value = *p; 1948 break; 1949 } 1950 default: 1951 value = 0; 1952 break; 1953 } 1954 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n", 1955 offset, value); 1956 1957 return (value); 1958} 1959 1960static uint64_t 1961pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 1962{ 1963 uint32_t value; 1964 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 1965 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 1966 1967 switch (offset) { 1968 case AHCI_P_CLB: 1969 case AHCI_P_CLBU: 1970 case AHCI_P_FB: 1971 case AHCI_P_FBU: 1972 case AHCI_P_IS: 1973 case AHCI_P_IE: 1974 case AHCI_P_CMD: 1975 case AHCI_P_TFD: 1976 case AHCI_P_SIG: 1977 case AHCI_P_SSTS: 1978 case AHCI_P_SCTL: 1979 case AHCI_P_SERR: 1980 case AHCI_P_SACT: 1981 case AHCI_P_CI: 1982 case AHCI_P_SNTF: 1983 case AHCI_P_FBS: 1984 { 1985 uint32_t *p= &sc->port[port].clb; 1986 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 1987 value = *p; 1988 break; 1989 } 1990 default: 1991 value = 0; 1992 break; 1993 } 1994 1995 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n", 1996 port, offset, value); 1997 1998 return value; 1999} 2000 2001static uint64_t 2002pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2003 uint64_t offset, int size) 2004{ 2005 struct pci_ahci_softc *sc = pi->pi_arg; 2006 uint32_t value; 2007 2008 assert(baridx == 5); 2009 assert(size == 4); 2010 2011 pthread_mutex_lock(&sc->mtx); 2012 2013 if (offset < AHCI_OFFSET) 2014 value = pci_ahci_host_read(sc, offset); 2015 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP) 2016 value = pci_ahci_port_read(sc, offset); 2017 else { 2018 value = 0; 2019 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset); 2020 } 2021 2022 pthread_mutex_unlock(&sc->mtx); 2023 2024 return (value); 2025} 2026 2027static int 2028pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi) 2029{ 2030 char bident[sizeof("XX:X:X")]; 2031 struct blockif_ctxt *bctxt; 2032 struct pci_ahci_softc *sc; 2033 int ret, slots; 2034 2035 ret = 0; 2036 2037 if (opts == NULL) { 2038 fprintf(stderr, "pci_ahci: backing device required\n"); 2039 return (1); 2040 } 2041 2042#ifdef AHCI_DEBUG 2043 dbg = fopen("/tmp/log", "w+"); 2044#endif 2045 2046 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2047 pi->pi_arg = sc; 2048 sc->asc_pi = pi; 2049 sc->ports = MAX_PORTS; 2050 2051 /* 2052 * Only use port 0 for a backing device. All other ports will be 2053 * marked as unused 2054 */ 2055 sc->port[0].atapi = atapi; 2056 2057 /* 2058 * Attempt to open the backing image. Use the PCI 2059 * slot/func for the identifier string. 2060 */ 2061 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func); 2062 bctxt = blockif_open(opts, bident); 2063 if (bctxt == NULL) { 2064 ret = 1; 2065 goto open_fail; 2066 } 2067 sc->port[0].bctx = bctxt; 2068 sc->port[0].pr_sc = sc; 2069 2070 /* 2071 * Allocate blockif request structures and add them 2072 * to the free list 2073 */ 2074 pci_ahci_ioreq_init(&sc->port[0]); 2075 2076 pthread_mutex_init(&sc->mtx, NULL); 2077 2078 /* Intel ICH8 AHCI */ 2079 slots = sc->port[0].ioqsz; 2080 if (slots > 32) 2081 slots = 32; 2082 --slots; 2083 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2084 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2085 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2086 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2087 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2088 2089 /* Only port 0 implemented */ 2090 sc->pi = 1; 2091 sc->vs = 0x10300; 2092 sc->cap2 = AHCI_CAP2_APST; 2093 ahci_reset(sc); 2094 2095 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2096 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2097 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2098 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2099 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2100 pci_emul_add_msicap(pi, 1); 2101 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2102 AHCI_OFFSET + sc->ports * AHCI_STEP); 2103 2104 pci_lintr_request(pi); 2105 2106open_fail: 2107 if (ret) { 2108 blockif_close(sc->port[0].bctx); 2109 free(sc); 2110 } 2111 2112 return (ret); 2113} 2114 2115static int 2116pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2117{ 2118 2119 return (pci_ahci_init(ctx, pi, opts, 0)); 2120} 2121 2122static int 2123pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 2124{ 2125 2126 return (pci_ahci_init(ctx, pi, opts, 1)); 2127} 2128 2129/* 2130 * Use separate emulation names to distinguish drive and atapi devices 2131 */ 2132struct pci_devemu pci_de_ahci_hd = { 2133 .pe_emu = "ahci-hd", 2134 .pe_init = pci_ahci_hd_init, 2135 .pe_barwrite = pci_ahci_write, 2136 .pe_barread = pci_ahci_read 2137}; 2138PCI_EMUL_SET(pci_de_ahci_hd); 2139 2140struct pci_devemu pci_de_ahci_cd = { 2141 .pe_emu = "ahci-cd", 2142 .pe_init = pci_ahci_atapi_init, 2143 .pe_barwrite = pci_ahci_write, 2144 .pe_barread = pci_ahci_read 2145}; 2146PCI_EMUL_SET(pci_de_ahci_cd); 2147