1221828Sgrehan/*- 2242131Sgrehan * Copyright (c) 2012 NetApp, Inc. 3221828Sgrehan * All rights reserved. 4221828Sgrehan * 5221828Sgrehan * Redistribution and use in source and binary forms, with or without 6221828Sgrehan * modification, are permitted provided that the following conditions 7221828Sgrehan * are met: 8221828Sgrehan * 1. Redistributions of source code must retain the above copyright 9221828Sgrehan * notice, this list of conditions and the following disclaimer. 10221828Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 11221828Sgrehan * notice, this list of conditions and the following disclaimer in the 12221828Sgrehan * documentation and/or other materials provided with the distribution. 13221828Sgrehan * 14221828Sgrehan * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 15221828Sgrehan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16221828Sgrehan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17221828Sgrehan * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 18221828Sgrehan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19221828Sgrehan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20221828Sgrehan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21221828Sgrehan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22221828Sgrehan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23221828Sgrehan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24221828Sgrehan * SUCH DAMAGE. 25221828Sgrehan * 26221828Sgrehan * $FreeBSD: releng/10.2/usr.sbin/bhyve/mptbl.c 268972 2014-07-22 03:14:37Z jhb $ 27221828Sgrehan */ 28221828Sgrehan 29221828Sgrehan#include <sys/cdefs.h> 30221828Sgrehan__FBSDID("$FreeBSD: releng/10.2/usr.sbin/bhyve/mptbl.c 268972 2014-07-22 03:14:37Z jhb $"); 31221828Sgrehan 32221828Sgrehan#include <sys/types.h> 33242131Sgrehan#include <sys/errno.h> 34242131Sgrehan#include <x86/mptable.h> 35221828Sgrehan 36221828Sgrehan#include <stdio.h> 37221828Sgrehan#include <string.h> 38221828Sgrehan 39261090Sjhb#include "acpi.h" 40244167Sgrehan#include "bhyverun.h" 41242131Sgrehan#include "mptbl.h" 42267393Sjhb#include "pci_emul.h" 43221828Sgrehan 44242131Sgrehan#define MPTABLE_BASE 0xF0000 45221828Sgrehan 46247523Sneel/* floating pointer length + maximum length of configuration table */ 47247523Sneel#define MPTABLE_MAX_LENGTH (65536 + 16) 48247523Sneel 49242131Sgrehan#define LAPIC_PADDR 0xFEE00000 50242131Sgrehan#define LAPIC_VERSION 16 51221828Sgrehan 52242131Sgrehan#define IOAPIC_PADDR 0xFEC00000 53242131Sgrehan#define IOAPIC_VERSION 0x11 54221828Sgrehan 55242131Sgrehan#define MP_SPECREV 4 56242131Sgrehan#define MPFP_SIG "_MP_" 57242131Sgrehan 58242131Sgrehan/* Configuration header defines */ 59242131Sgrehan#define MPCH_SIG "PCMP" 60242131Sgrehan#define MPCH_OEMID "BHyVe " 61242131Sgrehan#define MPCH_OEMID_LEN 8 62242131Sgrehan#define MPCH_PRODID "Hypervisor " 63242131Sgrehan#define MPCH_PRODID_LEN 12 64242131Sgrehan 65242131Sgrehan/* Processor entry defines */ 66242131Sgrehan#define MPEP_SIG_FAMILY 6 /* XXX bhyve should supply this */ 67242131Sgrehan#define MPEP_SIG_MODEL 26 68242131Sgrehan#define MPEP_SIG_STEPPING 5 69242131Sgrehan#define MPEP_SIG \ 70242131Sgrehan ((MPEP_SIG_FAMILY << 8) | \ 71242131Sgrehan (MPEP_SIG_MODEL << 4) | \ 72242131Sgrehan (MPEP_SIG_STEPPING)) 73242131Sgrehan 74242131Sgrehan#define MPEP_FEATURES (0xBFEBFBFF) /* XXX Intel i7 */ 75242131Sgrehan 76262350Sjhb/* Number of local intr entries */ 77262350Sjhb#define MPEII_NUM_LOCAL_IRQ 2 78262350Sjhb 79242131Sgrehan/* Bus entry defines */ 80242131Sgrehan#define MPE_NUM_BUSES 2 81242131Sgrehan#define MPE_BUSNAME_LEN 6 82242131Sgrehan#define MPE_BUSNAME_ISA "ISA " 83242131Sgrehan#define MPE_BUSNAME_PCI "PCI " 84242131Sgrehan 85242131Sgrehanstatic void *oem_tbl_start; 86242131Sgrehanstatic int oem_tbl_size; 87242131Sgrehan 88221828Sgrehanstatic uint8_t 89242131Sgrehanmpt_compute_checksum(void *base, size_t len) 90221828Sgrehan{ 91242131Sgrehan uint8_t *bytes; 92242131Sgrehan uint8_t sum; 93242131Sgrehan 94242131Sgrehan for(bytes = base, sum = 0; len > 0; len--) { 95221828Sgrehan sum += *bytes++; 96221828Sgrehan } 97242131Sgrehan 98242131Sgrehan return (256 - sum); 99221828Sgrehan} 100221828Sgrehan 101221828Sgrehanstatic void 102242131Sgrehanmpt_build_mpfp(mpfps_t mpfp, vm_paddr_t gpa) 103221828Sgrehan{ 104242131Sgrehan 105221828Sgrehan memset(mpfp, 0, sizeof(*mpfp)); 106242131Sgrehan memcpy(mpfp->signature, MPFP_SIG, 4); 107242131Sgrehan mpfp->pap = gpa + sizeof(*mpfp); 108242131Sgrehan mpfp->length = 1; 109242131Sgrehan mpfp->spec_rev = MP_SPECREV; 110242131Sgrehan mpfp->checksum = mpt_compute_checksum(mpfp, sizeof(*mpfp)); 111221828Sgrehan} 112221828Sgrehan 113221828Sgrehanstatic void 114242131Sgrehanmpt_build_mpch(mpcth_t mpch) 115221828Sgrehan{ 116242131Sgrehan 117221828Sgrehan memset(mpch, 0, sizeof(*mpch)); 118242131Sgrehan memcpy(mpch->signature, MPCH_SIG, 4); 119242131Sgrehan mpch->spec_rev = MP_SPECREV; 120242131Sgrehan memcpy(mpch->oem_id, MPCH_OEMID, MPCH_OEMID_LEN); 121242131Sgrehan memcpy(mpch->product_id, MPCH_PRODID, MPCH_PRODID_LEN); 122242131Sgrehan mpch->apic_address = LAPIC_PADDR; 123221828Sgrehan} 124221828Sgrehan 125221828Sgrehanstatic void 126259837Sjhbmpt_build_proc_entries(proc_entry_ptr mpep, int ncpu) 127221828Sgrehan{ 128221828Sgrehan int i; 129221828Sgrehan 130242131Sgrehan for (i = 0; i < ncpu; i++) { 131221828Sgrehan memset(mpep, 0, sizeof(*mpep)); 132242131Sgrehan mpep->type = MPCT_ENTRY_PROCESSOR; 133242131Sgrehan mpep->apic_id = i; // XXX 134242131Sgrehan mpep->apic_version = LAPIC_VERSION; 135242131Sgrehan mpep->cpu_flags = PROCENTRY_FLAG_EN; 136242131Sgrehan if (i == 0) 137242131Sgrehan mpep->cpu_flags |= PROCENTRY_FLAG_BP; 138242131Sgrehan mpep->cpu_signature = MPEP_SIG; 139221828Sgrehan mpep->feature_flags = MPEP_FEATURES; 140221828Sgrehan mpep++; 141221828Sgrehan } 142221828Sgrehan} 143221828Sgrehan 144221828Sgrehanstatic void 145262350Sjhbmpt_build_localint_entries(int_entry_ptr mpie) 146262350Sjhb{ 147262350Sjhb 148262350Sjhb /* Hardcode LINT0 as ExtINT on all CPUs. */ 149262350Sjhb memset(mpie, 0, sizeof(*mpie)); 150262350Sjhb mpie->type = MPCT_ENTRY_LOCAL_INT; 151262350Sjhb mpie->int_type = INTENTRY_TYPE_EXTINT; 152262350Sjhb mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 153262350Sjhb INTENTRY_FLAGS_TRIGGER_CONFORM; 154262350Sjhb mpie->dst_apic_id = 0xff; 155262350Sjhb mpie->dst_apic_int = 0; 156262350Sjhb mpie++; 157262350Sjhb 158262350Sjhb /* Hardcode LINT1 as NMI on all CPUs. */ 159262350Sjhb memset(mpie, 0, sizeof(*mpie)); 160262350Sjhb mpie->type = MPCT_ENTRY_LOCAL_INT; 161262350Sjhb mpie->int_type = INTENTRY_TYPE_NMI; 162262350Sjhb mpie->int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 163262350Sjhb INTENTRY_FLAGS_TRIGGER_CONFORM; 164262350Sjhb mpie->dst_apic_id = 0xff; 165262350Sjhb mpie->dst_apic_int = 1; 166262350Sjhb} 167262350Sjhb 168262350Sjhbstatic void 169242131Sgrehanmpt_build_bus_entries(bus_entry_ptr mpeb) 170221828Sgrehan{ 171242131Sgrehan 172221828Sgrehan memset(mpeb, 0, sizeof(*mpeb)); 173242131Sgrehan mpeb->type = MPCT_ENTRY_BUS; 174256755Sgrehan mpeb->bus_id = 0; 175256755Sgrehan memcpy(mpeb->bus_type, MPE_BUSNAME_PCI, MPE_BUSNAME_LEN); 176221828Sgrehan mpeb++; 177221828Sgrehan 178221828Sgrehan memset(mpeb, 0, sizeof(*mpeb)); 179242131Sgrehan mpeb->type = MPCT_ENTRY_BUS; 180256755Sgrehan mpeb->bus_id = 1; 181256755Sgrehan memcpy(mpeb->bus_type, MPE_BUSNAME_ISA, MPE_BUSNAME_LEN); 182221828Sgrehan} 183221828Sgrehan 184221828Sgrehanstatic void 185242131Sgrehanmpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id) 186221828Sgrehan{ 187242131Sgrehan 188221828Sgrehan memset(mpei, 0, sizeof(*mpei)); 189242131Sgrehan mpei->type = MPCT_ENTRY_IOAPIC; 190242131Sgrehan mpei->apic_id = id; 191242131Sgrehan mpei->apic_version = IOAPIC_VERSION; 192242131Sgrehan mpei->apic_flags = IOAPICENTRY_FLAG_EN; 193242131Sgrehan mpei->apic_address = IOAPIC_PADDR; 194221828Sgrehan} 195221828Sgrehan 196267393Sjhbstatic int 197267393Sjhbmpt_count_ioint_entries(void) 198267393Sjhb{ 199268887Sjhb int bus, count; 200267393Sjhb 201268887Sjhb count = 0; 202268887Sjhb for (bus = 0; bus <= PCI_BUSMAX; bus++) 203268887Sjhb count += pci_count_lintr(bus); 204268887Sjhb 205267393Sjhb /* 206267393Sjhb * Always include entries for the first 16 pins along with a entry 207267393Sjhb * for each active PCI INTx pin. 208267393Sjhb */ 209268887Sjhb return (16 + count); 210267393Sjhb} 211267393Sjhb 212221828Sgrehanstatic void 213268972Sjhbmpt_generate_pci_int(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 214268972Sjhb void *arg) 215221828Sgrehan{ 216267393Sjhb int_entry_ptr *mpiep, mpie; 217267393Sjhb 218267393Sjhb mpiep = arg; 219267393Sjhb mpie = *mpiep; 220267393Sjhb memset(mpie, 0, sizeof(*mpie)); 221267393Sjhb 222267393Sjhb /* 223267393Sjhb * This is always after another I/O interrupt entry, so cheat 224267393Sjhb * and fetch the I/O APIC ID from the prior entry. 225267393Sjhb */ 226267393Sjhb mpie->type = MPCT_ENTRY_INT; 227267393Sjhb mpie->int_type = INTENTRY_TYPE_INT; 228268887Sjhb mpie->src_bus_id = bus; 229267393Sjhb mpie->src_bus_irq = slot << 2 | (pin - 1); 230267393Sjhb mpie->dst_apic_id = mpie[-1].dst_apic_id; 231267393Sjhb mpie->dst_apic_int = ioapic_irq; 232267393Sjhb 233267393Sjhb *mpiep = mpie + 1; 234267393Sjhb} 235267393Sjhb 236267393Sjhbstatic void 237267393Sjhbmpt_build_ioint_entries(int_entry_ptr mpie, int id) 238267393Sjhb{ 239268887Sjhb int pin, bus; 240221828Sgrehan 241221828Sgrehan /* 242221828Sgrehan * The following config is taken from kernel mptable.c 243221828Sgrehan * mptable_parse_default_config_ints(...), for now 244221828Sgrehan * just use the default config, tweek later if needed. 245221828Sgrehan */ 246221828Sgrehan 247267393Sjhb /* First, generate the first 16 pins. */ 248267393Sjhb for (pin = 0; pin < 16; pin++) { 249256755Sgrehan memset(mpie, 0, sizeof(*mpie)); 250256755Sgrehan mpie->type = MPCT_ENTRY_INT; 251256755Sgrehan mpie->src_bus_id = 1; 252256755Sgrehan mpie->dst_apic_id = id; 253221828Sgrehan 254221828Sgrehan /* 255242131Sgrehan * All default configs route IRQs from bus 0 to the first 16 256242131Sgrehan * pins of the first I/O APIC with an APIC ID of 2. 257221828Sgrehan */ 258256755Sgrehan mpie->dst_apic_int = pin; 259221828Sgrehan switch (pin) { 260221828Sgrehan case 0: 261221828Sgrehan /* Pin 0 is an ExtINT pin. */ 262256755Sgrehan mpie->int_type = INTENTRY_TYPE_EXTINT; 263221828Sgrehan break; 264221828Sgrehan case 2: 265221828Sgrehan /* IRQ 0 is routed to pin 2. */ 266256755Sgrehan mpie->int_type = INTENTRY_TYPE_INT; 267256755Sgrehan mpie->src_bus_irq = 0; 268221828Sgrehan break; 269261090Sjhb case SCI_INT: 270261090Sjhb /* ACPI SCI is level triggered and active-lo. */ 271261090Sjhb mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO | 272261090Sjhb INTENTRY_FLAGS_TRIGGER_LEVEL; 273261090Sjhb mpie->int_type = INTENTRY_TYPE_INT; 274261090Sjhb mpie->src_bus_irq = SCI_INT; 275261090Sjhb break; 276221828Sgrehan default: 277221828Sgrehan /* All other pins are identity mapped. */ 278256755Sgrehan mpie->int_type = INTENTRY_TYPE_INT; 279256755Sgrehan mpie->src_bus_irq = pin; 280221828Sgrehan break; 281221828Sgrehan } 282256755Sgrehan mpie++; 283221828Sgrehan } 284221828Sgrehan 285267393Sjhb /* Next, generate entries for any PCI INTx interrupts. */ 286268887Sjhb for (bus = 0; bus <= PCI_BUSMAX; bus++) 287268887Sjhb pci_walk_lintr(bus, mpt_generate_pci_int, &mpie); 288221828Sgrehan} 289221828Sgrehan 290242131Sgrehanvoid 291242131Sgrehanmptable_add_oemtbl(void *tbl, int tblsz) 292242131Sgrehan{ 293242131Sgrehan 294242131Sgrehan oem_tbl_start = tbl; 295242131Sgrehan oem_tbl_size = tblsz; 296242131Sgrehan} 297242131Sgrehan 298221828Sgrehanint 299259301Sgrehanmptable_build(struct vmctx *ctx, int ncpu) 300221828Sgrehan{ 301242131Sgrehan mpcth_t mpch; 302242131Sgrehan bus_entry_ptr mpeb; 303242131Sgrehan io_apic_entry_ptr mpei; 304259837Sjhb proc_entry_ptr mpep; 305242131Sgrehan mpfps_t mpfp; 306256755Sgrehan int_entry_ptr mpie; 307268887Sjhb int ioints, bus; 308242131Sgrehan char *curraddr; 309221828Sgrehan char *startaddr; 310221828Sgrehan 311248477Sneel startaddr = paddr_guest2host(ctx, MPTABLE_BASE, MPTABLE_MAX_LENGTH); 312247523Sneel if (startaddr == NULL) { 313268887Sjhb fprintf(stderr, "mptable requires mapped mem\n"); 314242131Sgrehan return (ENOMEM); 315221828Sgrehan } 316221828Sgrehan 317268887Sjhb /* 318268887Sjhb * There is no way to advertise multiple PCI hierarchies via MPtable 319268887Sjhb * so require that there is no PCI hierarchy with a non-zero bus 320268887Sjhb * number. 321268887Sjhb */ 322268887Sjhb for (bus = 1; bus <= PCI_BUSMAX; bus++) { 323268887Sjhb if (pci_bus_configured(bus)) { 324268887Sjhb fprintf(stderr, "MPtable is incompatible with " 325268887Sjhb "multiple PCI hierarchies.\r\n"); 326268887Sjhb fprintf(stderr, "MPtable generation can be disabled " 327268887Sjhb "by passing the -Y option to bhyve(8).\r\n"); 328268887Sjhb return (EINVAL); 329268887Sjhb } 330268887Sjhb } 331268887Sjhb 332247523Sneel curraddr = startaddr; 333242131Sgrehan mpfp = (mpfps_t)curraddr; 334242131Sgrehan mpt_build_mpfp(mpfp, MPTABLE_BASE); 335242131Sgrehan curraddr += sizeof(*mpfp); 336221828Sgrehan 337242131Sgrehan mpch = (mpcth_t)curraddr; 338242131Sgrehan mpt_build_mpch(mpch); 339242131Sgrehan curraddr += sizeof(*mpch); 340221828Sgrehan 341259837Sjhb mpep = (proc_entry_ptr)curraddr; 342242131Sgrehan mpt_build_proc_entries(mpep, ncpu); 343242131Sgrehan curraddr += sizeof(*mpep) * ncpu; 344242131Sgrehan mpch->entry_count += ncpu; 345221828Sgrehan 346242131Sgrehan mpeb = (bus_entry_ptr) curraddr; 347242131Sgrehan mpt_build_bus_entries(mpeb); 348242131Sgrehan curraddr += sizeof(*mpeb) * MPE_NUM_BUSES; 349242131Sgrehan mpch->entry_count += MPE_NUM_BUSES; 350242131Sgrehan 351259301Sgrehan mpei = (io_apic_entry_ptr)curraddr; 352259301Sgrehan mpt_build_ioapic_entries(mpei, 0); 353259301Sgrehan curraddr += sizeof(*mpei); 354259301Sgrehan mpch->entry_count++; 355239042Sneel 356256755Sgrehan mpie = (int_entry_ptr) curraddr; 357267393Sjhb ioints = mpt_count_ioint_entries(); 358267393Sjhb mpt_build_ioint_entries(mpie, 0); 359267393Sjhb curraddr += sizeof(*mpie) * ioints; 360267393Sjhb mpch->entry_count += ioints; 361221828Sgrehan 362262350Sjhb mpie = (int_entry_ptr)curraddr; 363262350Sjhb mpt_build_localint_entries(mpie); 364262350Sjhb curraddr += sizeof(*mpie) * MPEII_NUM_LOCAL_IRQ; 365262350Sjhb mpch->entry_count += MPEII_NUM_LOCAL_IRQ; 366262350Sjhb 367242131Sgrehan if (oem_tbl_start) { 368242131Sgrehan mpch->oem_table_pointer = curraddr - startaddr + MPTABLE_BASE; 369242131Sgrehan mpch->oem_table_size = oem_tbl_size; 370242131Sgrehan memcpy(curraddr, oem_tbl_start, oem_tbl_size); 371221828Sgrehan } 372221828Sgrehan 373242131Sgrehan mpch->base_table_length = curraddr - (char *)mpch; 374249173Sgrehan mpch->checksum = mpt_compute_checksum(mpch, mpch->base_table_length); 375221828Sgrehan 376242131Sgrehan return (0); 377221828Sgrehan} 378