trace.h revision 251767
1181624Skmacy/****************************************************************************** 2181624Skmacy * include/public/trace.h 3181624Skmacy * 4181624Skmacy * Permission is hereby granted, free of charge, to any person obtaining a copy 5181624Skmacy * of this software and associated documentation files (the "Software"), to 6181624Skmacy * deal in the Software without restriction, including without limitation the 7181624Skmacy * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 8181624Skmacy * sell copies of the Software, and to permit persons to whom the Software is 9181624Skmacy * furnished to do so, subject to the following conditions: 10181624Skmacy * 11181624Skmacy * The above copyright notice and this permission notice shall be included in 12181624Skmacy * all copies or substantial portions of the Software. 13181624Skmacy * 14181624Skmacy * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15181624Skmacy * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16181624Skmacy * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 17181624Skmacy * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18181624Skmacy * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 19181624Skmacy * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 20181624Skmacy * DEALINGS IN THE SOFTWARE. 21181624Skmacy * 22181624Skmacy * Mark Williamson, (C) 2004 Intel Research Cambridge 23181624Skmacy * Copyright (C) 2005 Bin Ren 24181624Skmacy */ 25181624Skmacy 26181624Skmacy#ifndef __XEN_PUBLIC_TRACE_H__ 27181624Skmacy#define __XEN_PUBLIC_TRACE_H__ 28181624Skmacy 29183375Skmacy#define TRACE_EXTRA_MAX 7 30183375Skmacy#define TRACE_EXTRA_SHIFT 28 31183375Skmacy 32181624Skmacy/* Trace classes */ 33181624Skmacy#define TRC_CLS_SHIFT 16 34183375Skmacy#define TRC_GEN 0x0001f000 /* General trace */ 35183375Skmacy#define TRC_SCHED 0x0002f000 /* Xen Scheduler trace */ 36183375Skmacy#define TRC_DOM0OP 0x0004f000 /* Xen DOM0 operation trace */ 37183375Skmacy#define TRC_HVM 0x0008f000 /* Xen HVM trace */ 38183375Skmacy#define TRC_MEM 0x0010f000 /* Xen memory trace */ 39183375Skmacy#define TRC_PV 0x0020f000 /* Xen PV traces */ 40183375Skmacy#define TRC_SHADOW 0x0040f000 /* Xen shadow tracing */ 41251767Sgibbs#define TRC_HW 0x0080f000 /* Xen hardware-related traces */ 42251767Sgibbs#define TRC_GUEST 0x0800f000 /* Guest-generated traces */ 43183375Skmacy#define TRC_ALL 0x0ffff000 44183375Skmacy#define TRC_HD_TO_EVENT(x) ((x)&0x0fffffff) 45183375Skmacy#define TRC_HD_CYCLE_FLAG (1UL<<31) 46183375Skmacy#define TRC_HD_INCLUDES_CYCLE_COUNT(x) ( !!( (x) & TRC_HD_CYCLE_FLAG ) ) 47183375Skmacy#define TRC_HD_EXTRA(x) (((x)>>TRACE_EXTRA_SHIFT)&TRACE_EXTRA_MAX) 48181624Skmacy 49181624Skmacy/* Trace subclasses */ 50181624Skmacy#define TRC_SUBCLS_SHIFT 12 51181624Skmacy 52181624Skmacy/* trace subclasses for SVM */ 53181624Skmacy#define TRC_HVM_ENTRYEXIT 0x00081000 /* VMENTRY and #VMEXIT */ 54181624Skmacy#define TRC_HVM_HANDLER 0x00082000 /* various HVM handlers */ 55181624Skmacy 56183375Skmacy#define TRC_SCHED_MIN 0x00021000 /* Just runstate changes */ 57251767Sgibbs#define TRC_SCHED_CLASS 0x00022000 /* Scheduler-specific */ 58183375Skmacy#define TRC_SCHED_VERBOSE 0x00028000 /* More inclusive scheduling */ 59183375Skmacy 60251767Sgibbs/* Trace classes for Hardware */ 61251767Sgibbs#define TRC_HW_PM 0x00801000 /* Power management traces */ 62251767Sgibbs#define TRC_HW_IRQ 0x00802000 /* Traces relating to the handling of IRQs */ 63251767Sgibbs 64181624Skmacy/* Trace events per class */ 65181624Skmacy#define TRC_LOST_RECORDS (TRC_GEN + 1) 66183375Skmacy#define TRC_TRACE_WRAP_BUFFER (TRC_GEN + 2) 67183375Skmacy#define TRC_TRACE_CPU_CHANGE (TRC_GEN + 3) 68181624Skmacy 69251767Sgibbs#define TRC_SCHED_RUNSTATE_CHANGE (TRC_SCHED_MIN + 1) 70251767Sgibbs#define TRC_SCHED_CONTINUE_RUNNING (TRC_SCHED_MIN + 2) 71183375Skmacy#define TRC_SCHED_DOM_ADD (TRC_SCHED_VERBOSE + 1) 72183375Skmacy#define TRC_SCHED_DOM_REM (TRC_SCHED_VERBOSE + 2) 73183375Skmacy#define TRC_SCHED_SLEEP (TRC_SCHED_VERBOSE + 3) 74183375Skmacy#define TRC_SCHED_WAKE (TRC_SCHED_VERBOSE + 4) 75183375Skmacy#define TRC_SCHED_YIELD (TRC_SCHED_VERBOSE + 5) 76183375Skmacy#define TRC_SCHED_BLOCK (TRC_SCHED_VERBOSE + 6) 77183375Skmacy#define TRC_SCHED_SHUTDOWN (TRC_SCHED_VERBOSE + 7) 78183375Skmacy#define TRC_SCHED_CTL (TRC_SCHED_VERBOSE + 8) 79183375Skmacy#define TRC_SCHED_ADJDOM (TRC_SCHED_VERBOSE + 9) 80183375Skmacy#define TRC_SCHED_SWITCH (TRC_SCHED_VERBOSE + 10) 81183375Skmacy#define TRC_SCHED_S_TIMER_FN (TRC_SCHED_VERBOSE + 11) 82183375Skmacy#define TRC_SCHED_T_TIMER_FN (TRC_SCHED_VERBOSE + 12) 83183375Skmacy#define TRC_SCHED_DOM_TIMER_FN (TRC_SCHED_VERBOSE + 13) 84183375Skmacy#define TRC_SCHED_SWITCH_INFPREV (TRC_SCHED_VERBOSE + 14) 85183375Skmacy#define TRC_SCHED_SWITCH_INFNEXT (TRC_SCHED_VERBOSE + 15) 86251767Sgibbs#define TRC_SCHED_SHUTDOWN_CODE (TRC_SCHED_VERBOSE + 16) 87181624Skmacy 88181624Skmacy#define TRC_MEM_PAGE_GRANT_MAP (TRC_MEM + 1) 89181624Skmacy#define TRC_MEM_PAGE_GRANT_UNMAP (TRC_MEM + 2) 90181624Skmacy#define TRC_MEM_PAGE_GRANT_TRANSFER (TRC_MEM + 3) 91251767Sgibbs#define TRC_MEM_SET_P2M_ENTRY (TRC_MEM + 4) 92251767Sgibbs#define TRC_MEM_DECREASE_RESERVATION (TRC_MEM + 5) 93251767Sgibbs#define TRC_MEM_POD_POPULATE (TRC_MEM + 16) 94251767Sgibbs#define TRC_MEM_POD_ZERO_RECLAIM (TRC_MEM + 17) 95251767Sgibbs#define TRC_MEM_POD_SUPERPAGE_SPLINTER (TRC_MEM + 18) 96181624Skmacy 97251767Sgibbs 98183375Skmacy#define TRC_PV_HYPERCALL (TRC_PV + 1) 99183375Skmacy#define TRC_PV_TRAP (TRC_PV + 3) 100183375Skmacy#define TRC_PV_PAGE_FAULT (TRC_PV + 4) 101183375Skmacy#define TRC_PV_FORCED_INVALID_OP (TRC_PV + 5) 102183375Skmacy#define TRC_PV_EMULATE_PRIVOP (TRC_PV + 6) 103183375Skmacy#define TRC_PV_EMULATE_4GB (TRC_PV + 7) 104183375Skmacy#define TRC_PV_MATH_STATE_RESTORE (TRC_PV + 8) 105183375Skmacy#define TRC_PV_PAGING_FIXUP (TRC_PV + 9) 106183375Skmacy#define TRC_PV_GDT_LDT_MAPPING_FAULT (TRC_PV + 10) 107183375Skmacy#define TRC_PV_PTWR_EMULATION (TRC_PV + 11) 108183375Skmacy#define TRC_PV_PTWR_EMULATION_PAE (TRC_PV + 12) 109183375Skmacy /* Indicates that addresses in trace record are 64 bits */ 110183375Skmacy#define TRC_64_FLAG (0x100) 111183375Skmacy 112183375Skmacy#define TRC_SHADOW_NOT_SHADOW (TRC_SHADOW + 1) 113183375Skmacy#define TRC_SHADOW_FAST_PROPAGATE (TRC_SHADOW + 2) 114183375Skmacy#define TRC_SHADOW_FAST_MMIO (TRC_SHADOW + 3) 115183375Skmacy#define TRC_SHADOW_FALSE_FAST_PATH (TRC_SHADOW + 4) 116183375Skmacy#define TRC_SHADOW_MMIO (TRC_SHADOW + 5) 117183375Skmacy#define TRC_SHADOW_FIXUP (TRC_SHADOW + 6) 118183375Skmacy#define TRC_SHADOW_DOMF_DYING (TRC_SHADOW + 7) 119183375Skmacy#define TRC_SHADOW_EMULATE (TRC_SHADOW + 8) 120183375Skmacy#define TRC_SHADOW_EMULATE_UNSHADOW_USER (TRC_SHADOW + 9) 121183375Skmacy#define TRC_SHADOW_EMULATE_UNSHADOW_EVTINJ (TRC_SHADOW + 10) 122183375Skmacy#define TRC_SHADOW_EMULATE_UNSHADOW_UNHANDLED (TRC_SHADOW + 11) 123183375Skmacy#define TRC_SHADOW_WRMAP_BF (TRC_SHADOW + 12) 124183375Skmacy#define TRC_SHADOW_PREALLOC_UNPIN (TRC_SHADOW + 13) 125183375Skmacy#define TRC_SHADOW_RESYNC_FULL (TRC_SHADOW + 14) 126183375Skmacy#define TRC_SHADOW_RESYNC_ONLY (TRC_SHADOW + 15) 127183375Skmacy 128181624Skmacy/* trace events per subclass */ 129251767Sgibbs#define TRC_HVM_NESTEDFLAG (0x400) 130181624Skmacy#define TRC_HVM_VMENTRY (TRC_HVM_ENTRYEXIT + 0x01) 131181624Skmacy#define TRC_HVM_VMEXIT (TRC_HVM_ENTRYEXIT + 0x02) 132183375Skmacy#define TRC_HVM_VMEXIT64 (TRC_HVM_ENTRYEXIT + TRC_64_FLAG + 0x02) 133181624Skmacy#define TRC_HVM_PF_XEN (TRC_HVM_HANDLER + 0x01) 134183375Skmacy#define TRC_HVM_PF_XEN64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x01) 135181624Skmacy#define TRC_HVM_PF_INJECT (TRC_HVM_HANDLER + 0x02) 136183375Skmacy#define TRC_HVM_PF_INJECT64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x02) 137181624Skmacy#define TRC_HVM_INJ_EXC (TRC_HVM_HANDLER + 0x03) 138181624Skmacy#define TRC_HVM_INJ_VIRQ (TRC_HVM_HANDLER + 0x04) 139181624Skmacy#define TRC_HVM_REINJ_VIRQ (TRC_HVM_HANDLER + 0x05) 140181624Skmacy#define TRC_HVM_IO_READ (TRC_HVM_HANDLER + 0x06) 141181624Skmacy#define TRC_HVM_IO_WRITE (TRC_HVM_HANDLER + 0x07) 142181624Skmacy#define TRC_HVM_CR_READ (TRC_HVM_HANDLER + 0x08) 143183375Skmacy#define TRC_HVM_CR_READ64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x08) 144181624Skmacy#define TRC_HVM_CR_WRITE (TRC_HVM_HANDLER + 0x09) 145183375Skmacy#define TRC_HVM_CR_WRITE64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x09) 146181624Skmacy#define TRC_HVM_DR_READ (TRC_HVM_HANDLER + 0x0A) 147181624Skmacy#define TRC_HVM_DR_WRITE (TRC_HVM_HANDLER + 0x0B) 148181624Skmacy#define TRC_HVM_MSR_READ (TRC_HVM_HANDLER + 0x0C) 149181624Skmacy#define TRC_HVM_MSR_WRITE (TRC_HVM_HANDLER + 0x0D) 150181624Skmacy#define TRC_HVM_CPUID (TRC_HVM_HANDLER + 0x0E) 151181624Skmacy#define TRC_HVM_INTR (TRC_HVM_HANDLER + 0x0F) 152181624Skmacy#define TRC_HVM_NMI (TRC_HVM_HANDLER + 0x10) 153181624Skmacy#define TRC_HVM_SMI (TRC_HVM_HANDLER + 0x11) 154181624Skmacy#define TRC_HVM_VMMCALL (TRC_HVM_HANDLER + 0x12) 155181624Skmacy#define TRC_HVM_HLT (TRC_HVM_HANDLER + 0x13) 156181624Skmacy#define TRC_HVM_INVLPG (TRC_HVM_HANDLER + 0x14) 157183375Skmacy#define TRC_HVM_INVLPG64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x14) 158181624Skmacy#define TRC_HVM_MCE (TRC_HVM_HANDLER + 0x15) 159251767Sgibbs#define TRC_HVM_IOPORT_READ (TRC_HVM_HANDLER + 0x16) 160251767Sgibbs#define TRC_HVM_IOMEM_READ (TRC_HVM_HANDLER + 0x17) 161183375Skmacy#define TRC_HVM_CLTS (TRC_HVM_HANDLER + 0x18) 162183375Skmacy#define TRC_HVM_LMSW (TRC_HVM_HANDLER + 0x19) 163183375Skmacy#define TRC_HVM_LMSW64 (TRC_HVM_HANDLER + TRC_64_FLAG + 0x19) 164251767Sgibbs#define TRC_HVM_RDTSC (TRC_HVM_HANDLER + 0x1a) 165251767Sgibbs#define TRC_HVM_INTR_WINDOW (TRC_HVM_HANDLER + 0x20) 166251767Sgibbs#define TRC_HVM_NPF (TRC_HVM_HANDLER + 0x21) 167251767Sgibbs#define TRC_HVM_REALMODE_EMULATE (TRC_HVM_HANDLER + 0x22) 168251767Sgibbs#define TRC_HVM_TRAP (TRC_HVM_HANDLER + 0x23) 169251767Sgibbs#define TRC_HVM_TRAP_DEBUG (TRC_HVM_HANDLER + 0x24) 170251767Sgibbs#define TRC_HVM_VLAPIC (TRC_HVM_HANDLER + 0x25) 171181624Skmacy 172251767Sgibbs#define TRC_HVM_IOPORT_WRITE (TRC_HVM_HANDLER + 0x216) 173251767Sgibbs#define TRC_HVM_IOMEM_WRITE (TRC_HVM_HANDLER + 0x217) 174251767Sgibbs 175251767Sgibbs/* trace events for per class */ 176251767Sgibbs#define TRC_PM_FREQ_CHANGE (TRC_HW_PM + 0x01) 177251767Sgibbs#define TRC_PM_IDLE_ENTRY (TRC_HW_PM + 0x02) 178251767Sgibbs#define TRC_PM_IDLE_EXIT (TRC_HW_PM + 0x03) 179251767Sgibbs 180251767Sgibbs/* Trace events for IRQs */ 181251767Sgibbs#define TRC_HW_IRQ_MOVE_CLEANUP_DELAY (TRC_HW_IRQ + 0x1) 182251767Sgibbs#define TRC_HW_IRQ_MOVE_CLEANUP (TRC_HW_IRQ + 0x2) 183251767Sgibbs#define TRC_HW_IRQ_BIND_VECTOR (TRC_HW_IRQ + 0x3) 184251767Sgibbs#define TRC_HW_IRQ_CLEAR_VECTOR (TRC_HW_IRQ + 0x4) 185251767Sgibbs#define TRC_HW_IRQ_MOVE_FINISH (TRC_HW_IRQ + 0x5) 186251767Sgibbs#define TRC_HW_IRQ_ASSIGN_VECTOR (TRC_HW_IRQ + 0x6) 187251767Sgibbs#define TRC_HW_IRQ_UNMAPPED_VECTOR (TRC_HW_IRQ + 0x7) 188251767Sgibbs#define TRC_HW_IRQ_HANDLED (TRC_HW_IRQ + 0x8) 189251767Sgibbs 190251767Sgibbs 191181624Skmacy/* This structure represents a single trace buffer record. */ 192181624Skmacystruct t_rec { 193183375Skmacy uint32_t event:28; 194183375Skmacy uint32_t extra_u32:3; /* # entries in trailing extra_u32[] array */ 195183375Skmacy uint32_t cycles_included:1; /* u.cycles or u.no_cycles? */ 196183375Skmacy union { 197183375Skmacy struct { 198183375Skmacy uint32_t cycles_lo, cycles_hi; /* cycle counter timestamp */ 199183375Skmacy uint32_t extra_u32[7]; /* event data items */ 200183375Skmacy } cycles; 201183375Skmacy struct { 202183375Skmacy uint32_t extra_u32[7]; /* event data items */ 203183375Skmacy } nocycles; 204183375Skmacy } u; 205181624Skmacy}; 206181624Skmacy 207181624Skmacy/* 208181624Skmacy * This structure contains the metadata for a single trace buffer. The head 209181624Skmacy * field, indexes into an array of struct t_rec's. 210181624Skmacy */ 211181624Skmacystruct t_buf { 212183375Skmacy /* Assume the data buffer size is X. X is generally not a power of 2. 213183375Skmacy * CONS and PROD are incremented modulo (2*X): 214183375Skmacy * 0 <= cons < 2*X 215183375Skmacy * 0 <= prod < 2*X 216183375Skmacy * This is done because addition modulo X breaks at 2^32 when X is not a 217183375Skmacy * power of 2: 218183375Skmacy * (((2^32 - 1) % X) + 1) % X != (2^32) % X 219183375Skmacy */ 220183375Skmacy uint32_t cons; /* Offset of next item to be consumed by control tools. */ 221183375Skmacy uint32_t prod; /* Offset of next item to be produced by Xen. */ 222183375Skmacy /* Records follow immediately after the meta-data header. */ 223181624Skmacy}; 224181624Skmacy 225251767Sgibbs/* Structure used to pass MFNs to the trace buffers back to trace consumers. 226251767Sgibbs * Offset is an offset into the mapped structure where the mfn list will be held. 227251767Sgibbs * MFNs will be at ((unsigned long *)(t_info))+(t_info->cpu_offset[cpu]). 228251767Sgibbs */ 229251767Sgibbsstruct t_info { 230251767Sgibbs uint16_t tbuf_size; /* Size in pages of each trace buffer */ 231251767Sgibbs uint16_t mfn_offset[]; /* Offset within t_info structure of the page list per cpu */ 232251767Sgibbs /* MFN lists immediately after the header */ 233251767Sgibbs}; 234251767Sgibbs 235181624Skmacy#endif /* __XEN_PUBLIC_TRACE_H__ */ 236181624Skmacy 237181624Skmacy/* 238181624Skmacy * Local variables: 239181624Skmacy * mode: C 240181624Skmacy * c-set-style: "BSD" 241181624Skmacy * c-basic-offset: 4 242181624Skmacy * tab-width: 4 243181624Skmacy * indent-tabs-mode: nil 244181624Skmacy * End: 245181624Skmacy */ 246