smist.c revision 182401
1145287Snjl/*- 2145287Snjl * Copyright (c) 2005 Bruno Ducrot 3145287Snjl * 4145287Snjl * Redistribution and use in source and binary forms, with or without 5145287Snjl * modification, are permitted provided that the following conditions 6145287Snjl * are met: 7145287Snjl * 1. Redistributions of source code must retain the above copyright 8145287Snjl * notice, this list of conditions and the following disclaimer. 9145287Snjl * 2. Redistributions in binary form must reproduce the above copyright 10145287Snjl * notice, this list of conditions and the following disclaimer in the 11145287Snjl * documentation and/or other materials provided with the distribution. 12145287Snjl * 13145287Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14145287Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15145287Snjl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16145287Snjl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17145287Snjl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 18145287Snjl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 19145287Snjl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 20145287Snjl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 21145287Snjl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 22145287Snjl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23145287Snjl */ 24145287Snjl 25145287Snjl/* 26145287Snjl * This driver is based upon information found by examining speedstep-0.5 27145287Snjl * from Marc Lehman, which includes all the reverse engineering effort of 28145287Snjl * Malik Martin (function 1 and 2 of the GSI). 29145287Snjl * 30145287Snjl * The correct way for the OS to take ownership from the BIOS was found by 31145287Snjl * Hiroshi Miura (function 0 of the GSI). 32145287Snjl * 33145287Snjl * Finally, the int 15h call interface was (partially) documented by Intel. 34145287Snjl * 35145287Snjl * Many thanks to Jon Noack for testing and debugging this driver. 36145287Snjl */ 37145287Snjl 38145287Snjl#include <sys/cdefs.h> 39145287Snjl__FBSDID("$FreeBSD: head/sys/i386/cpufreq/smist.c 182401 2008-08-28 19:55:18Z jhb $"); 40145287Snjl 41145287Snjl#include <sys/param.h> 42145287Snjl#include <sys/bus.h> 43145287Snjl#include <sys/cpu.h> 44145287Snjl#include <sys/kernel.h> 45145287Snjl#include <sys/module.h> 46145287Snjl#include <sys/systm.h> 47145287Snjl 48170874Snjl#include <machine/bus.h> 49145287Snjl#include <machine/md_var.h> 50145287Snjl#include <machine/vm86.h> 51145287Snjl 52145287Snjl#include <dev/pci/pcivar.h> 53145287Snjl#include <dev/pci/pcireg.h> 54145287Snjl 55145287Snjl#include <vm/vm.h> 56145287Snjl#include <vm/pmap.h> 57145287Snjl 58145287Snjl#include "cpufreq_if.h" 59145287Snjl 60145287Snjl#if 0 61145287Snjl#define DPRINT(dev, x...) device_printf(dev, x) 62145287Snjl#else 63145287Snjl#define DPRINT(dev, x...) 64145287Snjl#endif 65145287Snjl 66145287Snjlstruct smist_softc { 67145287Snjl device_t dev; 68145287Snjl int smi_cmd; 69145287Snjl int smi_data; 70145287Snjl int command; 71145287Snjl int flags; 72145287Snjl struct cf_setting sets[2]; /* Only two settings. */ 73145287Snjl}; 74145287Snjl 75170874Snjlstatic char smist_magic[] = "Copyright (c) 1999 Intel Corporation"; 76170874Snjl 77145287Snjlstatic void smist_identify(driver_t *driver, device_t parent); 78145287Snjlstatic int smist_probe(device_t dev); 79145287Snjlstatic int smist_attach(device_t dev); 80145287Snjlstatic int smist_detach(device_t dev); 81145287Snjlstatic int smist_settings(device_t dev, struct cf_setting *sets, 82145287Snjl int *count); 83145287Snjlstatic int smist_set(device_t dev, const struct cf_setting *set); 84145287Snjlstatic int smist_get(device_t dev, struct cf_setting *set); 85145287Snjlstatic int smist_type(device_t dev, int *type); 86145287Snjl 87145287Snjlstatic device_method_t smist_methods[] = { 88145287Snjl /* Device interface */ 89145287Snjl DEVMETHOD(device_identify, smist_identify), 90145287Snjl DEVMETHOD(device_probe, smist_probe), 91145287Snjl DEVMETHOD(device_attach, smist_attach), 92145287Snjl DEVMETHOD(device_detach, smist_detach), 93145287Snjl 94145287Snjl /* cpufreq interface */ 95145287Snjl DEVMETHOD(cpufreq_drv_set, smist_set), 96145287Snjl DEVMETHOD(cpufreq_drv_get, smist_get), 97145287Snjl DEVMETHOD(cpufreq_drv_type, smist_type), 98145287Snjl DEVMETHOD(cpufreq_drv_settings, smist_settings), 99145287Snjl 100145287Snjl {0, 0} 101145287Snjl}; 102145287Snjl 103145287Snjlstatic driver_t smist_driver = { 104145287Snjl "smist", smist_methods, sizeof(struct smist_softc) 105145287Snjl}; 106145287Snjlstatic devclass_t smist_devclass; 107145287SnjlDRIVER_MODULE(smist, cpu, smist_driver, smist_devclass, 0, 0); 108145287Snjl 109145287Snjlstruct piix4_pci_device { 110145287Snjl uint16_t vendor; 111145287Snjl uint16_t device; 112145287Snjl char *desc; 113145287Snjl}; 114145287Snjl 115145287Snjlstatic struct piix4_pci_device piix4_pci_devices[] = { 116145287Snjl {0x8086, 0x7113, "Intel PIIX4 ISA bridge"}, 117145287Snjl {0x8086, 0x719b, "Intel PIIX4 ISA bridge (embedded in MX440 chipset)"}, 118145287Snjl 119145287Snjl {0, 0, NULL}, 120145287Snjl}; 121145287Snjl 122145287Snjl#define SET_OWNERSHIP 0 123145287Snjl#define GET_STATE 1 124145287Snjl#define SET_STATE 2 125145287Snjl 126145287Snjlstatic int 127145287Snjlint15_gsic_call(int *sig, int *smi_cmd, int *command, int *smi_data, int *flags) 128145287Snjl{ 129145287Snjl struct vm86frame vmf; 130145287Snjl 131145287Snjl bzero(&vmf, sizeof(vmf)); 132145287Snjl vmf.vmf_eax = 0x0000E980; /* IST support */ 133145287Snjl vmf.vmf_edx = 0x47534943; /* 'GSIC' in ASCII */ 134145287Snjl vm86_intcall(0x15, &vmf); 135145287Snjl 136145287Snjl if (vmf.vmf_eax == 0x47534943) { 137145287Snjl *sig = vmf.vmf_eax; 138145287Snjl *smi_cmd = vmf.vmf_ebx & 0xff; 139145287Snjl *command = (vmf.vmf_ebx >> 16) & 0xff; 140145287Snjl *smi_data = vmf.vmf_ecx; 141145287Snjl *flags = vmf.vmf_edx; 142145287Snjl } else { 143145287Snjl *sig = -1; 144145287Snjl *smi_cmd = -1; 145145287Snjl *command = -1; 146145287Snjl *smi_data = -1; 147145287Snjl *flags = -1; 148145287Snjl } 149145287Snjl 150145287Snjl return (0); 151145287Snjl} 152145287Snjl 153170874Snjl/* Temporary structure to hold mapped page and status. */ 154170874Snjlstruct set_ownership_data { 155170874Snjl int smi_cmd; 156170874Snjl int command; 157170874Snjl int result; 158170874Snjl void *buf; 159170874Snjl}; 160170874Snjl 161170874Snjl/* Perform actual SMI call to enable SpeedStep. */ 162170874Snjlstatic void 163170874Snjlset_ownership_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 164145287Snjl{ 165170874Snjl struct set_ownership_data *data; 166145287Snjl 167170874Snjl data = arg; 168170874Snjl if (error) { 169170874Snjl data->result = error; 170170874Snjl return; 171170874Snjl } 172145287Snjl 173170874Snjl /* Copy in the magic string and send it by writing to the SMI port. */ 174170874Snjl strlcpy(data->buf, smist_magic, PAGE_SIZE); 175145287Snjl __asm __volatile( 176145287Snjl "movl $-1, %%edi\n\t" 177145287Snjl "out %%al, (%%dx)\n" 178170874Snjl : "=D" (data->result) 179170874Snjl : "a" (data->command), 180145287Snjl "b" (0), 181145287Snjl "c" (0), 182170874Snjl "d" (data->smi_cmd), 183170874Snjl "S" ((uint32_t)segs[0].ds_addr) 184145287Snjl ); 185170874Snjl} 186145287Snjl 187170874Snjlstatic int 188170874Snjlset_ownership(device_t dev) 189170874Snjl{ 190170874Snjl struct smist_softc *sc; 191170874Snjl struct set_ownership_data cb_data; 192170874Snjl bus_dma_tag_t tag; 193170874Snjl bus_dmamap_t map; 194145287Snjl 195170874Snjl /* 196170874Snjl * Specify the region to store the magic string. Since its address is 197170874Snjl * passed to the BIOS in a 32-bit register, we have to make sure it is 198170874Snjl * located in a physical page below 4 GB (i.e., for PAE.) 199170874Snjl */ 200170874Snjl sc = device_get_softc(dev); 201170874Snjl if (bus_dma_tag_create(/*parent*/ NULL, 202170874Snjl /*alignment*/ PAGE_SIZE, /*no boundary*/ 0, 203170874Snjl /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, /*highaddr*/ BUS_SPACE_MAXADDR, 204170874Snjl NULL, NULL, /*maxsize*/ PAGE_SIZE, /*segments*/ 1, 205170874Snjl /*maxsegsize*/ PAGE_SIZE, 0, busdma_lock_mutex, &Giant, 206170874Snjl &tag) != 0) { 207170874Snjl device_printf(dev, "can't create mem tag\n"); 208170874Snjl return (ENXIO); 209170874Snjl } 210170874Snjl if (bus_dmamem_alloc(tag, &cb_data.buf, BUS_DMA_NOWAIT, &map) != 0) { 211170874Snjl bus_dma_tag_destroy(tag); 212170874Snjl device_printf(dev, "can't alloc mapped mem\n"); 213170874Snjl return (ENXIO); 214170874Snjl } 215170874Snjl 216170874Snjl /* Load the physical page map and take ownership in the callback. */ 217170874Snjl cb_data.smi_cmd = sc->smi_cmd; 218170874Snjl cb_data.command = sc->command; 219170874Snjl if (bus_dmamap_load(tag, map, cb_data.buf, PAGE_SIZE, set_ownership_cb, 220170874Snjl &cb_data, BUS_DMA_NOWAIT) != 0) { 221170874Snjl bus_dmamem_free(tag, cb_data.buf, map); 222170874Snjl bus_dma_tag_destroy(tag); 223170874Snjl device_printf(dev, "can't load mem\n"); 224170874Snjl return (ENXIO); 225170874Snjl }; 226170874Snjl DPRINT(dev, "taking ownership over BIOS return %d\n", cb_data.result); 227170874Snjl bus_dmamap_unload(tag, map); 228170874Snjl bus_dmamem_free(tag, cb_data.buf, map); 229170874Snjl bus_dma_tag_destroy(tag); 230170874Snjl return (cb_data.result ? ENXIO : 0); 231145287Snjl} 232145287Snjl 233145287Snjlstatic int 234145287Snjlgetset_state(struct smist_softc *sc, int *state, int function) 235145287Snjl{ 236145287Snjl int new_state; 237145287Snjl int result; 238145287Snjl int eax; 239145287Snjl 240145287Snjl if (!sc) 241145287Snjl return (ENXIO); 242145287Snjl 243145287Snjl if (function != GET_STATE && function != SET_STATE) 244145287Snjl return (EINVAL); 245145287Snjl 246145287Snjl DPRINT(sc->dev, "calling GSI\n"); 247145287Snjl 248145287Snjl __asm __volatile( 249145287Snjl "movl $-1, %%edi\n\t" 250145287Snjl "out %%al, (%%dx)\n" 251145287Snjl : "=a" (eax), 252145287Snjl "=b" (new_state), 253145287Snjl "=D" (result) 254145287Snjl : "a" (sc->command), 255145287Snjl "b" (function), 256145287Snjl "c" (*state), 257145287Snjl "d" (sc->smi_cmd) 258145287Snjl ); 259145287Snjl 260145287Snjl DPRINT(sc->dev, "GSI returned: eax %.8x ebx %.8x edi %.8x\n", 261145287Snjl eax, new_state, result); 262145287Snjl 263145287Snjl *state = new_state & 1; 264145287Snjl 265145287Snjl switch (function) { 266145287Snjl case GET_STATE: 267145287Snjl if (eax) 268145287Snjl return (ENXIO); 269145287Snjl break; 270145287Snjl case SET_STATE: 271145287Snjl if (result) 272145287Snjl return (ENXIO); 273145287Snjl break; 274145287Snjl } 275145287Snjl return (0); 276145287Snjl} 277145287Snjl 278145287Snjlstatic void 279145287Snjlsmist_identify(driver_t *driver, device_t parent) 280145287Snjl{ 281145287Snjl struct piix4_pci_device *id; 282145287Snjl device_t piix4 = NULL; 283145287Snjl 284145287Snjl if (resource_disabled("ichst", 0)) 285145287Snjl return; 286145287Snjl 287145287Snjl /* Check for a supported processor */ 288145287Snjl if (strcmp(cpu_vendor, "GenuineIntel") != 0) 289145287Snjl return; 290145287Snjl switch (cpu_id & 0xff0) { 291145287Snjl case 0x680: /* Pentium III [coppermine] */ 292145287Snjl case 0x6a0: /* Pentium III [Tualatin] */ 293145287Snjl break; 294145287Snjl default: 295145287Snjl return; 296145287Snjl } 297145287Snjl 298145287Snjl /* Check for a supported PCI-ISA bridge */ 299145287Snjl for (id = piix4_pci_devices; id->desc != NULL; ++id) { 300145287Snjl if ((piix4 = pci_find_device(id->vendor, id->device)) != NULL) 301145287Snjl break; 302145287Snjl } 303145287Snjl if (!piix4) 304145287Snjl return; 305145287Snjl 306145287Snjl if (bootverbose) 307145287Snjl printf("smist: found supported isa bridge %s\n", id->desc); 308145287Snjl 309145287Snjl if (device_find_child(parent, "smist", -1) != NULL) 310145287Snjl return; 311181691Sjhb if (BUS_ADD_CHILD(parent, 30, "smist", -1) == NULL) 312145287Snjl device_printf(parent, "smist: add child failed\n"); 313145287Snjl} 314145287Snjl 315145287Snjlstatic int 316145287Snjlsmist_probe(device_t dev) 317145287Snjl{ 318145287Snjl struct smist_softc *sc; 319145287Snjl device_t ichss_dev, perf_dev; 320145287Snjl int sig, smi_cmd, command, smi_data, flags; 321145287Snjl int type; 322145287Snjl int rv; 323145287Snjl 324145287Snjl if (resource_disabled("smist", 0)) 325145287Snjl return (ENXIO); 326145287Snjl 327145287Snjl sc = device_get_softc(dev); 328145287Snjl 329145287Snjl /* 330145287Snjl * If the ACPI perf or ICH SpeedStep drivers have attached and not 331145287Snjl * just offering info, let them manage things. 332145287Snjl */ 333145287Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 334145287Snjl if (perf_dev && device_is_attached(perf_dev)) { 335145287Snjl rv = CPUFREQ_DRV_TYPE(perf_dev, &type); 336145287Snjl if (rv == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 337145287Snjl return (ENXIO); 338145287Snjl } 339145287Snjl ichss_dev = device_find_child(device_get_parent(dev), "ichss", -1); 340145287Snjl if (ichss_dev && device_is_attached(ichss_dev)) 341145287Snjl return (ENXIO); 342145287Snjl 343145287Snjl int15_gsic_call(&sig, &smi_cmd, &command, &smi_data, &flags); 344145287Snjl if (bootverbose) 345145287Snjl device_printf(dev, "sig %.8x smi_cmd %.4x command %.2x " 346145287Snjl "smi_data %.4x flags %.8x\n", 347145287Snjl sig, smi_cmd, command, smi_data, flags); 348145287Snjl 349145287Snjl if (sig != -1) { 350145287Snjl sc->smi_cmd = smi_cmd; 351145287Snjl sc->smi_data = smi_data; 352145287Snjl 353145287Snjl /* 354145287Snjl * Sometimes int 15h 'GSIC' returns 0x80 for command, when 355145287Snjl * it is actually 0x82. The Windows driver will overwrite 356145287Snjl * this value given by the registry. 357145287Snjl */ 358145287Snjl if (command == 0x80) { 359145287Snjl device_printf(dev, 360145287Snjl "GSIC returned cmd 0x80, should be 0x82\n"); 361145287Snjl command = 0x82; 362145287Snjl } 363145287Snjl sc->command = (sig & 0xffffff00) | (command & 0xff); 364145287Snjl sc->flags = flags; 365145287Snjl } else { 366145287Snjl /* Give some default values */ 367145287Snjl sc->smi_cmd = 0xb2; 368145287Snjl sc->smi_data = 0xb3; 369145287Snjl sc->command = 0x47534982; 370145287Snjl sc->flags = 0; 371145287Snjl } 372145287Snjl 373145287Snjl device_set_desc(dev, "SpeedStep SMI"); 374145287Snjl 375145287Snjl return (-1500); 376145287Snjl} 377145287Snjl 378145287Snjlstatic int 379145287Snjlsmist_attach(device_t dev) 380145287Snjl{ 381145287Snjl struct smist_softc *sc; 382145287Snjl 383145287Snjl sc = device_get_softc(dev); 384145287Snjl sc->dev = dev; 385145287Snjl 386145287Snjl /* If we can't take ownership over BIOS, then bail out */ 387145287Snjl if (set_ownership(dev) != 0) 388145287Snjl return (ENXIO); 389145287Snjl 390145287Snjl /* Setup some defaults for our exported settings. */ 391145287Snjl sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 392145287Snjl sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 393145287Snjl sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 394145287Snjl sc->sets[0].lat = 1000; 395145287Snjl sc->sets[0].dev = dev; 396145287Snjl sc->sets[1] = sc->sets[0]; 397145287Snjl 398145287Snjl cpufreq_register(dev); 399145287Snjl 400145287Snjl return (0); 401145287Snjl} 402145287Snjl 403145287Snjlstatic int 404145287Snjlsmist_detach(device_t dev) 405145287Snjl{ 406182401Sjhb 407182401Sjhb return (cpufreq_unregister(dev)); 408145287Snjl} 409145287Snjl 410145287Snjlstatic int 411145287Snjlsmist_settings(device_t dev, struct cf_setting *sets, int *count) 412145287Snjl{ 413145287Snjl struct smist_softc *sc; 414145287Snjl struct cf_setting set; 415145287Snjl int first, i; 416145287Snjl 417145287Snjl if (sets == NULL || count == NULL) 418145287Snjl return (EINVAL); 419145287Snjl if (*count < 2) { 420145287Snjl *count = 2; 421145287Snjl return (E2BIG); 422145287Snjl } 423145287Snjl sc = device_get_softc(dev); 424145287Snjl 425145287Snjl /* 426145287Snjl * Estimate frequencies for both levels, temporarily switching to 427145287Snjl * the other one if we haven't calibrated it yet. 428145287Snjl */ 429145287Snjl for (i = 0; i < 2; i++) { 430145287Snjl if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 431145287Snjl first = (i == 0) ? 1 : 0; 432145287Snjl smist_set(dev, &sc->sets[i]); 433145287Snjl smist_get(dev, &set); 434145287Snjl smist_set(dev, &sc->sets[first]); 435145287Snjl } 436145287Snjl } 437145287Snjl 438145287Snjl bcopy(sc->sets, sets, sizeof(sc->sets)); 439145287Snjl *count = 2; 440145287Snjl 441145287Snjl return (0); 442145287Snjl} 443145287Snjl 444145287Snjlstatic int 445145287Snjlsmist_set(device_t dev, const struct cf_setting *set) 446145287Snjl{ 447145287Snjl struct smist_softc *sc; 448145287Snjl int rv, state, req_state, try; 449145287Snjl 450145287Snjl /* Look up appropriate bit value based on frequency. */ 451145287Snjl sc = device_get_softc(dev); 452145287Snjl if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 453145287Snjl req_state = 0; 454145287Snjl else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 455145287Snjl req_state = 1; 456145287Snjl else 457145287Snjl return (EINVAL); 458145287Snjl 459145287Snjl DPRINT(dev, "requested setting %d\n", req_state); 460145287Snjl 461145287Snjl rv = getset_state(sc, &state, GET_STATE); 462145287Snjl if (state == req_state) 463145287Snjl return (0); 464145287Snjl 465145287Snjl try = 3; 466145287Snjl do { 467145287Snjl rv = getset_state(sc, &req_state, SET_STATE); 468145287Snjl 469145287Snjl /* Sleep for 200 microseconds. This value is just a guess. */ 470145287Snjl if (rv) 471145287Snjl DELAY(200); 472145287Snjl } while (rv && --try); 473145287Snjl DPRINT(dev, "set_state return %d, tried %d times\n", 474145287Snjl rv, 4 - try); 475145287Snjl 476145287Snjl return (rv); 477145287Snjl} 478145287Snjl 479145287Snjlstatic int 480145287Snjlsmist_get(device_t dev, struct cf_setting *set) 481145287Snjl{ 482145287Snjl struct smist_softc *sc; 483145287Snjl uint64_t rate; 484145287Snjl int state; 485145287Snjl int rv; 486145287Snjl 487145287Snjl sc = device_get_softc(dev); 488145287Snjl rv = getset_state(sc, &state, GET_STATE); 489145287Snjl if (rv != 0) 490145287Snjl return (rv); 491145287Snjl 492145287Snjl /* If we haven't changed settings yet, estimate the current value. */ 493145287Snjl if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 494145287Snjl cpu_est_clockrate(0, &rate); 495145287Snjl sc->sets[state].freq = rate / 1000000; 496145287Snjl DPRINT(dev, "get calibrated new rate of %d\n", 497145287Snjl sc->sets[state].freq); 498145287Snjl } 499145287Snjl *set = sc->sets[state]; 500145287Snjl 501145287Snjl return (0); 502145287Snjl} 503145287Snjl 504145287Snjlstatic int 505145287Snjlsmist_type(device_t dev, int *type) 506145287Snjl{ 507145287Snjl 508145287Snjl if (type == NULL) 509145287Snjl return (EINVAL); 510145287Snjl 511145287Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 512145287Snjl return (0); 513145287Snjl} 514