p4tcc.c revision 142625
1/*- 2 * Copyright (c) 2005 Nate Lawson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Throttle clock frequency by using the thermal control circuit. This 29 * operates independently of SpeedStep and ACPI throttling and is supported 30 * on Pentium 4 and later models (feature TM). 31 * 32 * Reference: Intel Developer's manual v.3 #245472-012 33 * 34 * The original version of this driver was written by Ted Unangst for 35 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36 * for use with the cpufreq framework. 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: head/sys/i386/cpufreq/p4tcc.c 142625 2005-02-27 02:43:02Z njl $"); 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/cpu.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48 49#include <machine/md_var.h> 50#include <machine/specialreg.h> 51 52#include "cpufreq_if.h" 53 54struct p4tcc_softc { 55 device_t dev; 56 int set_count; 57 int lowest_val; 58 int auto_mode; 59}; 60 61#define TCC_NUM_SETTINGS 8 62 63#define TCC_ENABLE_ONDEMAND (1<<4) 64#define TCC_REG_OFFSET 1 65#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 66 67static void p4tcc_identify(driver_t *driver, device_t parent); 68static int p4tcc_probe(device_t dev); 69static int p4tcc_attach(device_t dev); 70static int p4tcc_settings(device_t dev, struct cf_setting *sets, 71 int *count); 72static int p4tcc_set(device_t dev, const struct cf_setting *set); 73static int p4tcc_get(device_t dev, struct cf_setting *set); 74static int p4tcc_type(device_t dev, int *type); 75 76static device_method_t p4tcc_methods[] = { 77 /* Device interface */ 78 DEVMETHOD(device_identify, p4tcc_identify), 79 DEVMETHOD(device_probe, p4tcc_probe), 80 DEVMETHOD(device_attach, p4tcc_attach), 81 82 /* cpufreq interface */ 83 DEVMETHOD(cpufreq_drv_set, p4tcc_set), 84 DEVMETHOD(cpufreq_drv_get, p4tcc_get), 85 DEVMETHOD(cpufreq_drv_type, p4tcc_type), 86 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 87 {0, 0} 88}; 89 90static driver_t p4tcc_driver = { 91 "p4tcc", 92 p4tcc_methods, 93 sizeof(struct p4tcc_softc), 94}; 95 96static devclass_t p4tcc_devclass; 97DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 98 99static void 100p4tcc_identify(driver_t *driver, device_t parent) 101{ 102 103 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 104 return; 105 106 /* Make sure we're not being doubly invoked. */ 107 if (device_find_child(parent, "p4tcc", -1) != NULL) 108 return; 109 110 /* 111 * We attach a p4tcc child for every CPU since settings need to 112 * be performed on every CPU in the SMP case. See section 13.15.3 113 * of the IA32 Intel Architecture Software Developer's Manual, 114 * Volume 3, for more info. 115 */ 116 if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL) 117 device_printf(parent, "add p4tcc child failed\n"); 118} 119 120static int 121p4tcc_probe(device_t dev) 122{ 123 124 if (resource_disabled("p4tcc", 0)) 125 return (ENXIO); 126 127 device_set_desc(dev, "CPU Frequency Thermal Control"); 128 return (0); 129} 130 131static int 132p4tcc_attach(device_t dev) 133{ 134 struct p4tcc_softc *sc; 135 136 sc = device_get_softc(dev); 137 sc->dev = dev; 138 sc->set_count = TCC_NUM_SETTINGS; 139 140 /* 141 * On boot, the TCC is usually in Automatic mode where reading the 142 * current performance level is likely to produce bogus results. 143 * We record that state here and don't trust the contents of the 144 * status MSR until we've set it ourselves. 145 */ 146 sc->auto_mode = TRUE; 147 148 switch (cpu_id & 0xf) { 149 case 0x22: 150 case 0x24: 151 case 0x25: 152 case 0x27: 153 case 0x29: 154 /* 155 * These CPU models hang when set to 12.5%. 156 * See Errata O50, P44, and Z21. 157 */ 158 sc->set_count -= 1; 159 break; 160 case 0x07: /* errata N44 and P18 */ 161 case 0x0a: 162 case 0x12: 163 case 0x13: 164 /* 165 * These CPU models hang when set to 12.5% or 25%. 166 * See Errata N44 and P18l. 167 */ 168 sc->set_count -= 2; 169 break; 170 } 171 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 172 173 cpufreq_register(dev); 174 return (0); 175} 176 177static int 178p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 179{ 180 struct p4tcc_softc *sc; 181 int i, val; 182 183 sc = device_get_softc(dev); 184 if (sets == NULL || count == NULL) 185 return (EINVAL); 186 if (*count < sc->set_count) 187 return (E2BIG); 188 189 /* Return a list of valid settings for this driver. */ 190 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 191 val = TCC_NUM_SETTINGS; 192 for (i = 0; i < sc->set_count; i++, val--) { 193 sets[i].freq = TCC_SPEED_PERCENT(val); 194 sets[i].dev = dev; 195 } 196 *count = sc->set_count; 197 198 return (0); 199} 200 201static int 202p4tcc_set(device_t dev, const struct cf_setting *set) 203{ 204 struct p4tcc_softc *sc; 205 uint64_t mask, msr; 206 int val; 207 208 if (set == NULL) 209 return (EINVAL); 210 sc = device_get_softc(dev); 211 212 /* 213 * Validate requested state converts to a setting that is an integer 214 * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 215 */ 216 val = set->freq * TCC_NUM_SETTINGS / 10000; 217 if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 218 val < sc->lowest_val || val > TCC_NUM_SETTINGS) 219 return (EINVAL); 220 221 /* 222 * Read the current register and mask off the old setting and 223 * On-Demand bit. If the new val is < 100%, set it and the On-Demand 224 * bit, otherwise just return to Automatic mode. 225 */ 226 msr = rdmsr(MSR_THERM_CONTROL); 227 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 228 msr &= ~(mask | TCC_ENABLE_ONDEMAND); 229 if (val < TCC_NUM_SETTINGS) 230 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 231 wrmsr(MSR_THERM_CONTROL, msr); 232 233 /* 234 * Record whether we're now in Automatic or On-Demand mode. We have 235 * to cache this since there is no reliable way to check if TCC is in 236 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 237 * the ACPI Thermal Monitor Control Register produces 0 no matter 238 * what the current mode. 239 */ 240 if (msr & TCC_ENABLE_ONDEMAND) 241 sc->auto_mode = TRUE; 242 else 243 sc->auto_mode = FALSE; 244 245 return (0); 246} 247 248static int 249p4tcc_get(device_t dev, struct cf_setting *set) 250{ 251 struct p4tcc_softc *sc; 252 uint64_t msr; 253 int val; 254 255 if (set == NULL) 256 return (EINVAL); 257 sc = device_get_softc(dev); 258 259 /* 260 * Read the current register and extract the current setting. If 261 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 262 * 263 * XXX This is not completely reliable since at high temperatures 264 * the CPU may be automatically throttling to 50% but it's the best 265 * we can do. 266 */ 267 if (!sc->auto_mode) { 268 msr = rdmsr(MSR_THERM_CONTROL); 269 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 270 } else 271 val = TCC_NUM_SETTINGS; 272 273 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 274 set->freq = TCC_SPEED_PERCENT(val); 275 set->dev = dev; 276 277 return (0); 278} 279 280static int 281p4tcc_type(device_t dev, int *type) 282{ 283 284 if (type == NULL) 285 return (EINVAL); 286 287 *type = CPUFREQ_TYPE_RELATIVE; 288 return (0); 289} 290