p4tcc.c revision 142308
1/*- 2 * Copyright (c) 2005 Nate Lawson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27/* 28 * Throttle clock frequency by using the thermal control circuit. This 29 * operates independently of SpeedStep and ACPI throttling and is supported 30 * on Pentium 4 and later models (feature TM). 31 * 32 * Reference: Intel Developer's manual v.3 #245472-012 33 * 34 * The original version of this driver was written by Ted Unangst for 35 * OpenBSD and imported by Maxim Sobolev. It was rewritten by Nate Lawson 36 * for use with the cpufreq framework. 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: head/sys/i386/cpufreq/p4tcc.c 142308 2005-02-23 16:42:56Z njl $"); 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/cpu.h> 46#include <sys/kernel.h> 47#include <sys/module.h> 48 49#include <machine/md_var.h> 50#include <machine/specialreg.h> 51 52#include "cpufreq_if.h" 53 54struct p4tcc_softc { 55 device_t dev; 56 int set_count; 57 int lowest_val; 58 int auto_mode; 59}; 60 61#define TCC_NUM_SETTINGS 8 62 63#define TCC_ENABLE_ONDEMAND (1<<4) 64#define TCC_REG_OFFSET 1 65#define TCC_SPEED_PERCENT(x) ((10000 * (x)) / TCC_NUM_SETTINGS) 66 67static void p4tcc_identify(driver_t *driver, device_t parent); 68static int p4tcc_probe(device_t dev); 69static int p4tcc_attach(device_t dev); 70static int p4tcc_settings(device_t dev, struct cf_setting *sets, 71 int *count); 72static int p4tcc_set(device_t dev, const struct cf_setting *set); 73static int p4tcc_get(device_t dev, struct cf_setting *set); 74static int p4tcc_type(device_t dev, int *type); 75 76static device_method_t p4tcc_methods[] = { 77 /* Device interface */ 78 DEVMETHOD(device_identify, p4tcc_identify), 79 DEVMETHOD(device_probe, p4tcc_probe), 80 DEVMETHOD(device_attach, p4tcc_attach), 81 82 /* cpufreq interface */ 83 DEVMETHOD(cpufreq_drv_set, p4tcc_set), 84 DEVMETHOD(cpufreq_drv_get, p4tcc_get), 85 DEVMETHOD(cpufreq_drv_type, p4tcc_type), 86 DEVMETHOD(cpufreq_drv_settings, p4tcc_settings), 87 {0, 0} 88}; 89 90static driver_t p4tcc_driver = { 91 "p4tcc", 92 p4tcc_methods, 93 sizeof(struct p4tcc_softc), 94}; 95 96static devclass_t p4tcc_devclass; 97DRIVER_MODULE(p4tcc, cpu, p4tcc_driver, p4tcc_devclass, 0, 0); 98 99static void 100p4tcc_identify(driver_t *driver, device_t parent) 101{ 102 103 if ((cpu_feature & (CPUID_ACPI | CPUID_TM)) != (CPUID_ACPI | CPUID_TM)) 104 return; 105 if (BUS_ADD_CHILD(parent, 0, "p4tcc", -1) == NULL) 106 device_printf(parent, "add p4tcc child failed\n"); 107} 108 109static int 110p4tcc_probe(device_t dev) 111{ 112 113 if (resource_disabled("p4tcc", 0)) 114 return (ENXIO); 115 116 device_set_desc(dev, "CPU Frequency Thermal Control"); 117 return (0); 118} 119 120static int 121p4tcc_attach(device_t dev) 122{ 123 struct p4tcc_softc *sc; 124 125 sc = device_get_softc(dev); 126 sc->dev = dev; 127 sc->set_count = TCC_NUM_SETTINGS; 128 129 /* 130 * On boot, the TCC is usually in Automatic mode where reading the 131 * current performance level is likely to produce bogus results. 132 * We record that state here and don't trust the contents of the 133 * status MSR until we've set it ourselves. 134 */ 135 sc->auto_mode = TRUE; 136 137 switch (cpu_id & 0xf) { 138 case 0x22: 139 case 0x24: 140 case 0x25: 141 case 0x27: 142 case 0x29: 143 /* 144 * These CPU models hang when set to 12.5%. 145 * See Errata O50, P44, and Z21. 146 */ 147 sc->set_count -= 1; 148 break; 149 case 0x07: /* errata N44 and P18 */ 150 case 0x0a: 151 case 0x12: 152 case 0x13: 153 /* 154 * These CPU models hang when set to 12.5% or 25%. 155 * See Errata N44 and P18l. 156 */ 157 sc->set_count -= 2; 158 break; 159 } 160 sc->lowest_val = TCC_NUM_SETTINGS - sc->set_count + 1; 161 162 cpufreq_register(dev); 163 return (0); 164} 165 166static int 167p4tcc_settings(device_t dev, struct cf_setting *sets, int *count) 168{ 169 struct p4tcc_softc *sc; 170 int i, val; 171 172 sc = device_get_softc(dev); 173 if (sets == NULL || count == NULL) 174 return (EINVAL); 175 if (*count < sc->set_count) 176 return (E2BIG); 177 178 /* Return a list of valid settings for this driver. */ 179 memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->set_count); 180 val = TCC_NUM_SETTINGS; 181 for (i = 0; i < sc->set_count; i++, val--) { 182 sets[i].freq = TCC_SPEED_PERCENT(val); 183 sets[i].dev = dev; 184 } 185 *count = sc->set_count; 186 187 return (0); 188} 189 190static int 191p4tcc_set(device_t dev, const struct cf_setting *set) 192{ 193 struct p4tcc_softc *sc; 194 uint64_t mask, msr; 195 int val; 196 197 if (set == NULL) 198 return (EINVAL); 199 sc = device_get_softc(dev); 200 201 /* 202 * Validate requested state converts to a setting that is an integer 203 * from [sc->lowest_val .. TCC_NUM_SETTINGS]. 204 */ 205 val = set->freq * TCC_NUM_SETTINGS / 10000; 206 if (val * 10000 != set->freq * TCC_NUM_SETTINGS || 207 val < sc->lowest_val || val > TCC_NUM_SETTINGS) 208 return (EINVAL); 209 210 /* 211 * Read the current register and mask off the old setting and 212 * On-Demand bit. If the new val is < 100%, set it and the On-Demand 213 * bit, otherwise just return to Automatic mode. 214 */ 215 msr = rdmsr(MSR_THERM_CONTROL); 216 mask = (TCC_NUM_SETTINGS - 1) << TCC_REG_OFFSET; 217 msr &= ~(mask | TCC_ENABLE_ONDEMAND); 218 if (val < TCC_NUM_SETTINGS) 219 msr |= (val << TCC_REG_OFFSET) | TCC_ENABLE_ONDEMAND; 220 wrmsr(MSR_THERM_CONTROL, msr); 221 222 /* 223 * Record whether we're now in Automatic or On-Demand mode. We have 224 * to cache this since there is no reliable way to check if TCC is in 225 * Automatic mode (i.e., at 100% or possibly 50%). Reading bit 4 of 226 * the ACPI Thermal Monitor Control Register produces 0 no matter 227 * what the current mode. 228 */ 229 if (msr & TCC_ENABLE_ONDEMAND) 230 sc->auto_mode = TRUE; 231 else 232 sc->auto_mode = FALSE; 233 234 return (0); 235} 236 237static int 238p4tcc_get(device_t dev, struct cf_setting *set) 239{ 240 struct p4tcc_softc *sc; 241 uint64_t msr; 242 int val; 243 244 if (set == NULL) 245 return (EINVAL); 246 sc = device_get_softc(dev); 247 248 /* 249 * Read the current register and extract the current setting. If 250 * in automatic mode, assume we're at TCC_NUM_SETTINGS (100%). 251 * 252 * XXX This is not completely reliable since at high temperatures 253 * the CPU may be automatically throttling to 50% but it's the best 254 * we can do. 255 */ 256 if (!sc->auto_mode) { 257 msr = rdmsr(MSR_THERM_CONTROL); 258 val = (msr >> TCC_REG_OFFSET) & (TCC_NUM_SETTINGS - 1); 259 } else 260 val = TCC_NUM_SETTINGS; 261 262 memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); 263 set->freq = TCC_SPEED_PERCENT(val); 264 set->dev = dev; 265 266 return (0); 267} 268 269static int 270p4tcc_type(device_t dev, int *type) 271{ 272 273 if (type == NULL) 274 return (EINVAL); 275 276 *type = CPUFREQ_TYPE_RELATIVE; 277 return (0); 278} 279