est.c revision 212721
1142140Snjl/*- 2142140Snjl * Copyright (c) 2004 Colin Percival 3142140Snjl * Copyright (c) 2005 Nate Lawson 4142140Snjl * All rights reserved. 5142140Snjl * 6142140Snjl * Redistribution and use in source and binary forms, with or without 7142140Snjl * modification, are permitted providing that the following conditions 8142140Snjl * are met: 9142140Snjl * 1. Redistributions of source code must retain the above copyright 10142140Snjl * notice, this list of conditions and the following disclaimer. 11142140Snjl * 2. Redistributions in binary form must reproduce the above copyright 12142140Snjl * notice, this list of conditions and the following disclaimer in the 13142140Snjl * documentation and/or other materials provided with the distribution. 14142140Snjl * 15142140Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16142140Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17142140Snjl * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18142140Snjl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19142140Snjl * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20142140Snjl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21142140Snjl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22142140Snjl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23142140Snjl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24142140Snjl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25142140Snjl * POSSIBILITY OF SUCH DAMAGE. 26142140Snjl */ 27142140Snjl 28142140Snjl#include <sys/cdefs.h> 29142140Snjl__FBSDID("$FreeBSD: head/sys/x86/cpufreq/est.c 212721 2010-09-16 02:59:25Z mav $"); 30142140Snjl 31142140Snjl#include <sys/param.h> 32142140Snjl#include <sys/bus.h> 33142140Snjl#include <sys/cpu.h> 34142140Snjl#include <sys/kernel.h> 35143902Snjl#include <sys/malloc.h> 36142140Snjl#include <sys/module.h> 37142140Snjl#include <sys/smp.h> 38142140Snjl#include <sys/systm.h> 39142140Snjl 40142140Snjl#include "cpufreq_if.h" 41182048Sjhb#include <machine/clock.h> 42185341Sjkim#include <machine/cputypes.h> 43142140Snjl#include <machine/md_var.h> 44177040Sjhb#include <machine/specialreg.h> 45142140Snjl 46193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 47193530Sjkim 48144630Snjl#include <dev/acpica/acpivar.h> 49144630Snjl#include "acpi_if.h" 50144630Snjl 51142140Snjl/* Status/control registers (from the IA-32 System Programming Guide). */ 52142140Snjl#define MSR_PERF_STATUS 0x198 53142140Snjl#define MSR_PERF_CTL 0x199 54142140Snjl 55142140Snjl/* Register and bit for enabling SpeedStep. */ 56142140Snjl#define MSR_MISC_ENABLE 0x1a0 57142140Snjl#define MSR_SS_ENABLE (1<<16) 58142140Snjl 59142140Snjl/* Frequency and MSR control values. */ 60142140Snjltypedef struct { 61142140Snjl uint16_t freq; 62142140Snjl uint16_t volts; 63142140Snjl uint16_t id16; 64143902Snjl int power; 65142140Snjl} freq_info; 66142140Snjl 67142140Snjl/* Identifying characteristics of a processor and supported frequencies. */ 68142140Snjltypedef struct { 69185341Sjkim const u_int vendor_id; 70142140Snjl uint32_t id32; 71143902Snjl freq_info *freqtab; 72142140Snjl} cpu_info; 73142140Snjl 74142140Snjlstruct est_softc { 75143902Snjl device_t dev; 76143902Snjl int acpi_settings; 77182048Sjhb int msr_settings; 78143902Snjl freq_info *freq_list; 79142140Snjl}; 80142140Snjl 81142140Snjl/* Convert MHz and mV into IDs for passing to the MSR. */ 82142140Snjl#define ID16(MHz, mV, bus_clk) \ 83142140Snjl (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 84142140Snjl#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 85142140Snjl ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 86142140Snjl 87142140Snjl/* Format for storing IDs in our table. */ 88158446Snjl#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 89158446Snjl { MHz, mV, ID16(MHz, mV, bus_clk), mW } 90142140Snjl#define FREQ_INFO(MHz, mV, bus_clk) \ 91158446Snjl FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 92142140Snjl#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 93185341Sjkim { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 94158446Snjl#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 95185341Sjkim { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 96142140Snjl 97182201Sjhbstatic int msr_info_enabled = 0; 98182201SjhbTUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 99199273Smavstatic int strict = -1; 100199273SmavTUNABLE_INT("hw.est.strict", &strict); 101142140Snjl 102142140Snjl/* Default bus clock value for Centrino processors. */ 103142140Snjl#define INTEL_BUS_CLK 100 104142140Snjl 105142140Snjl/* XXX Update this if new CPUs have more settings. */ 106142140Snjl#define EST_MAX_SETTINGS 10 107142140SnjlCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 108142140Snjl 109142140Snjl/* Estimate in microseconds of latency for performing a transition. */ 110177296Sphk#define EST_TRANS_LAT 1000 111142140Snjl 112142140Snjl/* 113212721Smav * Frequency (MHz) and voltage (mV) settings. 114142140Snjl * 115143902Snjl * Dothan processors have multiple VID#s with different settings for 116143902Snjl * each VID#. Since we can't uniquely identify this info 117142140Snjl * without undisclosed methods from Intel, we can't support newer 118142140Snjl * processors with this table method. If ACPI Px states are supported, 119143902Snjl * we get info from them. 120212721Smav * 121212721Smav * Data from the "Intel Pentium M Processor Datasheet", 122212721Smav * Order Number 252612-003, Table 5. 123142140Snjl */ 124143902Snjlstatic freq_info PM17_130[] = { 125142140Snjl /* 130nm 1.70GHz Pentium M */ 126142140Snjl FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 127142140Snjl FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 128142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 129142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 130142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 131142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 132142140Snjl FREQ_INFO( 0, 0, 1), 133142140Snjl}; 134143902Snjlstatic freq_info PM16_130[] = { 135142140Snjl /* 130nm 1.60GHz Pentium M */ 136142140Snjl FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 137142140Snjl FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 138142140Snjl FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 139142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 140142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 141142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 142142140Snjl FREQ_INFO( 0, 0, 1), 143142140Snjl}; 144143902Snjlstatic freq_info PM15_130[] = { 145142140Snjl /* 130nm 1.50GHz Pentium M */ 146142140Snjl FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 147142140Snjl FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 148142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 149142140Snjl FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 150142140Snjl FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 151142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 152142140Snjl FREQ_INFO( 0, 0, 1), 153142140Snjl}; 154143902Snjlstatic freq_info PM14_130[] = { 155142140Snjl /* 130nm 1.40GHz Pentium M */ 156142140Snjl FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 157142140Snjl FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 158142140Snjl FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 159142140Snjl FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 160142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 161142140Snjl FREQ_INFO( 0, 0, 1), 162142140Snjl}; 163143902Snjlstatic freq_info PM13_130[] = { 164142140Snjl /* 130nm 1.30GHz Pentium M */ 165142140Snjl FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 166142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 167142140Snjl FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 168142140Snjl FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 169142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 170142140Snjl FREQ_INFO( 0, 0, 1), 171142140Snjl}; 172143902Snjlstatic freq_info PM13_LV_130[] = { 173142140Snjl /* 130nm 1.30GHz Low Voltage Pentium M */ 174142140Snjl FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 175142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 176142140Snjl FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 177142140Snjl FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 178142140Snjl FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 179142140Snjl FREQ_INFO( 800, 988, INTEL_BUS_CLK), 180142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 181142140Snjl FREQ_INFO( 0, 0, 1), 182142140Snjl}; 183143902Snjlstatic freq_info PM12_LV_130[] = { 184142140Snjl /* 130 nm 1.20GHz Low Voltage Pentium M */ 185142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 186142140Snjl FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 187142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 188142140Snjl FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 189142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 190142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 191142140Snjl FREQ_INFO( 0, 0, 1), 192142140Snjl}; 193143902Snjlstatic freq_info PM11_LV_130[] = { 194142140Snjl /* 130 nm 1.10GHz Low Voltage Pentium M */ 195142140Snjl FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 196142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 197142140Snjl FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 198142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 199142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 200142140Snjl FREQ_INFO( 0, 0, 1), 201142140Snjl}; 202143902Snjlstatic freq_info PM11_ULV_130[] = { 203142140Snjl /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 204142140Snjl FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 205142140Snjl FREQ_INFO(1000, 988, INTEL_BUS_CLK), 206142140Snjl FREQ_INFO( 900, 972, INTEL_BUS_CLK), 207142140Snjl FREQ_INFO( 800, 956, INTEL_BUS_CLK), 208142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 209142140Snjl FREQ_INFO( 0, 0, 1), 210142140Snjl}; 211143902Snjlstatic freq_info PM10_ULV_130[] = { 212142140Snjl /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 213142140Snjl FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 214142140Snjl FREQ_INFO( 900, 988, INTEL_BUS_CLK), 215142140Snjl FREQ_INFO( 800, 972, INTEL_BUS_CLK), 216142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 217142140Snjl FREQ_INFO( 0, 0, 1), 218142140Snjl}; 219142140Snjl 220142140Snjl/* 221142140Snjl * Data from "Intel Pentium M Processor on 90nm Process with 222212721Smav * 2-MB L2 Cache Datasheet", Order Number 302189-008, Table 5. 223142140Snjl */ 224143902Snjlstatic freq_info PM_765A_90[] = { 225142140Snjl /* 90 nm 2.10GHz Pentium M, VID #A */ 226142140Snjl FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 227142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 228142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 229142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 230142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 231142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 232142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 233142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 234142140Snjl FREQ_INFO( 0, 0, 1), 235142140Snjl}; 236143902Snjlstatic freq_info PM_765B_90[] = { 237142140Snjl /* 90 nm 2.10GHz Pentium M, VID #B */ 238142140Snjl FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 239142140Snjl FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 240142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 241142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 242142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 243142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 244142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 245142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 246142140Snjl FREQ_INFO( 0, 0, 1), 247142140Snjl}; 248143902Snjlstatic freq_info PM_765C_90[] = { 249142140Snjl /* 90 nm 2.10GHz Pentium M, VID #C */ 250142140Snjl FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 251142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 252142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 253142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 254142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 255142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 256142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 257142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 258142140Snjl FREQ_INFO( 0, 0, 1), 259142140Snjl}; 260143902Snjlstatic freq_info PM_765E_90[] = { 261142140Snjl /* 90 nm 2.10GHz Pentium M, VID #E */ 262142140Snjl FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 263142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 264142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 265142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 266142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 267142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 268142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 269142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 270142140Snjl FREQ_INFO( 0, 0, 1), 271142140Snjl}; 272143902Snjlstatic freq_info PM_755A_90[] = { 273142140Snjl /* 90 nm 2.00GHz Pentium M, VID #A */ 274142140Snjl FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 275142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 276142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 277142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 278142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 279142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 280142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 281142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 282142140Snjl FREQ_INFO( 0, 0, 1), 283142140Snjl}; 284143902Snjlstatic freq_info PM_755B_90[] = { 285142140Snjl /* 90 nm 2.00GHz Pentium M, VID #B */ 286142140Snjl FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 287142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 288142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 289142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 290142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 291142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 292142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 293142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 294142140Snjl FREQ_INFO( 0, 0, 1), 295142140Snjl}; 296143902Snjlstatic freq_info PM_755C_90[] = { 297142140Snjl /* 90 nm 2.00GHz Pentium M, VID #C */ 298142140Snjl FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 299142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 300142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 301142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 302142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 303142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 304142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 305142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 306142140Snjl FREQ_INFO( 0, 0, 1), 307142140Snjl}; 308143902Snjlstatic freq_info PM_755D_90[] = { 309142140Snjl /* 90 nm 2.00GHz Pentium M, VID #D */ 310142140Snjl FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 311142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 312142140Snjl FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 313142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 314142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 315142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 316142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 317142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 318142140Snjl FREQ_INFO( 0, 0, 1), 319142140Snjl}; 320143902Snjlstatic freq_info PM_745A_90[] = { 321142140Snjl /* 90 nm 1.80GHz Pentium M, VID #A */ 322142140Snjl FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 323142140Snjl FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 324142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 325142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 326142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 327142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 328142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 329142140Snjl FREQ_INFO( 0, 0, 1), 330142140Snjl}; 331143902Snjlstatic freq_info PM_745B_90[] = { 332142140Snjl /* 90 nm 1.80GHz Pentium M, VID #B */ 333142140Snjl FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 334142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 335142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 336142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 337142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 338142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 339142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 340142140Snjl FREQ_INFO( 0, 0, 1), 341142140Snjl}; 342143902Snjlstatic freq_info PM_745C_90[] = { 343142140Snjl /* 90 nm 1.80GHz Pentium M, VID #C */ 344142140Snjl FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 345142140Snjl FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 346142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 347142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 348142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 349142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 350142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 351142140Snjl FREQ_INFO( 0, 0, 1), 352142140Snjl}; 353143902Snjlstatic freq_info PM_745D_90[] = { 354142140Snjl /* 90 nm 1.80GHz Pentium M, VID #D */ 355142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 356142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 357142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 358142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 359142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 360142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 361142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 362142140Snjl FREQ_INFO( 0, 0, 1), 363142140Snjl}; 364143902Snjlstatic freq_info PM_735A_90[] = { 365142140Snjl /* 90 nm 1.70GHz Pentium M, VID #A */ 366142140Snjl FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 367142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 368142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 369142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 370142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 371142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 372142140Snjl FREQ_INFO( 0, 0, 1), 373142140Snjl}; 374143902Snjlstatic freq_info PM_735B_90[] = { 375142140Snjl /* 90 nm 1.70GHz Pentium M, VID #B */ 376142140Snjl FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 377142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 378142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 379142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 380142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 381142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 382142140Snjl FREQ_INFO( 0, 0, 1), 383142140Snjl}; 384143902Snjlstatic freq_info PM_735C_90[] = { 385142140Snjl /* 90 nm 1.70GHz Pentium M, VID #C */ 386142140Snjl FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 387142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 388142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 389142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 390142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 391142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 392142140Snjl FREQ_INFO( 0, 0, 1), 393142140Snjl}; 394143902Snjlstatic freq_info PM_735D_90[] = { 395142140Snjl /* 90 nm 1.70GHz Pentium M, VID #D */ 396142140Snjl FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 397142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 398142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 399142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 400142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 401142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 402142140Snjl FREQ_INFO( 0, 0, 1), 403142140Snjl}; 404143902Snjlstatic freq_info PM_725A_90[] = { 405142140Snjl /* 90 nm 1.60GHz Pentium M, VID #A */ 406142140Snjl FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 407142140Snjl FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 408142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 409142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 410142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 411142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 412142140Snjl FREQ_INFO( 0, 0, 1), 413142140Snjl}; 414143902Snjlstatic freq_info PM_725B_90[] = { 415142140Snjl /* 90 nm 1.60GHz Pentium M, VID #B */ 416142140Snjl FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 417142140Snjl FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 418142140Snjl FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 419142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 420142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 421142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 422142140Snjl FREQ_INFO( 0, 0, 1), 423142140Snjl}; 424143902Snjlstatic freq_info PM_725C_90[] = { 425142140Snjl /* 90 nm 1.60GHz Pentium M, VID #C */ 426142140Snjl FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 427142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 428142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 429142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 430142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 431142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 432142140Snjl FREQ_INFO( 0, 0, 1), 433142140Snjl}; 434143902Snjlstatic freq_info PM_725D_90[] = { 435142140Snjl /* 90 nm 1.60GHz Pentium M, VID #D */ 436142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 437142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 438142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 439142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 440142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 441142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 442142140Snjl FREQ_INFO( 0, 0, 1), 443142140Snjl}; 444143902Snjlstatic freq_info PM_715A_90[] = { 445142140Snjl /* 90 nm 1.50GHz Pentium M, VID #A */ 446142140Snjl FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 447142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 448142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 449142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 450142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 451142140Snjl FREQ_INFO( 0, 0, 1), 452142140Snjl}; 453143902Snjlstatic freq_info PM_715B_90[] = { 454142140Snjl /* 90 nm 1.50GHz Pentium M, VID #B */ 455142140Snjl FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 456142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 457142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 458142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 459142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 460142140Snjl FREQ_INFO( 0, 0, 1), 461142140Snjl}; 462143902Snjlstatic freq_info PM_715C_90[] = { 463142140Snjl /* 90 nm 1.50GHz Pentium M, VID #C */ 464142140Snjl FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 465142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 466142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 467142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 468142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 469142140Snjl FREQ_INFO( 0, 0, 1), 470142140Snjl}; 471143902Snjlstatic freq_info PM_715D_90[] = { 472142140Snjl /* 90 nm 1.50GHz Pentium M, VID #D */ 473142140Snjl FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 474142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 475142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 476142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 477142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 478142140Snjl FREQ_INFO( 0, 0, 1), 479142140Snjl}; 480155996Scpercivastatic freq_info PM_778_90[] = { 481155996Scperciva /* 90 nm 1.60GHz Low Voltage Pentium M */ 482155996Scperciva FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 483155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 484155996Scperciva FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 485155996Scperciva FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 486155996Scperciva FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 487155996Scperciva FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 488155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 489155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 490155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 491155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 492155996Scperciva FREQ_INFO( 0, 0, 1), 493155996Scperciva}; 494155996Scpercivastatic freq_info PM_758_90[] = { 495155996Scperciva /* 90 nm 1.50GHz Low Voltage Pentium M */ 496155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 497155996Scperciva FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 498155996Scperciva FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 499155996Scperciva FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 500155996Scperciva FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 501155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 502155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 503155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 504155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 505155996Scperciva FREQ_INFO( 0, 0, 1), 506155996Scperciva}; 507143902Snjlstatic freq_info PM_738_90[] = { 508142140Snjl /* 90 nm 1.40GHz Low Voltage Pentium M */ 509142140Snjl FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 510142140Snjl FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 511142140Snjl FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 512142140Snjl FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 513142140Snjl FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 514142140Snjl FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 515142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 516142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 517142140Snjl FREQ_INFO( 0, 0, 1), 518142140Snjl}; 519155996Scpercivastatic freq_info PM_773G_90[] = { 520155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 521155996Scperciva FREQ_INFO(1300, 956, INTEL_BUS_CLK), 522155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 523155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 524155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 525155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 526155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 527155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 528155996Scperciva}; 529155996Scpercivastatic freq_info PM_773H_90[] = { 530155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 531155996Scperciva FREQ_INFO(1300, 940, INTEL_BUS_CLK), 532155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 533155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 534155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 535155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 536155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 537155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 538155996Scperciva}; 539155996Scpercivastatic freq_info PM_773I_90[] = { 540155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 541155996Scperciva FREQ_INFO(1300, 924, INTEL_BUS_CLK), 542155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 543155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 544155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 545155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 546155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 547155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 548155996Scperciva}; 549155996Scpercivastatic freq_info PM_773J_90[] = { 550155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 551155996Scperciva FREQ_INFO(1300, 908, INTEL_BUS_CLK), 552155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 553155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 554155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 555155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 556155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 557155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 558155996Scperciva}; 559155996Scpercivastatic freq_info PM_773K_90[] = { 560155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 561155996Scperciva FREQ_INFO(1300, 892, INTEL_BUS_CLK), 562155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 563155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 564155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 565155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 566155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 567155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 568155996Scperciva}; 569155996Scpercivastatic freq_info PM_773L_90[] = { 570155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 571155996Scperciva FREQ_INFO(1300, 876, INTEL_BUS_CLK), 572155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 573155996Scperciva FREQ_INFO(1100, 860, INTEL_BUS_CLK), 574155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 575155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 576155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 577155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 578155996Scperciva}; 579155996Scpercivastatic freq_info PM_753G_90[] = { 580155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 581155996Scperciva FREQ_INFO(1200, 956, INTEL_BUS_CLK), 582155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 583155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 584155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 585155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 586155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 587155996Scperciva}; 588155996Scpercivastatic freq_info PM_753H_90[] = { 589155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 590155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 591155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 592155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 593155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 594155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 595155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 596155996Scperciva}; 597155996Scpercivastatic freq_info PM_753I_90[] = { 598155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 599155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 600155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 601155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 602155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 603155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 604155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 605155996Scperciva}; 606155996Scpercivastatic freq_info PM_753J_90[] = { 607155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 608155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 609155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 610155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 611155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 612155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 613155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 614155996Scperciva}; 615155996Scpercivastatic freq_info PM_753K_90[] = { 616155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 617155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 618155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 619155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 620155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 621155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 622155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 623155996Scperciva}; 624155996Scpercivastatic freq_info PM_753L_90[] = { 625155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 626155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 627155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 628155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 629155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 630155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 631155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 632155996Scperciva}; 633155996Scperciva 634155996Scpercivastatic freq_info PM_733JG_90[] = { 635155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 636155996Scperciva FREQ_INFO(1100, 956, INTEL_BUS_CLK), 637155996Scperciva FREQ_INFO(1000, 940, INTEL_BUS_CLK), 638155996Scperciva FREQ_INFO( 900, 908, INTEL_BUS_CLK), 639155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 640155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 641155996Scperciva}; 642155996Scpercivastatic freq_info PM_733JH_90[] = { 643155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 644155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 645155996Scperciva FREQ_INFO(1000, 924, INTEL_BUS_CLK), 646155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 647155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 648155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 649155996Scperciva}; 650155996Scpercivastatic freq_info PM_733JI_90[] = { 651155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 652155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 653155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 654155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 655155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 656155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 657155996Scperciva}; 658155996Scpercivastatic freq_info PM_733JJ_90[] = { 659155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 660155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 661155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 662155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 663155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 664155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 665155996Scperciva}; 666155996Scpercivastatic freq_info PM_733JK_90[] = { 667155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 668155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 669155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 670155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 671155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 672155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 673155996Scperciva}; 674155996Scpercivastatic freq_info PM_733JL_90[] = { 675155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 676155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 677155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 678155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 679155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 680155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 681155996Scperciva}; 682143902Snjlstatic freq_info PM_733_90[] = { 683142140Snjl /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 684142140Snjl FREQ_INFO(1100, 940, INTEL_BUS_CLK), 685142140Snjl FREQ_INFO(1000, 924, INTEL_BUS_CLK), 686142140Snjl FREQ_INFO( 900, 892, INTEL_BUS_CLK), 687142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 688142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 689142140Snjl FREQ_INFO( 0, 0, 1), 690142140Snjl}; 691143902Snjlstatic freq_info PM_723_90[] = { 692142140Snjl /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 693142140Snjl FREQ_INFO(1000, 940, INTEL_BUS_CLK), 694142140Snjl FREQ_INFO( 900, 908, INTEL_BUS_CLK), 695142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 696142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 697142140Snjl FREQ_INFO( 0, 0, 1), 698142140Snjl}; 699142140Snjl 700158446Snjl/* 701158446Snjl * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 702158446Snjl * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 703158446Snjl */ 704158446Snjlstatic freq_info C7M_795[] = { 705158446Snjl /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 706158446Snjl FREQ_INFO_PWR(2000, 1148, 133, 20000), 707158446Snjl FREQ_INFO_PWR(1867, 1132, 133, 18000), 708158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 709158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 710158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 711158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 712158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 713158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 714158446Snjl FREQ_INFO(0, 0, 1), 715158446Snjl}; 716158446Snjlstatic freq_info C7M_785[] = { 717158446Snjl /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 718158446Snjl FREQ_INFO_PWR(1867, 1148, 133, 18000), 719158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 720158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 721158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 722158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 723158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 724158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 725158446Snjl FREQ_INFO(0, 0, 1), 726158446Snjl}; 727158446Snjlstatic freq_info C7M_765[] = { 728158446Snjl /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 729158446Snjl FREQ_INFO_PWR(1600, 1084, 133, 15000), 730158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 731158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 732158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 733158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 734158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 735158446Snjl FREQ_INFO(0, 0, 1), 736158446Snjl}; 737158446Snjl 738158446Snjlstatic freq_info C7M_794[] = { 739158446Snjl /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 740158446Snjl FREQ_INFO_PWR(2000, 1148, 100, 20000), 741158446Snjl FREQ_INFO_PWR(1800, 1132, 100, 18000), 742158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 743158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 744158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 745158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 746158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 747158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 748158446Snjl FREQ_INFO(0, 0, 1), 749158446Snjl}; 750158446Snjlstatic freq_info C7M_784[] = { 751158446Snjl /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 752158446Snjl FREQ_INFO_PWR(1800, 1148, 100, 18000), 753158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 754158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 755158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 756158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 757158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 758158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 759158446Snjl FREQ_INFO(0, 0, 1), 760158446Snjl}; 761158446Snjlstatic freq_info C7M_764[] = { 762158446Snjl /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 763158446Snjl FREQ_INFO_PWR(1600, 1084, 100, 15000), 764158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 765158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 766158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 767158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 768158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 769158446Snjl FREQ_INFO(0, 0, 1), 770158446Snjl}; 771158446Snjlstatic freq_info C7M_754[] = { 772158446Snjl /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 773158446Snjl FREQ_INFO_PWR(1500, 1004, 100, 12000), 774158446Snjl FREQ_INFO_PWR(1400, 988, 100, 11000), 775158446Snjl FREQ_INFO_PWR(1000, 940, 100, 9000), 776158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 777158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 778158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 779158446Snjl FREQ_INFO(0, 0, 1), 780158446Snjl}; 781158446Snjlstatic freq_info C7M_771[] = { 782158446Snjl /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 783158446Snjl FREQ_INFO_PWR(1200, 860, 100, 7000), 784158446Snjl FREQ_INFO_PWR(1000, 860, 100, 6000), 785158446Snjl FREQ_INFO_PWR( 800, 844, 100, 5500), 786158446Snjl FREQ_INFO_PWR( 600, 844, 100, 5000), 787158446Snjl FREQ_INFO_PWR( 400, 844, 100, 4000), 788158446Snjl FREQ_INFO(0, 0, 1), 789158446Snjl}; 790158446Snjl 791158446Snjlstatic freq_info C7M_775_ULV[] = { 792158446Snjl /* 1.50GHz Centaur C7-M ULV */ 793158446Snjl FREQ_INFO_PWR(1500, 956, 100, 7500), 794158446Snjl FREQ_INFO_PWR(1400, 940, 100, 6000), 795158446Snjl FREQ_INFO_PWR(1000, 860, 100, 5000), 796158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 797158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 798158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 799158446Snjl FREQ_INFO(0, 0, 1), 800158446Snjl}; 801158446Snjlstatic freq_info C7M_772_ULV[] = { 802158446Snjl /* 1.20GHz Centaur C7-M ULV */ 803158446Snjl FREQ_INFO_PWR(1200, 844, 100, 5000), 804158446Snjl FREQ_INFO_PWR(1000, 844, 100, 4000), 805158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 806158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 807158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 808158446Snjl FREQ_INFO(0, 0, 1), 809158446Snjl}; 810158446Snjlstatic freq_info C7M_779_ULV[] = { 811158446Snjl /* 1.00GHz Centaur C7-M ULV */ 812158446Snjl FREQ_INFO_PWR(1000, 796, 100, 3500), 813158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 814158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 815158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 816158446Snjl FREQ_INFO(0, 0, 1), 817158446Snjl}; 818158446Snjlstatic freq_info C7M_770_ULV[] = { 819158446Snjl /* 1.00GHz Centaur C7-M ULV */ 820158446Snjl FREQ_INFO_PWR(1000, 844, 100, 5000), 821158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 822158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 823158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 824158446Snjl FREQ_INFO(0, 0, 1), 825158446Snjl}; 826158446Snjl 827143902Snjlstatic cpu_info ESTprocs[] = { 828142140Snjl INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 829142140Snjl INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 830142140Snjl INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 831142140Snjl INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 832142140Snjl INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 833142140Snjl INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 834142140Snjl INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 835142140Snjl INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 836142140Snjl INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 837142140Snjl INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 838142140Snjl INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 839142140Snjl INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 840142140Snjl INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 841142140Snjl INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 842142140Snjl INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 843142140Snjl INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 844142140Snjl INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 845142140Snjl INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 846142140Snjl INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 847142140Snjl INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 848142140Snjl INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 849142140Snjl INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 850142140Snjl INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 851142140Snjl INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 852142140Snjl INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 853142140Snjl INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 854142140Snjl INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 855142140Snjl INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 856142140Snjl INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 857142140Snjl INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 858142140Snjl INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 859142140Snjl INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 860142140Snjl INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 861142140Snjl INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 862155996Scperciva INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 863155996Scperciva INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 864142140Snjl INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 865155996Scperciva INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 866155996Scperciva INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 867155996Scperciva INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 868155996Scperciva INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 869155996Scperciva INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 870155996Scperciva INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 871155996Scperciva INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 872155996Scperciva INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 873155996Scperciva INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 874155996Scperciva INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 875155996Scperciva INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 876155996Scperciva INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 877155996Scperciva INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 878155996Scperciva INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 879155996Scperciva INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 880155996Scperciva INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 881155996Scperciva INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 882155996Scperciva INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 883142140Snjl INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 884142140Snjl INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 885158446Snjl 886158446Snjl CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 887158446Snjl CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 888158446Snjl CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 889158446Snjl CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 890158446Snjl CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 891158446Snjl CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 892158446Snjl CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 893158446Snjl CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 894158446Snjl CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 895158446Snjl CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 896158446Snjl CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 897158446Snjl CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 898185341Sjkim { 0, 0, NULL }, 899142140Snjl}; 900142140Snjl 901142140Snjlstatic void est_identify(driver_t *driver, device_t parent); 902144630Snjlstatic int est_features(driver_t *driver, u_int *features); 903142140Snjlstatic int est_probe(device_t parent); 904142140Snjlstatic int est_attach(device_t parent); 905142140Snjlstatic int est_detach(device_t parent); 906143902Snjlstatic int est_get_info(device_t dev); 907143902Snjlstatic int est_acpi_info(device_t dev, freq_info **freqs); 908158446Snjlstatic int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 909182048Sjhbstatic int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 910143902Snjlstatic freq_info *est_get_current(freq_info *freq_list); 911142140Snjlstatic int est_settings(device_t dev, struct cf_setting *sets, int *count); 912142140Snjlstatic int est_set(device_t dev, const struct cf_setting *set); 913142140Snjlstatic int est_get(device_t dev, struct cf_setting *set); 914142140Snjlstatic int est_type(device_t dev, int *type); 915176649Srpaulostatic int est_set_id16(device_t dev, uint16_t id16, int need_check); 916176649Srpaulostatic void est_get_id16(uint16_t *id16_p); 917142140Snjl 918142140Snjlstatic device_method_t est_methods[] = { 919142140Snjl /* Device interface */ 920142140Snjl DEVMETHOD(device_identify, est_identify), 921142140Snjl DEVMETHOD(device_probe, est_probe), 922142140Snjl DEVMETHOD(device_attach, est_attach), 923142140Snjl DEVMETHOD(device_detach, est_detach), 924142140Snjl 925142140Snjl /* cpufreq interface */ 926142140Snjl DEVMETHOD(cpufreq_drv_set, est_set), 927142140Snjl DEVMETHOD(cpufreq_drv_get, est_get), 928142140Snjl DEVMETHOD(cpufreq_drv_type, est_type), 929142140Snjl DEVMETHOD(cpufreq_drv_settings, est_settings), 930144630Snjl 931144630Snjl /* ACPI interface */ 932144630Snjl DEVMETHOD(acpi_get_features, est_features), 933144630Snjl 934142140Snjl {0, 0} 935142140Snjl}; 936142140Snjl 937142140Snjlstatic driver_t est_driver = { 938142140Snjl "est", 939142140Snjl est_methods, 940142140Snjl sizeof(struct est_softc), 941142140Snjl}; 942142140Snjl 943142140Snjlstatic devclass_t est_devclass; 944142140SnjlDRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 945142140Snjl 946144630Snjlstatic int 947144630Snjlest_features(driver_t *driver, u_int *features) 948144630Snjl{ 949144630Snjl 950219046Sjkim /* Notify the ACPI CPU that we support direct access to MSRs */ 951219046Sjkim *features = ACPI_CAP_PERF_MSRS; 952219046Sjkim return (0); 953219046Sjkim} 954219046Sjkim 955144630Snjlstatic void 956144630Snjlest_identify(driver_t *driver, device_t parent) 957144630Snjl{ 958142140Snjl device_t child; 959142140Snjl 960142140Snjl /* Make sure we're not being doubly invoked. */ 961144630Snjl if (device_find_child(parent, "est", -1) != NULL) 962142140Snjl return; 963142140Snjl 964142140Snjl /* Check that CPUID is supported and the vendor is Intel.*/ 965142140Snjl if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 966142140Snjl cpu_vendor_id != CPU_VENDOR_CENTAUR)) 967142140Snjl return; 968185341Sjkim 969185341Sjkim /* 970142140Snjl * Check if the CPU supports EST. 971142140Snjl */ 972158446Snjl if (!(cpu_feature2 & CPUID2_EST)) 973177040Sjhb return; 974158446Snjl 975177040Sjhb /* 976142140Snjl * We add a child for each CPU since settings must be performed 977142140Snjl * on each CPU in the SMP case. 978142625Snjl */ 979142625Snjl child = BUS_ADD_CHILD(parent, 10, "est", -1); 980142625Snjl if (child == NULL) 981142625Snjl device_printf(parent, "add est child failed\n"); 982181691Sjhb} 983144630Snjl 984142140Snjlstatic int 985142140Snjlest_probe(device_t dev) 986142140Snjl{ 987142140Snjl device_t perf_dev; 988142140Snjl uint64_t msr; 989142140Snjl int error, type; 990142140Snjl 991142140Snjl if (resource_disabled("est", 0)) 992142140Snjl return (ENXIO); 993212721Smav 994241885Seadler /* 995241885Seadler * If the ACPI perf driver has attached and is not just offering 996241885Seadler * info, let it manage things. 997142140Snjl */ 998142140Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 999142140Snjl if (perf_dev && device_is_attached(perf_dev)) { 1000142140Snjl error = CPUFREQ_DRV_TYPE(perf_dev, &type); 1001142140Snjl if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 1002142140Snjl return (ENXIO); 1003142140Snjl } 1004142140Snjl 1005142140Snjl /* Attempt to enable SpeedStep if not currently enabled. */ 1006142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1007142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1008142140Snjl wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1009142140Snjl if (bootverbose) 1010142140Snjl device_printf(dev, "enabling SpeedStep\n"); 1011142140Snjl 1012143902Snjl /* Check if the enable failed. */ 1013143902Snjl msr = rdmsr(MSR_MISC_ENABLE); 1014142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1015142140Snjl device_printf(dev, "failed to enable SpeedStep\n"); 1016142140Snjl return (ENXIO); 1017142140Snjl } 1018142140Snjl } 1019142140Snjl 1020142140Snjl device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1021142140Snjl return (0); 1022142140Snjl} 1023142140Snjl 1024142140Snjlstatic int 1025142140Snjlest_attach(device_t dev) 1026142140Snjl{ 1027142140Snjl struct est_softc *sc; 1028142140Snjl 1029142140Snjl sc = device_get_softc(dev); 1030142140Snjl sc->dev = dev; 1031142140Snjl 1032142140Snjl /* On SMP system we can't guarantie independent freq setting. */ 1033142140Snjl if (strict == -1 && mp_ncpus > 1) 1034143902Snjl strict = 0; 1035199273Smav /* Check CPU for supported settings. */ 1036199273Smav if (est_get_info(dev)) 1037199273Smav return (ENXIO); 1038143902Snjl 1039143902Snjl cpufreq_register(dev); 1040143902Snjl return (0); 1041143902Snjl} 1042142140Snjl 1043142140Snjlstatic int 1044142140Snjlest_detach(device_t dev) 1045142140Snjl{ 1046142140Snjl struct est_softc *sc; 1047142140Snjl int error; 1048142140Snjl 1049143902Snjl error = cpufreq_unregister(dev); 1050182908Sjhb if (error) 1051143902Snjl return (error); 1052182908Sjhb 1053182908Sjhb sc = device_get_softc(dev); 1054182908Sjhb if (sc->acpi_settings || sc->msr_settings) 1055182908Sjhb free(sc->freq_list, M_DEVBUF); 1056143902Snjl return (0); 1057182048Sjhb} 1058143902Snjl 1059182908Sjhb/* 1060142140Snjl * Probe for supported CPU settings. First, check our static table of 1061142140Snjl * settings. If no match, try using the ones offered by acpi_perf 1062143902Snjl * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1063143902Snjl * series) export both legacy SMM IO-based access and direct MSR access 1064143902Snjl * but the direct access specifies invalid values for _PSS. 1065143902Snjl */ 1066143902Snjlstatic int 1067143902Snjlest_get_info(device_t dev) 1068143902Snjl{ 1069142140Snjl struct est_softc *sc; 1070143902Snjl uint64_t msr; 1071142140Snjl int error; 1072143902Snjl 1073143902Snjl sc = device_get_softc(dev); 1074143902Snjl msr = rdmsr(MSR_PERF_STATUS); 1075143902Snjl error = est_table_info(dev, msr, &sc->freq_list); 1076143902Snjl if (error) 1077143902Snjl error = est_acpi_info(dev, &sc->freq_list); 1078158446Snjl if (error) 1079143902Snjl error = est_msr_info(dev, msr, &sc->freq_list); 1080143902Snjl 1081182048Sjhb if (error) { 1082182048Sjhb printf( 1083143902Snjl "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1084143902Snjl "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1085143902Snjl return (ENXIO); 1086143902Snjl } 1087148583Scperciva 1088143902Snjl return (0); 1089143902Snjl} 1090143902Snjl 1091143902Snjlstatic int 1092143902Snjlest_acpi_info(device_t dev, freq_info **freqs) 1093143902Snjl{ 1094143902Snjl struct est_softc *sc; 1095143902Snjl struct cf_setting *sets; 1096143902Snjl freq_info *table; 1097143902Snjl device_t perf_dev; 1098143902Snjl int count, error, i, j; 1099143902Snjl uint16_t saved_id16; 1100143902Snjl 1101199273Smav perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1102179445Sjhb if (perf_dev == NULL || !device_is_attached(perf_dev)) 1103143902Snjl return (ENXIO); 1104143902Snjl 1105143902Snjl /* Fetch settings from acpi_perf. */ 1106143902Snjl sc = device_get_softc(dev); 1107143902Snjl table = NULL; 1108143902Snjl sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1109143902Snjl if (sets == NULL) 1110143902Snjl return (ENOMEM); 1111143902Snjl count = MAX_SETTINGS; 1112143902Snjl error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1113143902Snjl if (error) 1114176714Sgibbs goto out; 1115143902Snjl 1116143902Snjl /* Parse settings into our local table format. */ 1117143902Snjl table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1118143902Snjl if (table == NULL) { 1119143902Snjl error = ENOMEM; 1120144881Snjl goto out; 1121143902Snjl } 1122143902Snjl est_get_id16(&saved_id16); 1123143902Snjl for (i = 0, j = 0; i < count; i++) { 1124143902Snjl /* 1125179445Sjhb * Confirm id16 value is correct. 1126176649Srpaulo */ 1127143902Snjl if (sets[i].freq > 0) { 1128176649Srpaulo error = est_set_id16(dev, sets[i].spec[0], strict); 1129143902Snjl if (error != 0) { 1130176649Srpaulo if (bootverbose) 1131209339Smav device_printf(dev, "Invalid freq %u, " 1132209339Smav "ignored.\n", sets[i].freq); 1133212721Smav continue; 1134176649Srpaulo } 1135176649Srpaulo table[j].freq = sets[i].freq; 1136199273Smav table[j].volts = sets[i].volts; 1137176649Srpaulo table[j].id16 = sets[i].spec[0]; 1138199273Smav table[j].power = sets[i].power; 1139199273Smav ++j; 1140199273Smav } 1141199273Smav } 1142199273Smav /* restore saved setting */ 1143176649Srpaulo est_set_id16(dev, saved_id16, 0); 1144143902Snjl 1145179445Sjhb /* Mark end of table with a terminator. */ 1146179445Sjhb bzero(&table[j], sizeof(freq_info)); 1147143902Snjl 1148144881Snjl sc->acpi_settings = TRUE; 1149176649Srpaulo *freqs = table; 1150144881Snjl error = 0; 1151143902Snjl 1152143902Snjlout: 1153143902Snjl if (sets) 1154143902Snjl free(sets, M_TEMP); 1155143902Snjl if (error && table) 1156143902Snjl free(table, M_DEVBUF); 1157143902Snjl return (error); 1158143902Snjl} 1159143902Snjl 1160143902Snjlstatic int 1161143902Snjlest_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1162143902Snjl{ 1163143902Snjl cpu_info *p; 1164158446Snjl uint32_t id; 1165143902Snjl 1166143902Snjl /* Find a table which matches (vendor, id32). */ 1167142140Snjl id = msr >> 32; 1168142140Snjl for (p = ESTprocs; p->id32 != 0; p++) { 1169158446Snjl if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1170142140Snjl break; 1171142140Snjl } 1172185341Sjkim if (p->id32 == 0) 1173142140Snjl return (EOPNOTSUPP); 1174142140Snjl 1175142140Snjl /* Make sure the current setpoint is valid. */ 1176142140Snjl if (est_get_current(p->freqtab) == NULL) { 1177142140Snjl device_printf(dev, "current setting not found in table\n"); 1178142140Snjl return (EOPNOTSUPP); 1179143902Snjl } 1180143902Snjl 1181142140Snjl *freqs = p->freqtab; 1182143902Snjl return (0); 1183142140Snjl} 1184142140Snjl 1185142140Snjlstatic int 1186142140Snjlbus_speed_ok(int bus) 1187142140Snjl{ 1188182048Sjhb 1189182048Sjhb switch (bus) { 1190182048Sjhb case 100: 1191182048Sjhb case 133: 1192182048Sjhb case 333: 1193182048Sjhb return (1); 1194182048Sjhb default: 1195182048Sjhb return (0); 1196182048Sjhb } 1197182048Sjhb} 1198182048Sjhb 1199182048Sjhb/* 1200182048Sjhb * Flesh out a simple rate table containing the high and low frequencies 1201182048Sjhb * based on the current clock speed and the upper 32 bits of the MSR. 1202182048Sjhb */ 1203182048Sjhbstatic int 1204182048Sjhbest_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1205182048Sjhb{ 1206182048Sjhb struct est_softc *sc; 1207182048Sjhb freq_info *fp; 1208182048Sjhb int bus, freq, volts; 1209182048Sjhb uint16_t id; 1210182048Sjhb 1211182048Sjhb if (!msr_info_enabled) 1212182048Sjhb return (EOPNOTSUPP); 1213182048Sjhb 1214182201Sjhb /* Figure out the bus clock. */ 1215182201Sjhb freq = tsc_freq / 1000000; 1216182201Sjhb id = msr >> 32; 1217182048Sjhb bus = freq / (id >> 8); 1218220433Sjkim device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1219182048Sjhb if (!bus_speed_ok(bus)) { 1220182048Sjhb /* We may be running on the low frequency. */ 1221182048Sjhb id = msr >> 48; 1222182048Sjhb bus = freq / (id >> 8); 1223182048Sjhb device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1224182048Sjhb if (!bus_speed_ok(bus)) 1225182048Sjhb return (EOPNOTSUPP); 1226182048Sjhb 1227182048Sjhb /* Calculate high frequency. */ 1228182048Sjhb id = msr >> 32; 1229212721Smav freq = ((id >> 8) & 0xff) * bus; 1230182048Sjhb } 1231182048Sjhb 1232182048Sjhb /* Fill out a new freq table containing just the high and low freqs. */ 1233182048Sjhb sc = device_get_softc(dev); 1234182048Sjhb fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1235182048Sjhb 1236182048Sjhb /* First, the high frequency. */ 1237182048Sjhb volts = id & 0xff; 1238182048Sjhb if (volts != 0) { 1239182048Sjhb volts <<= 4; 1240182048Sjhb volts += 700; 1241182048Sjhb } 1242182048Sjhb fp[0].freq = freq; 1243182048Sjhb fp[0].volts = volts; 1244182048Sjhb fp[0].id16 = id; 1245182048Sjhb fp[0].power = CPUFREQ_VAL_UNKNOWN; 1246182048Sjhb device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1247182048Sjhb volts); 1248182048Sjhb 1249182048Sjhb /* Second, the low frequency. */ 1250182048Sjhb id = msr >> 48; 1251182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1252182048Sjhb volts = id & 0xff; 1253182048Sjhb if (volts != 0) { 1254182048Sjhb volts <<= 4; 1255182048Sjhb volts += 700; 1256182048Sjhb } 1257182048Sjhb fp[1].freq = freq; 1258182048Sjhb fp[1].volts = volts; 1259182048Sjhb fp[1].id16 = id; 1260182048Sjhb fp[1].power = CPUFREQ_VAL_UNKNOWN; 1261182048Sjhb device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1262182048Sjhb volts); 1263182048Sjhb 1264182048Sjhb /* Table is already terminated due to M_ZERO. */ 1265182048Sjhb sc->msr_settings = TRUE; 1266182048Sjhb *freqs = fp; 1267182048Sjhb return (0); 1268182048Sjhb} 1269182048Sjhb 1270182048Sjhbstatic void 1271182048Sjhbest_get_id16(uint16_t *id16_p) 1272182048Sjhb{ 1273176649Srpaulo *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1274176649Srpaulo} 1275176649Srpaulo 1276176649Srpaulostatic int 1277176649Srpauloest_set_id16(device_t dev, uint16_t id16, int need_check) 1278176649Srpaulo{ 1279176649Srpaulo uint64_t msr; 1280176649Srpaulo uint16_t new_id16; 1281176649Srpaulo int ret = 0; 1282176649Srpaulo 1283176649Srpaulo /* Read the current register, mask out the old, set the new id. */ 1284176649Srpaulo msr = rdmsr(MSR_PERF_CTL); 1285176649Srpaulo msr = (msr & ~0xffff) | id16; 1286176649Srpaulo wrmsr(MSR_PERF_CTL, msr); 1287176649Srpaulo 1288176649Srpaulo /* Wait a short while for the new setting. XXX Is this necessary? */ 1289176649Srpaulo DELAY(EST_TRANS_LAT); 1290212721Smav 1291176649Srpaulo if (need_check) { 1292176649Srpaulo est_get_id16(&new_id16); 1293212721Smav if (new_id16 != id16) { 1294176649Srpaulo if (bootverbose) 1295212721Smav device_printf(dev, "Invalid id16 (set, cur) " 1296176649Srpaulo "= (%u, %u)\n", id16, new_id16); 1297212721Smav ret = ENXIO; 1298176649Srpaulo } 1299176649Srpaulo } 1300176649Srpaulo return (ret); 1301176649Srpaulo} 1302176649Srpaulo 1303176649Srpaulostatic freq_info * 1304176649Srpauloest_get_current(freq_info *freq_list) 1305176649Srpaulo{ 1306143902Snjl freq_info *f; 1307143902Snjl int i; 1308142140Snjl uint16_t id16; 1309143902Snjl 1310142140Snjl /* 1311142140Snjl * Try a few times to get a valid value. Sometimes, if the CPU 1312142140Snjl * is in the middle of an asynchronous transition (i.e., P4TCC), 1313142140Snjl * we get a temporary invalid result. 1314142140Snjl */ 1315142140Snjl for (i = 0; i < 5; i++) { 1316142140Snjl est_get_id16(&id16); 1317142140Snjl for (f = freq_list; f->id16 != 0; f++) { 1318142140Snjl if (f->id16 == id16) 1319176649Srpaulo return (f); 1320142140Snjl } 1321142140Snjl DELAY(100); 1322142140Snjl } 1323142140Snjl return (NULL); 1324142140Snjl} 1325142140Snjl 1326142140Snjlstatic int 1327142140Snjlest_settings(device_t dev, struct cf_setting *sets, int *count) 1328142140Snjl{ 1329142140Snjl struct est_softc *sc; 1330142140Snjl freq_info *f; 1331142140Snjl int i; 1332142140Snjl 1333143902Snjl sc = device_get_softc(dev); 1334142140Snjl if (*count < EST_MAX_SETTINGS) 1335142140Snjl return (E2BIG); 1336142140Snjl 1337142140Snjl i = 0; 1338142140Snjl for (f = sc->freq_list; f->freq != 0; f++, i++) { 1339142140Snjl sets[i].freq = f->freq; 1340142140Snjl sets[i].volts = f->volts; 1341142394Snjl sets[i].power = f->power; 1342142140Snjl sets[i].lat = EST_TRANS_LAT; 1343142140Snjl sets[i].dev = dev; 1344143902Snjl } 1345142140Snjl *count = i; 1346142140Snjl 1347142140Snjl return (0); 1348142394Snjl} 1349142140Snjl 1350142140Snjlstatic int 1351142140Snjlest_set(device_t dev, const struct cf_setting *set) 1352142140Snjl{ 1353142140Snjl struct est_softc *sc; 1354142140Snjl freq_info *f; 1355142140Snjl 1356142140Snjl /* Find the setting matching the requested one. */ 1357143902Snjl sc = device_get_softc(dev); 1358142140Snjl for (f = sc->freq_list; f->freq != 0; f++) { 1359142140Snjl if (f->freq == set->freq) 1360142140Snjl break; 1361142140Snjl } 1362142140Snjl if (f->freq == 0) 1363142140Snjl return (EINVAL); 1364142140Snjl 1365142140Snjl /* Read the current register, mask out the old, set the new id. */ 1366142140Snjl est_set_id16(dev, f->id16, 0); 1367142140Snjl 1368142140Snjl return (0); 1369176649Srpaulo} 1370142140Snjl 1371142140Snjlstatic int 1372142140Snjlest_get(device_t dev, struct cf_setting *set) 1373142140Snjl{ 1374142140Snjl struct est_softc *sc; 1375142140Snjl freq_info *f; 1376142140Snjl 1377142140Snjl sc = device_get_softc(dev); 1378143902Snjl f = est_get_current(sc->freq_list); 1379142140Snjl if (f == NULL) 1380142140Snjl return (ENXIO); 1381142140Snjl 1382142140Snjl set->freq = f->freq; 1383142140Snjl set->volts = f->volts; 1384142140Snjl set->power = f->power; 1385142140Snjl set->lat = EST_TRANS_LAT; 1386142140Snjl set->dev = dev; 1387143902Snjl return (0); 1388142140Snjl} 1389142140Snjl 1390142140Snjlstatic int 1391142140Snjlest_type(device_t dev, int *type) 1392142140Snjl{ 1393142140Snjl 1394142140Snjl if (type == NULL) 1395142140Snjl return (EINVAL); 1396142140Snjl 1397142140Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 1398142140Snjl return (0); 1399142140Snjl} 1400142140Snjl