est.c revision 193530
1142140Snjl/*- 2142140Snjl * Copyright (c) 2004 Colin Percival 3142140Snjl * Copyright (c) 2005 Nate Lawson 4142140Snjl * All rights reserved. 5142140Snjl * 6142140Snjl * Redistribution and use in source and binary forms, with or without 7142140Snjl * modification, are permitted providing that the following conditions 8142140Snjl * are met: 9142140Snjl * 1. Redistributions of source code must retain the above copyright 10142140Snjl * notice, this list of conditions and the following disclaimer. 11142140Snjl * 2. Redistributions in binary form must reproduce the above copyright 12142140Snjl * notice, this list of conditions and the following disclaimer in the 13142140Snjl * documentation and/or other materials provided with the distribution. 14142140Snjl * 15142140Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16142140Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17142140Snjl * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18142140Snjl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19142140Snjl * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20142140Snjl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21142140Snjl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22142140Snjl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23142140Snjl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24142140Snjl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25142140Snjl * POSSIBILITY OF SUCH DAMAGE. 26142140Snjl */ 27142140Snjl 28142140Snjl#include <sys/cdefs.h> 29142140Snjl__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 193530 2009-06-05 18:44:36Z jkim $"); 30142140Snjl 31142140Snjl#include <sys/param.h> 32142140Snjl#include <sys/bus.h> 33142140Snjl#include <sys/cpu.h> 34142140Snjl#include <sys/kernel.h> 35143902Snjl#include <sys/malloc.h> 36142140Snjl#include <sys/module.h> 37142140Snjl#include <sys/smp.h> 38142140Snjl#include <sys/systm.h> 39142140Snjl 40142140Snjl#include "cpufreq_if.h" 41182048Sjhb#include <machine/clock.h> 42185341Sjkim#include <machine/cputypes.h> 43142140Snjl#include <machine/md_var.h> 44177040Sjhb#include <machine/specialreg.h> 45142140Snjl 46193530Sjkim#include <contrib/dev/acpica/include/acpi.h> 47193530Sjkim 48144630Snjl#include <dev/acpica/acpivar.h> 49144630Snjl#include "acpi_if.h" 50144630Snjl 51142140Snjl/* Status/control registers (from the IA-32 System Programming Guide). */ 52142140Snjl#define MSR_PERF_STATUS 0x198 53142140Snjl#define MSR_PERF_CTL 0x199 54142140Snjl 55142140Snjl/* Register and bit for enabling SpeedStep. */ 56142140Snjl#define MSR_MISC_ENABLE 0x1a0 57142140Snjl#define MSR_SS_ENABLE (1<<16) 58142140Snjl 59142140Snjl/* Frequency and MSR control values. */ 60142140Snjltypedef struct { 61142140Snjl uint16_t freq; 62142140Snjl uint16_t volts; 63142140Snjl uint16_t id16; 64143902Snjl int power; 65142140Snjl} freq_info; 66142140Snjl 67142140Snjl/* Identifying characteristics of a processor and supported frequencies. */ 68142140Snjltypedef struct { 69185341Sjkim const u_int vendor_id; 70142140Snjl uint32_t id32; 71143902Snjl freq_info *freqtab; 72142140Snjl} cpu_info; 73142140Snjl 74142140Snjlstruct est_softc { 75143902Snjl device_t dev; 76143902Snjl int acpi_settings; 77182048Sjhb int msr_settings; 78143902Snjl freq_info *freq_list; 79142140Snjl}; 80142140Snjl 81142140Snjl/* Convert MHz and mV into IDs for passing to the MSR. */ 82142140Snjl#define ID16(MHz, mV, bus_clk) \ 83142140Snjl (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 84142140Snjl#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 85142140Snjl ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 86142140Snjl 87142140Snjl/* Format for storing IDs in our table. */ 88158446Snjl#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 89158446Snjl { MHz, mV, ID16(MHz, mV, bus_clk), mW } 90142140Snjl#define FREQ_INFO(MHz, mV, bus_clk) \ 91158446Snjl FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 92142140Snjl#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 93185341Sjkim { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 94158446Snjl#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 95185341Sjkim { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 96142140Snjl 97182201Sjhbstatic int msr_info_enabled = 0; 98182201SjhbTUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 99142140Snjl 100142140Snjl/* Default bus clock value for Centrino processors. */ 101142140Snjl#define INTEL_BUS_CLK 100 102142140Snjl 103142140Snjl/* XXX Update this if new CPUs have more settings. */ 104142140Snjl#define EST_MAX_SETTINGS 10 105142140SnjlCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 106142140Snjl 107142140Snjl/* Estimate in microseconds of latency for performing a transition. */ 108177296Sphk#define EST_TRANS_LAT 1000 109142140Snjl 110142140Snjl/* 111142140Snjl * Frequency (MHz) and voltage (mV) settings. Data from the 112142140Snjl * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 113142140Snjl * 114143902Snjl * Dothan processors have multiple VID#s with different settings for 115143902Snjl * each VID#. Since we can't uniquely identify this info 116142140Snjl * without undisclosed methods from Intel, we can't support newer 117142140Snjl * processors with this table method. If ACPI Px states are supported, 118143902Snjl * we get info from them. 119142140Snjl */ 120143902Snjlstatic freq_info PM17_130[] = { 121142140Snjl /* 130nm 1.70GHz Pentium M */ 122142140Snjl FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 123142140Snjl FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 124142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 125142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 126142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 127142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 128142140Snjl FREQ_INFO( 0, 0, 1), 129142140Snjl}; 130143902Snjlstatic freq_info PM16_130[] = { 131142140Snjl /* 130nm 1.60GHz Pentium M */ 132142140Snjl FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 133142140Snjl FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 134142140Snjl FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 135142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 136142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 137142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 138142140Snjl FREQ_INFO( 0, 0, 1), 139142140Snjl}; 140143902Snjlstatic freq_info PM15_130[] = { 141142140Snjl /* 130nm 1.50GHz Pentium M */ 142142140Snjl FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 143142140Snjl FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 144142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 145142140Snjl FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 146142140Snjl FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 147142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 148142140Snjl FREQ_INFO( 0, 0, 1), 149142140Snjl}; 150143902Snjlstatic freq_info PM14_130[] = { 151142140Snjl /* 130nm 1.40GHz Pentium M */ 152142140Snjl FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 153142140Snjl FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 154142140Snjl FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 155142140Snjl FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 156142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 157142140Snjl FREQ_INFO( 0, 0, 1), 158142140Snjl}; 159143902Snjlstatic freq_info PM13_130[] = { 160142140Snjl /* 130nm 1.30GHz Pentium M */ 161142140Snjl FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 162142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 163142140Snjl FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 164142140Snjl FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 165142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 166142140Snjl FREQ_INFO( 0, 0, 1), 167142140Snjl}; 168143902Snjlstatic freq_info PM13_LV_130[] = { 169142140Snjl /* 130nm 1.30GHz Low Voltage Pentium M */ 170142140Snjl FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 171142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 172142140Snjl FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 173142140Snjl FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 174142140Snjl FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 175142140Snjl FREQ_INFO( 800, 988, INTEL_BUS_CLK), 176142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 177142140Snjl FREQ_INFO( 0, 0, 1), 178142140Snjl}; 179143902Snjlstatic freq_info PM12_LV_130[] = { 180142140Snjl /* 130 nm 1.20GHz Low Voltage Pentium M */ 181142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 182142140Snjl FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 183142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 184142140Snjl FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 185142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 186142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 187142140Snjl FREQ_INFO( 0, 0, 1), 188142140Snjl}; 189143902Snjlstatic freq_info PM11_LV_130[] = { 190142140Snjl /* 130 nm 1.10GHz Low Voltage Pentium M */ 191142140Snjl FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 192142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 193142140Snjl FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 194142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 195142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 196142140Snjl FREQ_INFO( 0, 0, 1), 197142140Snjl}; 198143902Snjlstatic freq_info PM11_ULV_130[] = { 199142140Snjl /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 200142140Snjl FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 201142140Snjl FREQ_INFO(1000, 988, INTEL_BUS_CLK), 202142140Snjl FREQ_INFO( 900, 972, INTEL_BUS_CLK), 203142140Snjl FREQ_INFO( 800, 956, INTEL_BUS_CLK), 204142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 205142140Snjl FREQ_INFO( 0, 0, 1), 206142140Snjl}; 207143902Snjlstatic freq_info PM10_ULV_130[] = { 208142140Snjl /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 209142140Snjl FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 210142140Snjl FREQ_INFO( 900, 988, INTEL_BUS_CLK), 211142140Snjl FREQ_INFO( 800, 972, INTEL_BUS_CLK), 212142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 213142140Snjl FREQ_INFO( 0, 0, 1), 214142140Snjl}; 215142140Snjl 216142140Snjl/* 217142140Snjl * Data from "Intel Pentium M Processor on 90nm Process with 218142140Snjl * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 219142140Snjl */ 220143902Snjlstatic freq_info PM_765A_90[] = { 221142140Snjl /* 90 nm 2.10GHz Pentium M, VID #A */ 222142140Snjl FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 223142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 224142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 225142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 226142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 227142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 228142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 229142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 230142140Snjl FREQ_INFO( 0, 0, 1), 231142140Snjl}; 232143902Snjlstatic freq_info PM_765B_90[] = { 233142140Snjl /* 90 nm 2.10GHz Pentium M, VID #B */ 234142140Snjl FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 235142140Snjl FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 236142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 237142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 238142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 239142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 240142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 241142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 242142140Snjl FREQ_INFO( 0, 0, 1), 243142140Snjl}; 244143902Snjlstatic freq_info PM_765C_90[] = { 245142140Snjl /* 90 nm 2.10GHz Pentium M, VID #C */ 246142140Snjl FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 247142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 248142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 249142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 250142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 251142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 252142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 253142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 254142140Snjl FREQ_INFO( 0, 0, 1), 255142140Snjl}; 256143902Snjlstatic freq_info PM_765E_90[] = { 257142140Snjl /* 90 nm 2.10GHz Pentium M, VID #E */ 258142140Snjl FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 259142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 260142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 261142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 262142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 263142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 264142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 265142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 266142140Snjl FREQ_INFO( 0, 0, 1), 267142140Snjl}; 268143902Snjlstatic freq_info PM_755A_90[] = { 269142140Snjl /* 90 nm 2.00GHz Pentium M, VID #A */ 270142140Snjl FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 271142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 272142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 273142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 274142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 275142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 276142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 277142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 278142140Snjl FREQ_INFO( 0, 0, 1), 279142140Snjl}; 280143902Snjlstatic freq_info PM_755B_90[] = { 281142140Snjl /* 90 nm 2.00GHz Pentium M, VID #B */ 282142140Snjl FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 283142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 284142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 285142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 286142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 287142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 288142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 289142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 290142140Snjl FREQ_INFO( 0, 0, 1), 291142140Snjl}; 292143902Snjlstatic freq_info PM_755C_90[] = { 293142140Snjl /* 90 nm 2.00GHz Pentium M, VID #C */ 294142140Snjl FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 295142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 296142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 297142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 298142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 299142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 300142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 301142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 302142140Snjl FREQ_INFO( 0, 0, 1), 303142140Snjl}; 304143902Snjlstatic freq_info PM_755D_90[] = { 305142140Snjl /* 90 nm 2.00GHz Pentium M, VID #D */ 306142140Snjl FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 307142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 308142140Snjl FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 309142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 310142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 311142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 312142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 313142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 314142140Snjl FREQ_INFO( 0, 0, 1), 315142140Snjl}; 316143902Snjlstatic freq_info PM_745A_90[] = { 317142140Snjl /* 90 nm 1.80GHz Pentium M, VID #A */ 318142140Snjl FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 319142140Snjl FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 320142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 321142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 322142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 323142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 324142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 325142140Snjl FREQ_INFO( 0, 0, 1), 326142140Snjl}; 327143902Snjlstatic freq_info PM_745B_90[] = { 328142140Snjl /* 90 nm 1.80GHz Pentium M, VID #B */ 329142140Snjl FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 330142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 331142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 332142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 333142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 334142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 335142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 336142140Snjl FREQ_INFO( 0, 0, 1), 337142140Snjl}; 338143902Snjlstatic freq_info PM_745C_90[] = { 339142140Snjl /* 90 nm 1.80GHz Pentium M, VID #C */ 340142140Snjl FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 341142140Snjl FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 342142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 343142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 344142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 345142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 346142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 347142140Snjl FREQ_INFO( 0, 0, 1), 348142140Snjl}; 349143902Snjlstatic freq_info PM_745D_90[] = { 350142140Snjl /* 90 nm 1.80GHz Pentium M, VID #D */ 351142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 352142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 353142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 354142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 355142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 356142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 357142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 358142140Snjl FREQ_INFO( 0, 0, 1), 359142140Snjl}; 360143902Snjlstatic freq_info PM_735A_90[] = { 361142140Snjl /* 90 nm 1.70GHz Pentium M, VID #A */ 362142140Snjl FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 363142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 364142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 365142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 366142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 367142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 368142140Snjl FREQ_INFO( 0, 0, 1), 369142140Snjl}; 370143902Snjlstatic freq_info PM_735B_90[] = { 371142140Snjl /* 90 nm 1.70GHz Pentium M, VID #B */ 372142140Snjl FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 373142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 374142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 375142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 376142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 377142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 378142140Snjl FREQ_INFO( 0, 0, 1), 379142140Snjl}; 380143902Snjlstatic freq_info PM_735C_90[] = { 381142140Snjl /* 90 nm 1.70GHz Pentium M, VID #C */ 382142140Snjl FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 383142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 384142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 385142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 386142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 387142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 388142140Snjl FREQ_INFO( 0, 0, 1), 389142140Snjl}; 390143902Snjlstatic freq_info PM_735D_90[] = { 391142140Snjl /* 90 nm 1.70GHz Pentium M, VID #D */ 392142140Snjl FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 393142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 394142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 395142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 396142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 397142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 398142140Snjl FREQ_INFO( 0, 0, 1), 399142140Snjl}; 400143902Snjlstatic freq_info PM_725A_90[] = { 401142140Snjl /* 90 nm 1.60GHz Pentium M, VID #A */ 402142140Snjl FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 403142140Snjl FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 404142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 405142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 406142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 407142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 408142140Snjl FREQ_INFO( 0, 0, 1), 409142140Snjl}; 410143902Snjlstatic freq_info PM_725B_90[] = { 411142140Snjl /* 90 nm 1.60GHz Pentium M, VID #B */ 412142140Snjl FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 413142140Snjl FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 414142140Snjl FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 415142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 416142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 417142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 418142140Snjl FREQ_INFO( 0, 0, 1), 419142140Snjl}; 420143902Snjlstatic freq_info PM_725C_90[] = { 421142140Snjl /* 90 nm 1.60GHz Pentium M, VID #C */ 422142140Snjl FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 423142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 424142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 425142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 426142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 427142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 428142140Snjl FREQ_INFO( 0, 0, 1), 429142140Snjl}; 430143902Snjlstatic freq_info PM_725D_90[] = { 431142140Snjl /* 90 nm 1.60GHz Pentium M, VID #D */ 432142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 433142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 434142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 435142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 436142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 437142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 438142140Snjl FREQ_INFO( 0, 0, 1), 439142140Snjl}; 440143902Snjlstatic freq_info PM_715A_90[] = { 441142140Snjl /* 90 nm 1.50GHz Pentium M, VID #A */ 442142140Snjl FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 443142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 444142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 445142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 446142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 447142140Snjl FREQ_INFO( 0, 0, 1), 448142140Snjl}; 449143902Snjlstatic freq_info PM_715B_90[] = { 450142140Snjl /* 90 nm 1.50GHz Pentium M, VID #B */ 451142140Snjl FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 452142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 453142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 454142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 455142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 456142140Snjl FREQ_INFO( 0, 0, 1), 457142140Snjl}; 458143902Snjlstatic freq_info PM_715C_90[] = { 459142140Snjl /* 90 nm 1.50GHz Pentium M, VID #C */ 460142140Snjl FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 461142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 462142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 463142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 464142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 465142140Snjl FREQ_INFO( 0, 0, 1), 466142140Snjl}; 467143902Snjlstatic freq_info PM_715D_90[] = { 468142140Snjl /* 90 nm 1.50GHz Pentium M, VID #D */ 469142140Snjl FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 470142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 471142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 472142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 473142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 474142140Snjl FREQ_INFO( 0, 0, 1), 475142140Snjl}; 476155996Scpercivastatic freq_info PM_778_90[] = { 477155996Scperciva /* 90 nm 1.60GHz Low Voltage Pentium M */ 478155996Scperciva FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 479155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 480155996Scperciva FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 481155996Scperciva FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 482155996Scperciva FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 483155996Scperciva FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 484155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 485155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 486155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 487155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 488155996Scperciva FREQ_INFO( 0, 0, 1), 489155996Scperciva}; 490155996Scpercivastatic freq_info PM_758_90[] = { 491155996Scperciva /* 90 nm 1.50GHz Low Voltage Pentium M */ 492155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 493155996Scperciva FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 494155996Scperciva FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 495155996Scperciva FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 496155996Scperciva FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 497155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 498155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 499155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 500155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 501155996Scperciva FREQ_INFO( 0, 0, 1), 502155996Scperciva}; 503143902Snjlstatic freq_info PM_738_90[] = { 504142140Snjl /* 90 nm 1.40GHz Low Voltage Pentium M */ 505142140Snjl FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 506142140Snjl FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 507142140Snjl FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 508142140Snjl FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 509142140Snjl FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 510142140Snjl FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 511142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 512142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 513142140Snjl FREQ_INFO( 0, 0, 1), 514142140Snjl}; 515155996Scpercivastatic freq_info PM_773G_90[] = { 516155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 517155996Scperciva FREQ_INFO(1300, 956, INTEL_BUS_CLK), 518155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 519155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 520155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 521155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 522155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 523155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 524155996Scperciva}; 525155996Scpercivastatic freq_info PM_773H_90[] = { 526155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 527155996Scperciva FREQ_INFO(1300, 940, INTEL_BUS_CLK), 528155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 529155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 530155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 531155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 532155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 533155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 534155996Scperciva}; 535155996Scpercivastatic freq_info PM_773I_90[] = { 536155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 537155996Scperciva FREQ_INFO(1300, 924, INTEL_BUS_CLK), 538155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 539155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 540155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 541155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 542155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 543155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 544155996Scperciva}; 545155996Scpercivastatic freq_info PM_773J_90[] = { 546155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 547155996Scperciva FREQ_INFO(1300, 908, INTEL_BUS_CLK), 548155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 549155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 550155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 551155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 552155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 553155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 554155996Scperciva}; 555155996Scpercivastatic freq_info PM_773K_90[] = { 556155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 557155996Scperciva FREQ_INFO(1300, 892, INTEL_BUS_CLK), 558155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 559155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 560155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 561155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 562155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 563155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 564155996Scperciva}; 565155996Scpercivastatic freq_info PM_773L_90[] = { 566155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 567155996Scperciva FREQ_INFO(1300, 876, INTEL_BUS_CLK), 568155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 569155996Scperciva FREQ_INFO(1100, 860, INTEL_BUS_CLK), 570155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 571155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 572155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 573155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 574155996Scperciva}; 575155996Scpercivastatic freq_info PM_753G_90[] = { 576155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 577155996Scperciva FREQ_INFO(1200, 956, INTEL_BUS_CLK), 578155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 579155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 580155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 581155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 582155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 583155996Scperciva}; 584155996Scpercivastatic freq_info PM_753H_90[] = { 585155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 586155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 587155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 588155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 589155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 590155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 591155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 592155996Scperciva}; 593155996Scpercivastatic freq_info PM_753I_90[] = { 594155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 595155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 596155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 597155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 598155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 599155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 600155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 601155996Scperciva}; 602155996Scpercivastatic freq_info PM_753J_90[] = { 603155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 604155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 605155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 606155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 607155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 608155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 609155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 610155996Scperciva}; 611155996Scpercivastatic freq_info PM_753K_90[] = { 612155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 613155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 614155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 615155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 616155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 617155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 618155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 619155996Scperciva}; 620155996Scpercivastatic freq_info PM_753L_90[] = { 621155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 622155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 623155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 624155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 625155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 626155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 627155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 628155996Scperciva}; 629155996Scperciva 630155996Scpercivastatic freq_info PM_733JG_90[] = { 631155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 632155996Scperciva FREQ_INFO(1100, 956, INTEL_BUS_CLK), 633155996Scperciva FREQ_INFO(1000, 940, INTEL_BUS_CLK), 634155996Scperciva FREQ_INFO( 900, 908, INTEL_BUS_CLK), 635155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 636155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 637155996Scperciva}; 638155996Scpercivastatic freq_info PM_733JH_90[] = { 639155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 640155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 641155996Scperciva FREQ_INFO(1000, 924, INTEL_BUS_CLK), 642155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 643155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 644155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 645155996Scperciva}; 646155996Scpercivastatic freq_info PM_733JI_90[] = { 647155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 648155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 649155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 650155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 651155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 652155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 653155996Scperciva}; 654155996Scpercivastatic freq_info PM_733JJ_90[] = { 655155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 656155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 657155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 658155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 659155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 660155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 661155996Scperciva}; 662155996Scpercivastatic freq_info PM_733JK_90[] = { 663155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 664155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 665155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 666155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 667155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 668155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 669155996Scperciva}; 670155996Scpercivastatic freq_info PM_733JL_90[] = { 671155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 672155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 673155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 674155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 675155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 676155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 677155996Scperciva}; 678143902Snjlstatic freq_info PM_733_90[] = { 679142140Snjl /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 680142140Snjl FREQ_INFO(1100, 940, INTEL_BUS_CLK), 681142140Snjl FREQ_INFO(1000, 924, INTEL_BUS_CLK), 682142140Snjl FREQ_INFO( 900, 892, INTEL_BUS_CLK), 683142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 684142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 685142140Snjl FREQ_INFO( 0, 0, 1), 686142140Snjl}; 687143902Snjlstatic freq_info PM_723_90[] = { 688142140Snjl /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 689142140Snjl FREQ_INFO(1000, 940, INTEL_BUS_CLK), 690142140Snjl FREQ_INFO( 900, 908, INTEL_BUS_CLK), 691142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 692142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 693142140Snjl FREQ_INFO( 0, 0, 1), 694142140Snjl}; 695142140Snjl 696158446Snjl/* 697158446Snjl * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 698158446Snjl * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 699158446Snjl */ 700158446Snjlstatic freq_info C7M_795[] = { 701158446Snjl /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 702158446Snjl FREQ_INFO_PWR(2000, 1148, 133, 20000), 703158446Snjl FREQ_INFO_PWR(1867, 1132, 133, 18000), 704158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 705158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 706158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 707158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 708158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 709158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 710158446Snjl FREQ_INFO(0, 0, 1), 711158446Snjl}; 712158446Snjlstatic freq_info C7M_785[] = { 713158446Snjl /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 714158446Snjl FREQ_INFO_PWR(1867, 1148, 133, 18000), 715158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 716158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 717158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 718158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 719158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 720158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 721158446Snjl FREQ_INFO(0, 0, 1), 722158446Snjl}; 723158446Snjlstatic freq_info C7M_765[] = { 724158446Snjl /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 725158446Snjl FREQ_INFO_PWR(1600, 1084, 133, 15000), 726158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 727158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 728158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 729158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 730158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 731158446Snjl FREQ_INFO(0, 0, 1), 732158446Snjl}; 733158446Snjl 734158446Snjlstatic freq_info C7M_794[] = { 735158446Snjl /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 736158446Snjl FREQ_INFO_PWR(2000, 1148, 100, 20000), 737158446Snjl FREQ_INFO_PWR(1800, 1132, 100, 18000), 738158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 739158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 740158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 741158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 742158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 743158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 744158446Snjl FREQ_INFO(0, 0, 1), 745158446Snjl}; 746158446Snjlstatic freq_info C7M_784[] = { 747158446Snjl /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 748158446Snjl FREQ_INFO_PWR(1800, 1148, 100, 18000), 749158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 750158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 751158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 752158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 753158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 754158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 755158446Snjl FREQ_INFO(0, 0, 1), 756158446Snjl}; 757158446Snjlstatic freq_info C7M_764[] = { 758158446Snjl /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 759158446Snjl FREQ_INFO_PWR(1600, 1084, 100, 15000), 760158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 761158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 762158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 763158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 764158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 765158446Snjl FREQ_INFO(0, 0, 1), 766158446Snjl}; 767158446Snjlstatic freq_info C7M_754[] = { 768158446Snjl /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 769158446Snjl FREQ_INFO_PWR(1500, 1004, 100, 12000), 770158446Snjl FREQ_INFO_PWR(1400, 988, 100, 11000), 771158446Snjl FREQ_INFO_PWR(1000, 940, 100, 9000), 772158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 773158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 774158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 775158446Snjl FREQ_INFO(0, 0, 1), 776158446Snjl}; 777158446Snjlstatic freq_info C7M_771[] = { 778158446Snjl /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 779158446Snjl FREQ_INFO_PWR(1200, 860, 100, 7000), 780158446Snjl FREQ_INFO_PWR(1000, 860, 100, 6000), 781158446Snjl FREQ_INFO_PWR( 800, 844, 100, 5500), 782158446Snjl FREQ_INFO_PWR( 600, 844, 100, 5000), 783158446Snjl FREQ_INFO_PWR( 400, 844, 100, 4000), 784158446Snjl FREQ_INFO(0, 0, 1), 785158446Snjl}; 786158446Snjl 787158446Snjlstatic freq_info C7M_775_ULV[] = { 788158446Snjl /* 1.50GHz Centaur C7-M ULV */ 789158446Snjl FREQ_INFO_PWR(1500, 956, 100, 7500), 790158446Snjl FREQ_INFO_PWR(1400, 940, 100, 6000), 791158446Snjl FREQ_INFO_PWR(1000, 860, 100, 5000), 792158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 793158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 794158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 795158446Snjl FREQ_INFO(0, 0, 1), 796158446Snjl}; 797158446Snjlstatic freq_info C7M_772_ULV[] = { 798158446Snjl /* 1.20GHz Centaur C7-M ULV */ 799158446Snjl FREQ_INFO_PWR(1200, 844, 100, 5000), 800158446Snjl FREQ_INFO_PWR(1000, 844, 100, 4000), 801158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 802158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 803158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 804158446Snjl FREQ_INFO(0, 0, 1), 805158446Snjl}; 806158446Snjlstatic freq_info C7M_779_ULV[] = { 807158446Snjl /* 1.00GHz Centaur C7-M ULV */ 808158446Snjl FREQ_INFO_PWR(1000, 796, 100, 3500), 809158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 810158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 811158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 812158446Snjl FREQ_INFO(0, 0, 1), 813158446Snjl}; 814158446Snjlstatic freq_info C7M_770_ULV[] = { 815158446Snjl /* 1.00GHz Centaur C7-M ULV */ 816158446Snjl FREQ_INFO_PWR(1000, 844, 100, 5000), 817158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 818158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 819158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 820158446Snjl FREQ_INFO(0, 0, 1), 821158446Snjl}; 822158446Snjl 823143902Snjlstatic cpu_info ESTprocs[] = { 824142140Snjl INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 825142140Snjl INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 826142140Snjl INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 827142140Snjl INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 828142140Snjl INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 829142140Snjl INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 830142140Snjl INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 831142140Snjl INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 832142140Snjl INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 833142140Snjl INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 834142140Snjl INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 835142140Snjl INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 836142140Snjl INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 837142140Snjl INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 838142140Snjl INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 839142140Snjl INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 840142140Snjl INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 841142140Snjl INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 842142140Snjl INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 843142140Snjl INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 844142140Snjl INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 845142140Snjl INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 846142140Snjl INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 847142140Snjl INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 848142140Snjl INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 849142140Snjl INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 850142140Snjl INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 851142140Snjl INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 852142140Snjl INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 853142140Snjl INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 854142140Snjl INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 855142140Snjl INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 856142140Snjl INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 857142140Snjl INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 858155996Scperciva INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 859155996Scperciva INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 860142140Snjl INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 861155996Scperciva INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 862155996Scperciva INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 863155996Scperciva INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 864155996Scperciva INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 865155996Scperciva INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 866155996Scperciva INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 867155996Scperciva INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 868155996Scperciva INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 869155996Scperciva INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 870155996Scperciva INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 871155996Scperciva INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 872155996Scperciva INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 873155996Scperciva INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 874155996Scperciva INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 875155996Scperciva INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 876155996Scperciva INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 877155996Scperciva INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 878155996Scperciva INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 879142140Snjl INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 880142140Snjl INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 881158446Snjl 882158446Snjl CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 883158446Snjl CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 884158446Snjl CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 885158446Snjl CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 886158446Snjl CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 887158446Snjl CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 888158446Snjl CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 889158446Snjl CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 890158446Snjl CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 891158446Snjl CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 892158446Snjl CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 893158446Snjl CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 894185341Sjkim { 0, 0, NULL }, 895142140Snjl}; 896142140Snjl 897142140Snjlstatic void est_identify(driver_t *driver, device_t parent); 898144630Snjlstatic int est_features(driver_t *driver, u_int *features); 899142140Snjlstatic int est_probe(device_t parent); 900142140Snjlstatic int est_attach(device_t parent); 901142140Snjlstatic int est_detach(device_t parent); 902143902Snjlstatic int est_get_info(device_t dev); 903143902Snjlstatic int est_acpi_info(device_t dev, freq_info **freqs); 904158446Snjlstatic int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 905182048Sjhbstatic int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 906143902Snjlstatic freq_info *est_get_current(freq_info *freq_list); 907142140Snjlstatic int est_settings(device_t dev, struct cf_setting *sets, int *count); 908142140Snjlstatic int est_set(device_t dev, const struct cf_setting *set); 909142140Snjlstatic int est_get(device_t dev, struct cf_setting *set); 910142140Snjlstatic int est_type(device_t dev, int *type); 911176649Srpaulostatic int est_set_id16(device_t dev, uint16_t id16, int need_check); 912176649Srpaulostatic void est_get_id16(uint16_t *id16_p); 913142140Snjl 914142140Snjlstatic device_method_t est_methods[] = { 915142140Snjl /* Device interface */ 916142140Snjl DEVMETHOD(device_identify, est_identify), 917142140Snjl DEVMETHOD(device_probe, est_probe), 918142140Snjl DEVMETHOD(device_attach, est_attach), 919142140Snjl DEVMETHOD(device_detach, est_detach), 920142140Snjl 921142140Snjl /* cpufreq interface */ 922142140Snjl DEVMETHOD(cpufreq_drv_set, est_set), 923142140Snjl DEVMETHOD(cpufreq_drv_get, est_get), 924142140Snjl DEVMETHOD(cpufreq_drv_type, est_type), 925142140Snjl DEVMETHOD(cpufreq_drv_settings, est_settings), 926144630Snjl 927144630Snjl /* ACPI interface */ 928144630Snjl DEVMETHOD(acpi_get_features, est_features), 929144630Snjl 930142140Snjl {0, 0} 931142140Snjl}; 932142140Snjl 933142140Snjlstatic driver_t est_driver = { 934142140Snjl "est", 935142140Snjl est_methods, 936142140Snjl sizeof(struct est_softc), 937142140Snjl}; 938142140Snjl 939142140Snjlstatic devclass_t est_devclass; 940142140SnjlDRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 941142140Snjl 942144630Snjlstatic int 943144630Snjlest_features(driver_t *driver, u_int *features) 944144630Snjl{ 945144630Snjl 946144630Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 947144630Snjl *features = ACPI_CAP_PERF_MSRS; 948144630Snjl return (0); 949144630Snjl} 950144630Snjl 951142140Snjlstatic void 952142140Snjlest_identify(driver_t *driver, device_t parent) 953142140Snjl{ 954144630Snjl device_t child; 955142140Snjl 956142140Snjl /* Make sure we're not being doubly invoked. */ 957142140Snjl if (device_find_child(parent, "est", -1) != NULL) 958142140Snjl return; 959142140Snjl 960142140Snjl /* Check that CPUID is supported and the vendor is Intel.*/ 961185341Sjkim if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 962185341Sjkim cpu_vendor_id != CPU_VENDOR_CENTAUR)) 963142140Snjl return; 964142140Snjl 965158446Snjl /* 966177040Sjhb * Check if the CPU supports EST. 967158446Snjl */ 968177040Sjhb if (!(cpu_feature2 & CPUID2_EST)) 969142140Snjl return; 970142140Snjl 971142625Snjl /* 972142625Snjl * We add a child for each CPU since settings must be performed 973142625Snjl * on each CPU in the SMP case. 974142625Snjl */ 975181691Sjhb child = BUS_ADD_CHILD(parent, 10, "est", -1); 976144630Snjl if (child == NULL) 977142140Snjl device_printf(parent, "add est child failed\n"); 978142140Snjl} 979142140Snjl 980142140Snjlstatic int 981142140Snjlest_probe(device_t dev) 982142140Snjl{ 983142140Snjl device_t perf_dev; 984142140Snjl uint64_t msr; 985142140Snjl int error, type; 986142203Snjl 987142203Snjl if (resource_disabled("est", 0)) 988142203Snjl return (ENXIO); 989142140Snjl 990142140Snjl /* 991142140Snjl * If the ACPI perf driver has attached and is not just offering 992142140Snjl * info, let it manage things. 993142140Snjl */ 994142140Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 995142140Snjl if (perf_dev && device_is_attached(perf_dev)) { 996142140Snjl error = CPUFREQ_DRV_TYPE(perf_dev, &type); 997142140Snjl if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 998142140Snjl return (ENXIO); 999142140Snjl } 1000142140Snjl 1001142140Snjl /* Attempt to enable SpeedStep if not currently enabled. */ 1002142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1003142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1004142140Snjl wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1005143902Snjl if (bootverbose) 1006143902Snjl device_printf(dev, "enabling SpeedStep\n"); 1007142140Snjl 1008142140Snjl /* Check if the enable failed. */ 1009142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1010142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1011142140Snjl device_printf(dev, "failed to enable SpeedStep\n"); 1012142140Snjl return (ENXIO); 1013142140Snjl } 1014142140Snjl } 1015142140Snjl 1016142140Snjl device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1017142140Snjl return (0); 1018142140Snjl} 1019142140Snjl 1020142140Snjlstatic int 1021142140Snjlest_attach(device_t dev) 1022142140Snjl{ 1023142140Snjl struct est_softc *sc; 1024142140Snjl 1025142140Snjl sc = device_get_softc(dev); 1026142140Snjl sc->dev = dev; 1027143902Snjl 1028143902Snjl /* Check CPU for supported settings. */ 1029143902Snjl if (est_get_info(dev)) 1030143902Snjl return (ENXIO); 1031143902Snjl 1032142140Snjl cpufreq_register(dev); 1033142140Snjl return (0); 1034142140Snjl} 1035142140Snjl 1036142140Snjlstatic int 1037142140Snjlest_detach(device_t dev) 1038142140Snjl{ 1039143902Snjl struct est_softc *sc; 1040182908Sjhb int error; 1041143902Snjl 1042182908Sjhb error = cpufreq_unregister(dev); 1043182908Sjhb if (error) 1044182908Sjhb return (error); 1045182908Sjhb 1046143902Snjl sc = device_get_softc(dev); 1047182048Sjhb if (sc->acpi_settings || sc->msr_settings) 1048143902Snjl free(sc->freq_list, M_DEVBUF); 1049182908Sjhb return (0); 1050142140Snjl} 1051142140Snjl 1052143902Snjl/* 1053143902Snjl * Probe for supported CPU settings. First, check our static table of 1054143902Snjl * settings. If no match, try using the ones offered by acpi_perf 1055143902Snjl * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1056143902Snjl * series) export both legacy SMM IO-based access and direct MSR access 1057143902Snjl * but the direct access specifies invalid values for _PSS. 1058143902Snjl */ 1059142140Snjlstatic int 1060143902Snjlest_get_info(device_t dev) 1061142140Snjl{ 1062143902Snjl struct est_softc *sc; 1063143902Snjl uint64_t msr; 1064143902Snjl int error; 1065143902Snjl 1066143902Snjl sc = device_get_softc(dev); 1067143902Snjl msr = rdmsr(MSR_PERF_STATUS); 1068158446Snjl error = est_table_info(dev, msr, &sc->freq_list); 1069143902Snjl if (error) 1070143902Snjl error = est_acpi_info(dev, &sc->freq_list); 1071182048Sjhb if (error) 1072182048Sjhb error = est_msr_info(dev, msr, &sc->freq_list); 1073143902Snjl 1074143902Snjl if (error) { 1075143902Snjl printf( 1076143902Snjl "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1077148583Scperciva "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1078143902Snjl return (ENXIO); 1079143902Snjl } 1080143902Snjl 1081143902Snjl return (0); 1082143902Snjl} 1083143902Snjl 1084143902Snjlstatic int 1085143902Snjlest_acpi_info(device_t dev, freq_info **freqs) 1086143902Snjl{ 1087143902Snjl struct est_softc *sc; 1088143902Snjl struct cf_setting *sets; 1089143902Snjl freq_info *table; 1090143902Snjl device_t perf_dev; 1091179445Sjhb int count, error, i, j; 1092179445Sjhb uint16_t saved_id16; 1093143902Snjl 1094143902Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1095143902Snjl if (perf_dev == NULL || !device_is_attached(perf_dev)) 1096143902Snjl return (ENXIO); 1097143902Snjl 1098143902Snjl /* Fetch settings from acpi_perf. */ 1099143902Snjl sc = device_get_softc(dev); 1100143902Snjl table = NULL; 1101143902Snjl sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1102143902Snjl if (sets == NULL) 1103143902Snjl return (ENOMEM); 1104176714Sgibbs count = MAX_SETTINGS; 1105143902Snjl error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1106143902Snjl if (error) 1107143902Snjl goto out; 1108143902Snjl 1109143902Snjl /* Parse settings into our local table format. */ 1110144881Snjl table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1111143902Snjl if (table == NULL) { 1112143902Snjl error = ENOMEM; 1113143902Snjl goto out; 1114143902Snjl } 1115179445Sjhb est_get_id16(&saved_id16); 1116176649Srpaulo for (i = 0, j = 0; i < count; i++) { 1117143902Snjl /* 1118176649Srpaulo * Confirm id16 value is correct. 1119143902Snjl */ 1120176649Srpaulo if (sets[i].freq > 0) { 1121176649Srpaulo error = est_set_id16(dev, sets[i].spec[0], 1); 1122176649Srpaulo if (error != 0) { 1123176649Srpaulo if (bootverbose) 1124176649Srpaulo device_printf(dev, "Invalid freq %u, " 1125176649Srpaulo "ignored.\n", sets[i].freq); 1126176649Srpaulo } else { 1127176649Srpaulo table[j].freq = sets[i].freq; 1128176649Srpaulo table[j].volts = sets[i].volts; 1129176649Srpaulo table[j].id16 = sets[i].spec[0]; 1130176649Srpaulo table[j].power = sets[i].power; 1131176649Srpaulo ++j; 1132176649Srpaulo } 1133176649Srpaulo } 1134143902Snjl } 1135179445Sjhb /* restore saved setting */ 1136179445Sjhb est_set_id16(dev, saved_id16, 0); 1137143902Snjl 1138144881Snjl /* Mark end of table with a terminator. */ 1139176649Srpaulo bzero(&table[j], sizeof(freq_info)); 1140144881Snjl 1141143902Snjl sc->acpi_settings = TRUE; 1142143902Snjl *freqs = table; 1143143902Snjl error = 0; 1144143902Snjl 1145143902Snjlout: 1146143902Snjl if (sets) 1147143902Snjl free(sets, M_TEMP); 1148143902Snjl if (error && table) 1149143902Snjl free(table, M_DEVBUF); 1150143902Snjl return (error); 1151143902Snjl} 1152143902Snjl 1153143902Snjlstatic int 1154158446Snjlest_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1155143902Snjl{ 1156143902Snjl cpu_info *p; 1157142140Snjl uint32_t id; 1158142140Snjl 1159158446Snjl /* Find a table which matches (vendor, id32). */ 1160142140Snjl id = msr >> 32; 1161142140Snjl for (p = ESTprocs; p->id32 != 0; p++) { 1162185341Sjkim if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1163142140Snjl break; 1164142140Snjl } 1165142140Snjl if (p->id32 == 0) 1166142140Snjl return (EOPNOTSUPP); 1167142140Snjl 1168142140Snjl /* Make sure the current setpoint is valid. */ 1169143902Snjl if (est_get_current(p->freqtab) == NULL) { 1170143902Snjl device_printf(dev, "current setting not found in table\n"); 1171142140Snjl return (EOPNOTSUPP); 1172143902Snjl } 1173142140Snjl 1174142140Snjl *freqs = p->freqtab; 1175142140Snjl return (0); 1176142140Snjl} 1177142140Snjl 1178182048Sjhbstatic int 1179182048Sjhbbus_speed_ok(int bus) 1180182048Sjhb{ 1181182048Sjhb 1182182048Sjhb switch (bus) { 1183182048Sjhb case 100: 1184182048Sjhb case 133: 1185182048Sjhb case 333: 1186182048Sjhb return (1); 1187182048Sjhb default: 1188182048Sjhb return (0); 1189182048Sjhb } 1190182048Sjhb} 1191182048Sjhb 1192182048Sjhb/* 1193182048Sjhb * Flesh out a simple rate table containing the high and low frequencies 1194182048Sjhb * based on the current clock speed and the upper 32 bits of the MSR. 1195182048Sjhb */ 1196182048Sjhbstatic int 1197182048Sjhbest_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1198182048Sjhb{ 1199182048Sjhb struct est_softc *sc; 1200182048Sjhb freq_info *fp; 1201182048Sjhb int bus, freq, volts; 1202182048Sjhb uint16_t id; 1203182048Sjhb 1204182201Sjhb if (!msr_info_enabled) 1205182201Sjhb return (EOPNOTSUPP); 1206182201Sjhb 1207182048Sjhb /* Figure out the bus clock. */ 1208182048Sjhb freq = tsc_freq / 1000000; 1209182048Sjhb id = msr >> 32; 1210182048Sjhb bus = freq / (id >> 8); 1211182048Sjhb device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1212182048Sjhb if (!bus_speed_ok(bus)) { 1213182048Sjhb /* We may be running on the low frequency. */ 1214182048Sjhb id = msr >> 48; 1215182048Sjhb bus = freq / (id >> 8); 1216182048Sjhb device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1217182048Sjhb if (!bus_speed_ok(bus)) 1218182048Sjhb return (EOPNOTSUPP); 1219182048Sjhb 1220182048Sjhb /* Calculate high frequency. */ 1221182048Sjhb id = msr >> 32; 1222182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1223182048Sjhb } 1224182048Sjhb 1225182048Sjhb /* Fill out a new freq table containing just the high and low freqs. */ 1226182048Sjhb sc = device_get_softc(dev); 1227182048Sjhb fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1228182048Sjhb 1229182048Sjhb /* First, the high frequency. */ 1230182048Sjhb volts = id & 0xff; 1231182048Sjhb if (volts != 0) { 1232182048Sjhb volts <<= 4; 1233182048Sjhb volts += 700; 1234182048Sjhb } 1235182048Sjhb fp[0].freq = freq; 1236182048Sjhb fp[0].volts = volts; 1237182048Sjhb fp[0].id16 = id; 1238182048Sjhb fp[0].power = CPUFREQ_VAL_UNKNOWN; 1239182048Sjhb device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1240182048Sjhb volts); 1241182048Sjhb 1242182048Sjhb /* Second, the low frequency. */ 1243182048Sjhb id = msr >> 48; 1244182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1245182048Sjhb volts = id & 0xff; 1246182048Sjhb if (volts != 0) { 1247182048Sjhb volts <<= 4; 1248182048Sjhb volts += 700; 1249182048Sjhb } 1250182048Sjhb fp[1].freq = freq; 1251182048Sjhb fp[1].volts = volts; 1252182048Sjhb fp[1].id16 = id; 1253182048Sjhb fp[1].power = CPUFREQ_VAL_UNKNOWN; 1254182048Sjhb device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1255182048Sjhb volts); 1256182048Sjhb 1257182048Sjhb /* Table is already terminated due to M_ZERO. */ 1258182048Sjhb sc->msr_settings = TRUE; 1259182048Sjhb *freqs = fp; 1260182048Sjhb return (0); 1261182048Sjhb} 1262182048Sjhb 1263176649Srpaulostatic void 1264176649Srpauloest_get_id16(uint16_t *id16_p) 1265176649Srpaulo{ 1266176649Srpaulo *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1267176649Srpaulo} 1268176649Srpaulo 1269176649Srpaulostatic int 1270176649Srpauloest_set_id16(device_t dev, uint16_t id16, int need_check) 1271176649Srpaulo{ 1272176649Srpaulo uint64_t msr; 1273176649Srpaulo uint16_t new_id16; 1274176649Srpaulo int ret = 0; 1275176649Srpaulo 1276176649Srpaulo /* Read the current register, mask out the old, set the new id. */ 1277176649Srpaulo msr = rdmsr(MSR_PERF_CTL); 1278176649Srpaulo msr = (msr & ~0xffff) | id16; 1279176649Srpaulo wrmsr(MSR_PERF_CTL, msr); 1280176649Srpaulo 1281176649Srpaulo /* Wait a short while for the new setting. XXX Is this necessary? */ 1282176649Srpaulo DELAY(EST_TRANS_LAT); 1283176649Srpaulo 1284176649Srpaulo if (need_check) { 1285176649Srpaulo est_get_id16(&new_id16); 1286176649Srpaulo if (new_id16 != id16) { 1287176649Srpaulo if (bootverbose) 1288176649Srpaulo device_printf(dev, "Invalid id16 (set, cur) " 1289176649Srpaulo "= (%u, %u)\n", id16, new_id16); 1290176649Srpaulo ret = ENXIO; 1291176649Srpaulo } 1292176649Srpaulo } 1293176649Srpaulo return (ret); 1294176649Srpaulo} 1295176649Srpaulo 1296143902Snjlstatic freq_info * 1297143902Snjlest_get_current(freq_info *freq_list) 1298142140Snjl{ 1299143902Snjl freq_info *f; 1300142140Snjl int i; 1301142140Snjl uint16_t id16; 1302142140Snjl 1303142140Snjl /* 1304142140Snjl * Try a few times to get a valid value. Sometimes, if the CPU 1305142140Snjl * is in the middle of an asynchronous transition (i.e., P4TCC), 1306142140Snjl * we get a temporary invalid result. 1307142140Snjl */ 1308142140Snjl for (i = 0; i < 5; i++) { 1309176649Srpaulo est_get_id16(&id16); 1310142140Snjl for (f = freq_list; f->id16 != 0; f++) { 1311142140Snjl if (f->id16 == id16) 1312142140Snjl return (f); 1313142140Snjl } 1314142140Snjl DELAY(100); 1315142140Snjl } 1316142140Snjl return (NULL); 1317142140Snjl} 1318142140Snjl 1319142140Snjlstatic int 1320142140Snjlest_settings(device_t dev, struct cf_setting *sets, int *count) 1321142140Snjl{ 1322142140Snjl struct est_softc *sc; 1323143902Snjl freq_info *f; 1324142140Snjl int i; 1325142140Snjl 1326142140Snjl sc = device_get_softc(dev); 1327142140Snjl if (*count < EST_MAX_SETTINGS) 1328142140Snjl return (E2BIG); 1329142140Snjl 1330142140Snjl i = 0; 1331142394Snjl for (f = sc->freq_list; f->freq != 0; f++, i++) { 1332142140Snjl sets[i].freq = f->freq; 1333142140Snjl sets[i].volts = f->volts; 1334143902Snjl sets[i].power = f->power; 1335142140Snjl sets[i].lat = EST_TRANS_LAT; 1336142140Snjl sets[i].dev = dev; 1337142140Snjl } 1338142394Snjl *count = i; 1339142140Snjl 1340142140Snjl return (0); 1341142140Snjl} 1342142140Snjl 1343142140Snjlstatic int 1344142140Snjlest_set(device_t dev, const struct cf_setting *set) 1345142140Snjl{ 1346142140Snjl struct est_softc *sc; 1347143902Snjl freq_info *f; 1348142140Snjl 1349142140Snjl /* Find the setting matching the requested one. */ 1350142140Snjl sc = device_get_softc(dev); 1351142140Snjl for (f = sc->freq_list; f->freq != 0; f++) { 1352142140Snjl if (f->freq == set->freq) 1353142140Snjl break; 1354142140Snjl } 1355142140Snjl if (f->freq == 0) 1356142140Snjl return (EINVAL); 1357142140Snjl 1358142140Snjl /* Read the current register, mask out the old, set the new id. */ 1359176649Srpaulo est_set_id16(dev, f->id16, 0); 1360142140Snjl 1361142140Snjl return (0); 1362142140Snjl} 1363142140Snjl 1364142140Snjlstatic int 1365142140Snjlest_get(device_t dev, struct cf_setting *set) 1366142140Snjl{ 1367142140Snjl struct est_softc *sc; 1368143902Snjl freq_info *f; 1369142140Snjl 1370142140Snjl sc = device_get_softc(dev); 1371142140Snjl f = est_get_current(sc->freq_list); 1372142140Snjl if (f == NULL) 1373142140Snjl return (ENXIO); 1374142140Snjl 1375142140Snjl set->freq = f->freq; 1376142140Snjl set->volts = f->volts; 1377143902Snjl set->power = f->power; 1378142140Snjl set->lat = EST_TRANS_LAT; 1379142140Snjl set->dev = dev; 1380142140Snjl return (0); 1381142140Snjl} 1382142140Snjl 1383142140Snjlstatic int 1384142140Snjlest_type(device_t dev, int *type) 1385142140Snjl{ 1386142140Snjl 1387142140Snjl if (type == NULL) 1388142140Snjl return (EINVAL); 1389142140Snjl 1390142140Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 1391142140Snjl return (0); 1392142140Snjl} 1393