est.c revision 185341
1142140Snjl/*- 2142140Snjl * Copyright (c) 2004 Colin Percival 3142140Snjl * Copyright (c) 2005 Nate Lawson 4142140Snjl * All rights reserved. 5142140Snjl * 6142140Snjl * Redistribution and use in source and binary forms, with or without 7142140Snjl * modification, are permitted providing that the following conditions 8142140Snjl * are met: 9142140Snjl * 1. Redistributions of source code must retain the above copyright 10142140Snjl * notice, this list of conditions and the following disclaimer. 11142140Snjl * 2. Redistributions in binary form must reproduce the above copyright 12142140Snjl * notice, this list of conditions and the following disclaimer in the 13142140Snjl * documentation and/or other materials provided with the distribution. 14142140Snjl * 15142140Snjl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 16142140Snjl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17142140Snjl * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18142140Snjl * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 19142140Snjl * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20142140Snjl * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21142140Snjl * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22142140Snjl * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23142140Snjl * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 24142140Snjl * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25142140Snjl * POSSIBILITY OF SUCH DAMAGE. 26142140Snjl */ 27142140Snjl 28142140Snjl#include <sys/cdefs.h> 29142140Snjl__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 185341 2008-11-26 19:25:13Z jkim $"); 30142140Snjl 31142140Snjl#include <sys/param.h> 32142140Snjl#include <sys/bus.h> 33142140Snjl#include <sys/cpu.h> 34142140Snjl#include <sys/kernel.h> 35143902Snjl#include <sys/malloc.h> 36142140Snjl#include <sys/module.h> 37142140Snjl#include <sys/smp.h> 38142140Snjl#include <sys/systm.h> 39142140Snjl 40142140Snjl#include "cpufreq_if.h" 41182048Sjhb#include <machine/clock.h> 42185341Sjkim#include <machine/cputypes.h> 43142140Snjl#include <machine/md_var.h> 44177040Sjhb#include <machine/specialreg.h> 45142140Snjl 46144630Snjl#include <contrib/dev/acpica/acpi.h> 47144630Snjl#include <dev/acpica/acpivar.h> 48144630Snjl#include "acpi_if.h" 49144630Snjl 50142140Snjl/* Status/control registers (from the IA-32 System Programming Guide). */ 51142140Snjl#define MSR_PERF_STATUS 0x198 52142140Snjl#define MSR_PERF_CTL 0x199 53142140Snjl 54142140Snjl/* Register and bit for enabling SpeedStep. */ 55142140Snjl#define MSR_MISC_ENABLE 0x1a0 56142140Snjl#define MSR_SS_ENABLE (1<<16) 57142140Snjl 58185341Sjkim#ifndef CPU_VENDOR_CENTAUR 59185341Sjkim#define CPU_VENDOR_CENTAUR 0x111d 60185341Sjkim#endif 61185341Sjkim 62142140Snjl/* Frequency and MSR control values. */ 63142140Snjltypedef struct { 64142140Snjl uint16_t freq; 65142140Snjl uint16_t volts; 66142140Snjl uint16_t id16; 67143902Snjl int power; 68142140Snjl} freq_info; 69142140Snjl 70142140Snjl/* Identifying characteristics of a processor and supported frequencies. */ 71142140Snjltypedef struct { 72185341Sjkim const u_int vendor_id; 73142140Snjl uint32_t id32; 74143902Snjl freq_info *freqtab; 75142140Snjl} cpu_info; 76142140Snjl 77142140Snjlstruct est_softc { 78143902Snjl device_t dev; 79143902Snjl int acpi_settings; 80182048Sjhb int msr_settings; 81143902Snjl freq_info *freq_list; 82142140Snjl}; 83142140Snjl 84142140Snjl/* Convert MHz and mV into IDs for passing to the MSR. */ 85142140Snjl#define ID16(MHz, mV, bus_clk) \ 86142140Snjl (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 87142140Snjl#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 88142140Snjl ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 89142140Snjl 90142140Snjl/* Format for storing IDs in our table. */ 91158446Snjl#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \ 92158446Snjl { MHz, mV, ID16(MHz, mV, bus_clk), mW } 93142140Snjl#define FREQ_INFO(MHz, mV, bus_clk) \ 94158446Snjl FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN) 95142140Snjl#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 96185341Sjkim { CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 97158446Snjl#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \ 98185341Sjkim { CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab } 99142140Snjl 100182201Sjhbstatic int msr_info_enabled = 0; 101182201SjhbTUNABLE_INT("hw.est.msr_info", &msr_info_enabled); 102142140Snjl 103142140Snjl/* Default bus clock value for Centrino processors. */ 104142140Snjl#define INTEL_BUS_CLK 100 105142140Snjl 106142140Snjl/* XXX Update this if new CPUs have more settings. */ 107142140Snjl#define EST_MAX_SETTINGS 10 108142140SnjlCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 109142140Snjl 110142140Snjl/* Estimate in microseconds of latency for performing a transition. */ 111177296Sphk#define EST_TRANS_LAT 1000 112142140Snjl 113142140Snjl/* 114142140Snjl * Frequency (MHz) and voltage (mV) settings. Data from the 115142140Snjl * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 116142140Snjl * 117143902Snjl * Dothan processors have multiple VID#s with different settings for 118143902Snjl * each VID#. Since we can't uniquely identify this info 119142140Snjl * without undisclosed methods from Intel, we can't support newer 120142140Snjl * processors with this table method. If ACPI Px states are supported, 121143902Snjl * we get info from them. 122142140Snjl */ 123143902Snjlstatic freq_info PM17_130[] = { 124142140Snjl /* 130nm 1.70GHz Pentium M */ 125142140Snjl FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 126142140Snjl FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 127142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 128142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 129142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 130142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 131142140Snjl FREQ_INFO( 0, 0, 1), 132142140Snjl}; 133143902Snjlstatic freq_info PM16_130[] = { 134142140Snjl /* 130nm 1.60GHz Pentium M */ 135142140Snjl FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 136142140Snjl FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 137142140Snjl FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 138142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 139142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 140142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 141142140Snjl FREQ_INFO( 0, 0, 1), 142142140Snjl}; 143143902Snjlstatic freq_info PM15_130[] = { 144142140Snjl /* 130nm 1.50GHz Pentium M */ 145142140Snjl FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 146142140Snjl FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 147142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 148142140Snjl FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 149142140Snjl FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 150142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 151142140Snjl FREQ_INFO( 0, 0, 1), 152142140Snjl}; 153143902Snjlstatic freq_info PM14_130[] = { 154142140Snjl /* 130nm 1.40GHz Pentium M */ 155142140Snjl FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 156142140Snjl FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 157142140Snjl FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 158142140Snjl FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 159142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 160142140Snjl FREQ_INFO( 0, 0, 1), 161142140Snjl}; 162143902Snjlstatic freq_info PM13_130[] = { 163142140Snjl /* 130nm 1.30GHz Pentium M */ 164142140Snjl FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 165142140Snjl FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 166142140Snjl FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 167142140Snjl FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 168142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 169142140Snjl FREQ_INFO( 0, 0, 1), 170142140Snjl}; 171143902Snjlstatic freq_info PM13_LV_130[] = { 172142140Snjl /* 130nm 1.30GHz Low Voltage Pentium M */ 173142140Snjl FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 174142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 175142140Snjl FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 176142140Snjl FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 177142140Snjl FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 178142140Snjl FREQ_INFO( 800, 988, INTEL_BUS_CLK), 179142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 180142140Snjl FREQ_INFO( 0, 0, 1), 181142140Snjl}; 182143902Snjlstatic freq_info PM12_LV_130[] = { 183142140Snjl /* 130 nm 1.20GHz Low Voltage Pentium M */ 184142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 185142140Snjl FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 186142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 187142140Snjl FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 188142140Snjl FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 189142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 190142140Snjl FREQ_INFO( 0, 0, 1), 191142140Snjl}; 192143902Snjlstatic freq_info PM11_LV_130[] = { 193142140Snjl /* 130 nm 1.10GHz Low Voltage Pentium M */ 194142140Snjl FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 195142140Snjl FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 196142140Snjl FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 197142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 198142140Snjl FREQ_INFO( 600, 956, INTEL_BUS_CLK), 199142140Snjl FREQ_INFO( 0, 0, 1), 200142140Snjl}; 201143902Snjlstatic freq_info PM11_ULV_130[] = { 202142140Snjl /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 203142140Snjl FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 204142140Snjl FREQ_INFO(1000, 988, INTEL_BUS_CLK), 205142140Snjl FREQ_INFO( 900, 972, INTEL_BUS_CLK), 206142140Snjl FREQ_INFO( 800, 956, INTEL_BUS_CLK), 207142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 208142140Snjl FREQ_INFO( 0, 0, 1), 209142140Snjl}; 210143902Snjlstatic freq_info PM10_ULV_130[] = { 211142140Snjl /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 212142140Snjl FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 213142140Snjl FREQ_INFO( 900, 988, INTEL_BUS_CLK), 214142140Snjl FREQ_INFO( 800, 972, INTEL_BUS_CLK), 215142140Snjl FREQ_INFO( 600, 844, INTEL_BUS_CLK), 216142140Snjl FREQ_INFO( 0, 0, 1), 217142140Snjl}; 218142140Snjl 219142140Snjl/* 220142140Snjl * Data from "Intel Pentium M Processor on 90nm Process with 221142140Snjl * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 222142140Snjl */ 223143902Snjlstatic freq_info PM_765A_90[] = { 224142140Snjl /* 90 nm 2.10GHz Pentium M, VID #A */ 225142140Snjl FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 226142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 227142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 228142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 229142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 230142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 231142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 232142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 233142140Snjl FREQ_INFO( 0, 0, 1), 234142140Snjl}; 235143902Snjlstatic freq_info PM_765B_90[] = { 236142140Snjl /* 90 nm 2.10GHz Pentium M, VID #B */ 237142140Snjl FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 238142140Snjl FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 239142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 240142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 241142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 242142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 243142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 244142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 245142140Snjl FREQ_INFO( 0, 0, 1), 246142140Snjl}; 247143902Snjlstatic freq_info PM_765C_90[] = { 248142140Snjl /* 90 nm 2.10GHz Pentium M, VID #C */ 249142140Snjl FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 250142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 251142140Snjl FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 252142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 253142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 254142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 255142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 256142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 257142140Snjl FREQ_INFO( 0, 0, 1), 258142140Snjl}; 259143902Snjlstatic freq_info PM_765E_90[] = { 260142140Snjl /* 90 nm 2.10GHz Pentium M, VID #E */ 261142140Snjl FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 262142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 263142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 264142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 265142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 266142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 267142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 268142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 269142140Snjl FREQ_INFO( 0, 0, 1), 270142140Snjl}; 271143902Snjlstatic freq_info PM_755A_90[] = { 272142140Snjl /* 90 nm 2.00GHz Pentium M, VID #A */ 273142140Snjl FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 274142140Snjl FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 275142140Snjl FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 276142140Snjl FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 277142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 278142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 279142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 280142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 281142140Snjl FREQ_INFO( 0, 0, 1), 282142140Snjl}; 283143902Snjlstatic freq_info PM_755B_90[] = { 284142140Snjl /* 90 nm 2.00GHz Pentium M, VID #B */ 285142140Snjl FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 286142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 287142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 288142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 289142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 290142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 291142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 292142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 293142140Snjl FREQ_INFO( 0, 0, 1), 294142140Snjl}; 295143902Snjlstatic freq_info PM_755C_90[] = { 296142140Snjl /* 90 nm 2.00GHz Pentium M, VID #C */ 297142140Snjl FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 298142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 299142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 300142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 301142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 302142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 303142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 304142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 305142140Snjl FREQ_INFO( 0, 0, 1), 306142140Snjl}; 307143902Snjlstatic freq_info PM_755D_90[] = { 308142140Snjl /* 90 nm 2.00GHz Pentium M, VID #D */ 309142140Snjl FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 310142140Snjl FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 311142140Snjl FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 312142140Snjl FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 313142140Snjl FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 314142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 315142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 316142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 317142140Snjl FREQ_INFO( 0, 0, 1), 318142140Snjl}; 319143902Snjlstatic freq_info PM_745A_90[] = { 320142140Snjl /* 90 nm 1.80GHz Pentium M, VID #A */ 321142140Snjl FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 322142140Snjl FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 323142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 324142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 325142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 326142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 327142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 328142140Snjl FREQ_INFO( 0, 0, 1), 329142140Snjl}; 330143902Snjlstatic freq_info PM_745B_90[] = { 331142140Snjl /* 90 nm 1.80GHz Pentium M, VID #B */ 332142140Snjl FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 333142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 334142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 335142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 336142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 337142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 338142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 339142140Snjl FREQ_INFO( 0, 0, 1), 340142140Snjl}; 341143902Snjlstatic freq_info PM_745C_90[] = { 342142140Snjl /* 90 nm 1.80GHz Pentium M, VID #C */ 343142140Snjl FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 344142140Snjl FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 345142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 346142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 347142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 348142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 349142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 350142140Snjl FREQ_INFO( 0, 0, 1), 351142140Snjl}; 352143902Snjlstatic freq_info PM_745D_90[] = { 353142140Snjl /* 90 nm 1.80GHz Pentium M, VID #D */ 354142140Snjl FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 355142140Snjl FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 356142140Snjl FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 357142140Snjl FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 358142140Snjl FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 359142140Snjl FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 360142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 361142140Snjl FREQ_INFO( 0, 0, 1), 362142140Snjl}; 363143902Snjlstatic freq_info PM_735A_90[] = { 364142140Snjl /* 90 nm 1.70GHz Pentium M, VID #A */ 365142140Snjl FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 366142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 367142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 368142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 369142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 370142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 371142140Snjl FREQ_INFO( 0, 0, 1), 372142140Snjl}; 373143902Snjlstatic freq_info PM_735B_90[] = { 374142140Snjl /* 90 nm 1.70GHz Pentium M, VID #B */ 375142140Snjl FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 376142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 377142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 378142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 379142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 380142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 381142140Snjl FREQ_INFO( 0, 0, 1), 382142140Snjl}; 383143902Snjlstatic freq_info PM_735C_90[] = { 384142140Snjl /* 90 nm 1.70GHz Pentium M, VID #C */ 385142140Snjl FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 386142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 387142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 388142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 389142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 390142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 391142140Snjl FREQ_INFO( 0, 0, 1), 392142140Snjl}; 393143902Snjlstatic freq_info PM_735D_90[] = { 394142140Snjl /* 90 nm 1.70GHz Pentium M, VID #D */ 395142140Snjl FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 396142140Snjl FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 397142140Snjl FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 398142140Snjl FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 399142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 400142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 401142140Snjl FREQ_INFO( 0, 0, 1), 402142140Snjl}; 403143902Snjlstatic freq_info PM_725A_90[] = { 404142140Snjl /* 90 nm 1.60GHz Pentium M, VID #A */ 405142140Snjl FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 406142140Snjl FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 407142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 408142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 409142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 410142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 411142140Snjl FREQ_INFO( 0, 0, 1), 412142140Snjl}; 413143902Snjlstatic freq_info PM_725B_90[] = { 414142140Snjl /* 90 nm 1.60GHz Pentium M, VID #B */ 415142140Snjl FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 416142140Snjl FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 417142140Snjl FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 418142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 419142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 420142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 421142140Snjl FREQ_INFO( 0, 0, 1), 422142140Snjl}; 423143902Snjlstatic freq_info PM_725C_90[] = { 424142140Snjl /* 90 nm 1.60GHz Pentium M, VID #C */ 425142140Snjl FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 426142140Snjl FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 427142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 428142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 429142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 430142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 431142140Snjl FREQ_INFO( 0, 0, 1), 432142140Snjl}; 433143902Snjlstatic freq_info PM_725D_90[] = { 434142140Snjl /* 90 nm 1.60GHz Pentium M, VID #D */ 435142140Snjl FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 436142140Snjl FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 437142140Snjl FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 438142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 439142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 440142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 441142140Snjl FREQ_INFO( 0, 0, 1), 442142140Snjl}; 443143902Snjlstatic freq_info PM_715A_90[] = { 444142140Snjl /* 90 nm 1.50GHz Pentium M, VID #A */ 445142140Snjl FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 446142140Snjl FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 447142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 448142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 449142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 450142140Snjl FREQ_INFO( 0, 0, 1), 451142140Snjl}; 452143902Snjlstatic freq_info PM_715B_90[] = { 453142140Snjl /* 90 nm 1.50GHz Pentium M, VID #B */ 454142140Snjl FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 455142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 456142140Snjl FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 457142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 458142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 459142140Snjl FREQ_INFO( 0, 0, 1), 460142140Snjl}; 461143902Snjlstatic freq_info PM_715C_90[] = { 462142140Snjl /* 90 nm 1.50GHz Pentium M, VID #C */ 463142140Snjl FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 464142140Snjl FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 465142140Snjl FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 466142140Snjl FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 467142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 468142140Snjl FREQ_INFO( 0, 0, 1), 469142140Snjl}; 470143902Snjlstatic freq_info PM_715D_90[] = { 471142140Snjl /* 90 nm 1.50GHz Pentium M, VID #D */ 472142140Snjl FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 473142140Snjl FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 474142140Snjl FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 475142140Snjl FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 476142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 477142140Snjl FREQ_INFO( 0, 0, 1), 478142140Snjl}; 479155996Scpercivastatic freq_info PM_778_90[] = { 480155996Scperciva /* 90 nm 1.60GHz Low Voltage Pentium M */ 481155996Scperciva FREQ_INFO(1600, 1116, INTEL_BUS_CLK), 482155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 483155996Scperciva FREQ_INFO(1400, 1100, INTEL_BUS_CLK), 484155996Scperciva FREQ_INFO(1300, 1084, INTEL_BUS_CLK), 485155996Scperciva FREQ_INFO(1200, 1068, INTEL_BUS_CLK), 486155996Scperciva FREQ_INFO(1100, 1052, INTEL_BUS_CLK), 487155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 488155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 489155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 490155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 491155996Scperciva FREQ_INFO( 0, 0, 1), 492155996Scperciva}; 493155996Scpercivastatic freq_info PM_758_90[] = { 494155996Scperciva /* 90 nm 1.50GHz Low Voltage Pentium M */ 495155996Scperciva FREQ_INFO(1500, 1116, INTEL_BUS_CLK), 496155996Scperciva FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 497155996Scperciva FREQ_INFO(1300, 1100, INTEL_BUS_CLK), 498155996Scperciva FREQ_INFO(1200, 1084, INTEL_BUS_CLK), 499155996Scperciva FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 500155996Scperciva FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 501155996Scperciva FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 502155996Scperciva FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 503155996Scperciva FREQ_INFO( 600, 988, INTEL_BUS_CLK), 504155996Scperciva FREQ_INFO( 0, 0, 1), 505155996Scperciva}; 506143902Snjlstatic freq_info PM_738_90[] = { 507142140Snjl /* 90 nm 1.40GHz Low Voltage Pentium M */ 508142140Snjl FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 509142140Snjl FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 510142140Snjl FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 511142140Snjl FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 512142140Snjl FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 513142140Snjl FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 514142140Snjl FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 515142140Snjl FREQ_INFO( 600, 988, INTEL_BUS_CLK), 516142140Snjl FREQ_INFO( 0, 0, 1), 517142140Snjl}; 518155996Scpercivastatic freq_info PM_773G_90[] = { 519155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */ 520155996Scperciva FREQ_INFO(1300, 956, INTEL_BUS_CLK), 521155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 522155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 523155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 524155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 525155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 526155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 527155996Scperciva}; 528155996Scpercivastatic freq_info PM_773H_90[] = { 529155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */ 530155996Scperciva FREQ_INFO(1300, 940, INTEL_BUS_CLK), 531155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 532155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 533155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 534155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 535155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 536155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 537155996Scperciva}; 538155996Scpercivastatic freq_info PM_773I_90[] = { 539155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */ 540155996Scperciva FREQ_INFO(1300, 924, INTEL_BUS_CLK), 541155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 542155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 543155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 544155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 545155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 546155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 547155996Scperciva}; 548155996Scpercivastatic freq_info PM_773J_90[] = { 549155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */ 550155996Scperciva FREQ_INFO(1300, 908, INTEL_BUS_CLK), 551155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 552155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 553155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 554155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 555155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 556155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 557155996Scperciva}; 558155996Scpercivastatic freq_info PM_773K_90[] = { 559155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */ 560155996Scperciva FREQ_INFO(1300, 892, INTEL_BUS_CLK), 561155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 562155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 563155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 564155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 565155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 566155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 567155996Scperciva}; 568155996Scpercivastatic freq_info PM_773L_90[] = { 569155996Scperciva /* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */ 570155996Scperciva FREQ_INFO(1300, 876, INTEL_BUS_CLK), 571155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 572155996Scperciva FREQ_INFO(1100, 860, INTEL_BUS_CLK), 573155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 574155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 575155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 576155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 577155996Scperciva}; 578155996Scpercivastatic freq_info PM_753G_90[] = { 579155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */ 580155996Scperciva FREQ_INFO(1200, 956, INTEL_BUS_CLK), 581155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 582155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 583155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 584155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 585155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 586155996Scperciva}; 587155996Scpercivastatic freq_info PM_753H_90[] = { 588155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */ 589155996Scperciva FREQ_INFO(1200, 940, INTEL_BUS_CLK), 590155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 591155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 592155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 593155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 594155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 595155996Scperciva}; 596155996Scpercivastatic freq_info PM_753I_90[] = { 597155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */ 598155996Scperciva FREQ_INFO(1200, 924, INTEL_BUS_CLK), 599155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 600155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 601155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 602155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 603155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 604155996Scperciva}; 605155996Scpercivastatic freq_info PM_753J_90[] = { 606155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */ 607155996Scperciva FREQ_INFO(1200, 908, INTEL_BUS_CLK), 608155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 609155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 610155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 611155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 612155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 613155996Scperciva}; 614155996Scpercivastatic freq_info PM_753K_90[] = { 615155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */ 616155996Scperciva FREQ_INFO(1200, 892, INTEL_BUS_CLK), 617155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 618155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 619155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 620155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 621155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 622155996Scperciva}; 623155996Scpercivastatic freq_info PM_753L_90[] = { 624155996Scperciva /* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */ 625155996Scperciva FREQ_INFO(1200, 876, INTEL_BUS_CLK), 626155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 627155996Scperciva FREQ_INFO(1000, 860, INTEL_BUS_CLK), 628155996Scperciva FREQ_INFO( 900, 844, INTEL_BUS_CLK), 629155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 630155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 631155996Scperciva}; 632155996Scperciva 633155996Scpercivastatic freq_info PM_733JG_90[] = { 634155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */ 635155996Scperciva FREQ_INFO(1100, 956, INTEL_BUS_CLK), 636155996Scperciva FREQ_INFO(1000, 940, INTEL_BUS_CLK), 637155996Scperciva FREQ_INFO( 900, 908, INTEL_BUS_CLK), 638155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 639155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 640155996Scperciva}; 641155996Scpercivastatic freq_info PM_733JH_90[] = { 642155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */ 643155996Scperciva FREQ_INFO(1100, 940, INTEL_BUS_CLK), 644155996Scperciva FREQ_INFO(1000, 924, INTEL_BUS_CLK), 645155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 646155996Scperciva FREQ_INFO( 800, 876, INTEL_BUS_CLK), 647155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 648155996Scperciva}; 649155996Scpercivastatic freq_info PM_733JI_90[] = { 650155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */ 651155996Scperciva FREQ_INFO(1100, 924, INTEL_BUS_CLK), 652155996Scperciva FREQ_INFO(1000, 908, INTEL_BUS_CLK), 653155996Scperciva FREQ_INFO( 900, 892, INTEL_BUS_CLK), 654155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 655155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 656155996Scperciva}; 657155996Scpercivastatic freq_info PM_733JJ_90[] = { 658155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */ 659155996Scperciva FREQ_INFO(1100, 908, INTEL_BUS_CLK), 660155996Scperciva FREQ_INFO(1000, 892, INTEL_BUS_CLK), 661155996Scperciva FREQ_INFO( 900, 876, INTEL_BUS_CLK), 662155996Scperciva FREQ_INFO( 800, 860, INTEL_BUS_CLK), 663155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 664155996Scperciva}; 665155996Scpercivastatic freq_info PM_733JK_90[] = { 666155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */ 667155996Scperciva FREQ_INFO(1100, 892, INTEL_BUS_CLK), 668155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 669155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 670155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 671155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 672155996Scperciva}; 673155996Scpercivastatic freq_info PM_733JL_90[] = { 674155996Scperciva /* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */ 675155996Scperciva FREQ_INFO(1100, 876, INTEL_BUS_CLK), 676155996Scperciva FREQ_INFO(1000, 876, INTEL_BUS_CLK), 677155996Scperciva FREQ_INFO( 900, 860, INTEL_BUS_CLK), 678155996Scperciva FREQ_INFO( 800, 844, INTEL_BUS_CLK), 679155996Scperciva FREQ_INFO( 600, 812, INTEL_BUS_CLK), 680155996Scperciva}; 681143902Snjlstatic freq_info PM_733_90[] = { 682142140Snjl /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 683142140Snjl FREQ_INFO(1100, 940, INTEL_BUS_CLK), 684142140Snjl FREQ_INFO(1000, 924, INTEL_BUS_CLK), 685142140Snjl FREQ_INFO( 900, 892, INTEL_BUS_CLK), 686142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 687142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 688142140Snjl FREQ_INFO( 0, 0, 1), 689142140Snjl}; 690143902Snjlstatic freq_info PM_723_90[] = { 691142140Snjl /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 692142140Snjl FREQ_INFO(1000, 940, INTEL_BUS_CLK), 693142140Snjl FREQ_INFO( 900, 908, INTEL_BUS_CLK), 694142140Snjl FREQ_INFO( 800, 876, INTEL_BUS_CLK), 695142140Snjl FREQ_INFO( 600, 812, INTEL_BUS_CLK), 696142140Snjl FREQ_INFO( 0, 0, 1), 697142140Snjl}; 698142140Snjl 699158446Snjl/* 700158446Snjl * VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants. 701158446Snjl * Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet. 702158446Snjl */ 703158446Snjlstatic freq_info C7M_795[] = { 704158446Snjl /* 2.00GHz Centaur C7-M 533 Mhz FSB */ 705158446Snjl FREQ_INFO_PWR(2000, 1148, 133, 20000), 706158446Snjl FREQ_INFO_PWR(1867, 1132, 133, 18000), 707158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 708158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 709158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 710158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 711158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 712158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 713158446Snjl FREQ_INFO(0, 0, 1), 714158446Snjl}; 715158446Snjlstatic freq_info C7M_785[] = { 716158446Snjl /* 1.80GHz Centaur C7-M 533 Mhz FSB */ 717158446Snjl FREQ_INFO_PWR(1867, 1148, 133, 18000), 718158446Snjl FREQ_INFO_PWR(1600, 1100, 133, 15000), 719158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 720158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 721158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 722158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 723158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 724158446Snjl FREQ_INFO(0, 0, 1), 725158446Snjl}; 726158446Snjlstatic freq_info C7M_765[] = { 727158446Snjl /* 1.60GHz Centaur C7-M 533 Mhz FSB */ 728158446Snjl FREQ_INFO_PWR(1600, 1084, 133, 15000), 729158446Snjl FREQ_INFO_PWR(1467, 1052, 133, 13000), 730158446Snjl FREQ_INFO_PWR(1200, 1004, 133, 10000), 731158446Snjl FREQ_INFO_PWR( 800, 844, 133, 7000), 732158446Snjl FREQ_INFO_PWR( 667, 844, 133, 6000), 733158446Snjl FREQ_INFO_PWR( 533, 844, 133, 5000), 734158446Snjl FREQ_INFO(0, 0, 1), 735158446Snjl}; 736158446Snjl 737158446Snjlstatic freq_info C7M_794[] = { 738158446Snjl /* 2.00GHz Centaur C7-M 400 Mhz FSB */ 739158446Snjl FREQ_INFO_PWR(2000, 1148, 100, 20000), 740158446Snjl FREQ_INFO_PWR(1800, 1132, 100, 18000), 741158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 742158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 743158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 744158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 745158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 746158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 747158446Snjl FREQ_INFO(0, 0, 1), 748158446Snjl}; 749158446Snjlstatic freq_info C7M_784[] = { 750158446Snjl /* 1.80GHz Centaur C7-M 400 Mhz FSB */ 751158446Snjl FREQ_INFO_PWR(1800, 1148, 100, 18000), 752158446Snjl FREQ_INFO_PWR(1600, 1100, 100, 15000), 753158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 754158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 755158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 756158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 757158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 758158446Snjl FREQ_INFO(0, 0, 1), 759158446Snjl}; 760158446Snjlstatic freq_info C7M_764[] = { 761158446Snjl /* 1.60GHz Centaur C7-M 400 Mhz FSB */ 762158446Snjl FREQ_INFO_PWR(1600, 1084, 100, 15000), 763158446Snjl FREQ_INFO_PWR(1400, 1052, 100, 13000), 764158446Snjl FREQ_INFO_PWR(1000, 1004, 100, 10000), 765158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 766158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 767158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 768158446Snjl FREQ_INFO(0, 0, 1), 769158446Snjl}; 770158446Snjlstatic freq_info C7M_754[] = { 771158446Snjl /* 1.50GHz Centaur C7-M 400 Mhz FSB */ 772158446Snjl FREQ_INFO_PWR(1500, 1004, 100, 12000), 773158446Snjl FREQ_INFO_PWR(1400, 988, 100, 11000), 774158446Snjl FREQ_INFO_PWR(1000, 940, 100, 9000), 775158446Snjl FREQ_INFO_PWR( 800, 844, 100, 7000), 776158446Snjl FREQ_INFO_PWR( 600, 844, 100, 6000), 777158446Snjl FREQ_INFO_PWR( 400, 844, 100, 5000), 778158446Snjl FREQ_INFO(0, 0, 1), 779158446Snjl}; 780158446Snjlstatic freq_info C7M_771[] = { 781158446Snjl /* 1.20GHz Centaur C7-M 400 Mhz FSB */ 782158446Snjl FREQ_INFO_PWR(1200, 860, 100, 7000), 783158446Snjl FREQ_INFO_PWR(1000, 860, 100, 6000), 784158446Snjl FREQ_INFO_PWR( 800, 844, 100, 5500), 785158446Snjl FREQ_INFO_PWR( 600, 844, 100, 5000), 786158446Snjl FREQ_INFO_PWR( 400, 844, 100, 4000), 787158446Snjl FREQ_INFO(0, 0, 1), 788158446Snjl}; 789158446Snjl 790158446Snjlstatic freq_info C7M_775_ULV[] = { 791158446Snjl /* 1.50GHz Centaur C7-M ULV */ 792158446Snjl FREQ_INFO_PWR(1500, 956, 100, 7500), 793158446Snjl FREQ_INFO_PWR(1400, 940, 100, 6000), 794158446Snjl FREQ_INFO_PWR(1000, 860, 100, 5000), 795158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 796158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 797158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 798158446Snjl FREQ_INFO(0, 0, 1), 799158446Snjl}; 800158446Snjlstatic freq_info C7M_772_ULV[] = { 801158446Snjl /* 1.20GHz Centaur C7-M ULV */ 802158446Snjl FREQ_INFO_PWR(1200, 844, 100, 5000), 803158446Snjl FREQ_INFO_PWR(1000, 844, 100, 4000), 804158446Snjl FREQ_INFO_PWR( 800, 828, 100, 2800), 805158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 806158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 807158446Snjl FREQ_INFO(0, 0, 1), 808158446Snjl}; 809158446Snjlstatic freq_info C7M_779_ULV[] = { 810158446Snjl /* 1.00GHz Centaur C7-M ULV */ 811158446Snjl FREQ_INFO_PWR(1000, 796, 100, 3500), 812158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 813158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 814158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 815158446Snjl FREQ_INFO(0, 0, 1), 816158446Snjl}; 817158446Snjlstatic freq_info C7M_770_ULV[] = { 818158446Snjl /* 1.00GHz Centaur C7-M ULV */ 819158446Snjl FREQ_INFO_PWR(1000, 844, 100, 5000), 820158446Snjl FREQ_INFO_PWR( 800, 796, 100, 2800), 821158446Snjl FREQ_INFO_PWR( 600, 796, 100, 2500), 822158446Snjl FREQ_INFO_PWR( 400, 796, 100, 2000), 823158446Snjl FREQ_INFO(0, 0, 1), 824158446Snjl}; 825158446Snjl 826143902Snjlstatic cpu_info ESTprocs[] = { 827142140Snjl INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 828142140Snjl INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 829142140Snjl INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 830142140Snjl INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 831142140Snjl INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 832142140Snjl INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 833142140Snjl INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 834142140Snjl INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 835142140Snjl INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 836142140Snjl INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 837142140Snjl INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 838142140Snjl INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 839142140Snjl INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 840142140Snjl INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 841142140Snjl INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 842142140Snjl INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 843142140Snjl INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 844142140Snjl INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 845142140Snjl INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 846142140Snjl INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 847142140Snjl INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 848142140Snjl INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 849142140Snjl INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 850142140Snjl INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 851142140Snjl INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 852142140Snjl INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 853142140Snjl INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 854142140Snjl INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 855142140Snjl INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 856142140Snjl INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 857142140Snjl INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 858142140Snjl INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 859142140Snjl INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 860142140Snjl INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 861155996Scperciva INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK), 862155996Scperciva INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK), 863142140Snjl INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 864155996Scperciva INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK), 865155996Scperciva INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK), 866155996Scperciva INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK), 867155996Scperciva INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK), 868155996Scperciva INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK), 869155996Scperciva INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK), 870155996Scperciva INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK), 871155996Scperciva INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK), 872155996Scperciva INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK), 873155996Scperciva INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK), 874155996Scperciva INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK), 875155996Scperciva INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK), 876155996Scperciva INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK), 877155996Scperciva INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 878155996Scperciva INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK), 879155996Scperciva INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK), 880155996Scperciva INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK), 881155996Scperciva INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK), 882142140Snjl INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 883142140Snjl INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 884158446Snjl 885158446Snjl CENTAUR(C7M_795, 2000, 1148, 533, 844, 133), 886158446Snjl CENTAUR(C7M_794, 2000, 1148, 400, 844, 100), 887158446Snjl CENTAUR(C7M_785, 1867, 1148, 533, 844, 133), 888158446Snjl CENTAUR(C7M_784, 1800, 1148, 400, 844, 100), 889158446Snjl CENTAUR(C7M_765, 1600, 1084, 533, 844, 133), 890158446Snjl CENTAUR(C7M_764, 1600, 1084, 400, 844, 100), 891158446Snjl CENTAUR(C7M_754, 1500, 1004, 400, 844, 100), 892158446Snjl CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100), 893158446Snjl CENTAUR(C7M_771, 1200, 860, 400, 844, 100), 894158446Snjl CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100), 895158446Snjl CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100), 896158446Snjl CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100), 897185341Sjkim { 0, 0, NULL }, 898142140Snjl}; 899142140Snjl 900142140Snjlstatic void est_identify(driver_t *driver, device_t parent); 901144630Snjlstatic int est_features(driver_t *driver, u_int *features); 902142140Snjlstatic int est_probe(device_t parent); 903142140Snjlstatic int est_attach(device_t parent); 904142140Snjlstatic int est_detach(device_t parent); 905143902Snjlstatic int est_get_info(device_t dev); 906143902Snjlstatic int est_acpi_info(device_t dev, freq_info **freqs); 907158446Snjlstatic int est_table_info(device_t dev, uint64_t msr, freq_info **freqs); 908182048Sjhbstatic int est_msr_info(device_t dev, uint64_t msr, freq_info **freqs); 909143902Snjlstatic freq_info *est_get_current(freq_info *freq_list); 910142140Snjlstatic int est_settings(device_t dev, struct cf_setting *sets, int *count); 911142140Snjlstatic int est_set(device_t dev, const struct cf_setting *set); 912142140Snjlstatic int est_get(device_t dev, struct cf_setting *set); 913142140Snjlstatic int est_type(device_t dev, int *type); 914176649Srpaulostatic int est_set_id16(device_t dev, uint16_t id16, int need_check); 915176649Srpaulostatic void est_get_id16(uint16_t *id16_p); 916142140Snjl 917142140Snjlstatic device_method_t est_methods[] = { 918142140Snjl /* Device interface */ 919142140Snjl DEVMETHOD(device_identify, est_identify), 920142140Snjl DEVMETHOD(device_probe, est_probe), 921142140Snjl DEVMETHOD(device_attach, est_attach), 922142140Snjl DEVMETHOD(device_detach, est_detach), 923142140Snjl 924142140Snjl /* cpufreq interface */ 925142140Snjl DEVMETHOD(cpufreq_drv_set, est_set), 926142140Snjl DEVMETHOD(cpufreq_drv_get, est_get), 927142140Snjl DEVMETHOD(cpufreq_drv_type, est_type), 928142140Snjl DEVMETHOD(cpufreq_drv_settings, est_settings), 929144630Snjl 930144630Snjl /* ACPI interface */ 931144630Snjl DEVMETHOD(acpi_get_features, est_features), 932144630Snjl 933142140Snjl {0, 0} 934142140Snjl}; 935142140Snjl 936142140Snjlstatic driver_t est_driver = { 937142140Snjl "est", 938142140Snjl est_methods, 939142140Snjl sizeof(struct est_softc), 940142140Snjl}; 941142140Snjl 942142140Snjlstatic devclass_t est_devclass; 943142140SnjlDRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 944142140Snjl 945144630Snjlstatic int 946144630Snjlest_features(driver_t *driver, u_int *features) 947144630Snjl{ 948144630Snjl 949144630Snjl /* Notify the ACPI CPU that we support direct access to MSRs */ 950144630Snjl *features = ACPI_CAP_PERF_MSRS; 951144630Snjl return (0); 952144630Snjl} 953144630Snjl 954142140Snjlstatic void 955142140Snjlest_identify(driver_t *driver, device_t parent) 956142140Snjl{ 957144630Snjl device_t child; 958142140Snjl 959142140Snjl /* Make sure we're not being doubly invoked. */ 960142140Snjl if (device_find_child(parent, "est", -1) != NULL) 961142140Snjl return; 962142140Snjl 963142140Snjl /* Check that CPUID is supported and the vendor is Intel.*/ 964185341Sjkim if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL && 965185341Sjkim cpu_vendor_id != CPU_VENDOR_CENTAUR)) 966142140Snjl return; 967142140Snjl 968158446Snjl /* 969177040Sjhb * Check if the CPU supports EST. 970158446Snjl */ 971177040Sjhb if (!(cpu_feature2 & CPUID2_EST)) 972142140Snjl return; 973142140Snjl 974142625Snjl /* 975142625Snjl * We add a child for each CPU since settings must be performed 976142625Snjl * on each CPU in the SMP case. 977142625Snjl */ 978181691Sjhb child = BUS_ADD_CHILD(parent, 10, "est", -1); 979144630Snjl if (child == NULL) 980142140Snjl device_printf(parent, "add est child failed\n"); 981142140Snjl} 982142140Snjl 983142140Snjlstatic int 984142140Snjlest_probe(device_t dev) 985142140Snjl{ 986142140Snjl device_t perf_dev; 987142140Snjl uint64_t msr; 988142140Snjl int error, type; 989142203Snjl 990142203Snjl if (resource_disabled("est", 0)) 991142203Snjl return (ENXIO); 992142140Snjl 993142140Snjl /* 994142140Snjl * If the ACPI perf driver has attached and is not just offering 995142140Snjl * info, let it manage things. 996142140Snjl */ 997142140Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 998142140Snjl if (perf_dev && device_is_attached(perf_dev)) { 999142140Snjl error = CPUFREQ_DRV_TYPE(perf_dev, &type); 1000142140Snjl if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 1001142140Snjl return (ENXIO); 1002142140Snjl } 1003142140Snjl 1004142140Snjl /* Attempt to enable SpeedStep if not currently enabled. */ 1005142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1006142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1007142140Snjl wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 1008143902Snjl if (bootverbose) 1009143902Snjl device_printf(dev, "enabling SpeedStep\n"); 1010142140Snjl 1011142140Snjl /* Check if the enable failed. */ 1012142140Snjl msr = rdmsr(MSR_MISC_ENABLE); 1013142140Snjl if ((msr & MSR_SS_ENABLE) == 0) { 1014142140Snjl device_printf(dev, "failed to enable SpeedStep\n"); 1015142140Snjl return (ENXIO); 1016142140Snjl } 1017142140Snjl } 1018142140Snjl 1019142140Snjl device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 1020142140Snjl return (0); 1021142140Snjl} 1022142140Snjl 1023142140Snjlstatic int 1024142140Snjlest_attach(device_t dev) 1025142140Snjl{ 1026142140Snjl struct est_softc *sc; 1027142140Snjl 1028142140Snjl sc = device_get_softc(dev); 1029142140Snjl sc->dev = dev; 1030143902Snjl 1031143902Snjl /* Check CPU for supported settings. */ 1032143902Snjl if (est_get_info(dev)) 1033143902Snjl return (ENXIO); 1034143902Snjl 1035142140Snjl cpufreq_register(dev); 1036142140Snjl return (0); 1037142140Snjl} 1038142140Snjl 1039142140Snjlstatic int 1040142140Snjlest_detach(device_t dev) 1041142140Snjl{ 1042143902Snjl struct est_softc *sc; 1043182908Sjhb int error; 1044143902Snjl 1045182908Sjhb error = cpufreq_unregister(dev); 1046182908Sjhb if (error) 1047182908Sjhb return (error); 1048182908Sjhb 1049143902Snjl sc = device_get_softc(dev); 1050182048Sjhb if (sc->acpi_settings || sc->msr_settings) 1051143902Snjl free(sc->freq_list, M_DEVBUF); 1052182908Sjhb return (0); 1053142140Snjl} 1054142140Snjl 1055143902Snjl/* 1056143902Snjl * Probe for supported CPU settings. First, check our static table of 1057143902Snjl * settings. If no match, try using the ones offered by acpi_perf 1058143902Snjl * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 1059143902Snjl * series) export both legacy SMM IO-based access and direct MSR access 1060143902Snjl * but the direct access specifies invalid values for _PSS. 1061143902Snjl */ 1062142140Snjlstatic int 1063143902Snjlest_get_info(device_t dev) 1064142140Snjl{ 1065143902Snjl struct est_softc *sc; 1066143902Snjl uint64_t msr; 1067143902Snjl int error; 1068143902Snjl 1069143902Snjl sc = device_get_softc(dev); 1070143902Snjl msr = rdmsr(MSR_PERF_STATUS); 1071158446Snjl error = est_table_info(dev, msr, &sc->freq_list); 1072143902Snjl if (error) 1073143902Snjl error = est_acpi_info(dev, &sc->freq_list); 1074182048Sjhb if (error) 1075182048Sjhb error = est_msr_info(dev, msr, &sc->freq_list); 1076143902Snjl 1077143902Snjl if (error) { 1078143902Snjl printf( 1079143902Snjl "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 1080148583Scperciva "est: cpu_vendor %s, msr %0jx\n", cpu_vendor, msr); 1081143902Snjl return (ENXIO); 1082143902Snjl } 1083143902Snjl 1084143902Snjl return (0); 1085143902Snjl} 1086143902Snjl 1087143902Snjlstatic int 1088143902Snjlest_acpi_info(device_t dev, freq_info **freqs) 1089143902Snjl{ 1090143902Snjl struct est_softc *sc; 1091143902Snjl struct cf_setting *sets; 1092143902Snjl freq_info *table; 1093143902Snjl device_t perf_dev; 1094179445Sjhb int count, error, i, j; 1095179445Sjhb uint16_t saved_id16; 1096143902Snjl 1097143902Snjl perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 1098143902Snjl if (perf_dev == NULL || !device_is_attached(perf_dev)) 1099143902Snjl return (ENXIO); 1100143902Snjl 1101143902Snjl /* Fetch settings from acpi_perf. */ 1102143902Snjl sc = device_get_softc(dev); 1103143902Snjl table = NULL; 1104143902Snjl sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 1105143902Snjl if (sets == NULL) 1106143902Snjl return (ENOMEM); 1107176714Sgibbs count = MAX_SETTINGS; 1108143902Snjl error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 1109143902Snjl if (error) 1110143902Snjl goto out; 1111143902Snjl 1112143902Snjl /* Parse settings into our local table format. */ 1113144881Snjl table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 1114143902Snjl if (table == NULL) { 1115143902Snjl error = ENOMEM; 1116143902Snjl goto out; 1117143902Snjl } 1118179445Sjhb est_get_id16(&saved_id16); 1119176649Srpaulo for (i = 0, j = 0; i < count; i++) { 1120143902Snjl /* 1121176649Srpaulo * Confirm id16 value is correct. 1122143902Snjl */ 1123176649Srpaulo if (sets[i].freq > 0) { 1124176649Srpaulo error = est_set_id16(dev, sets[i].spec[0], 1); 1125176649Srpaulo if (error != 0) { 1126176649Srpaulo if (bootverbose) 1127176649Srpaulo device_printf(dev, "Invalid freq %u, " 1128176649Srpaulo "ignored.\n", sets[i].freq); 1129176649Srpaulo } else { 1130176649Srpaulo table[j].freq = sets[i].freq; 1131176649Srpaulo table[j].volts = sets[i].volts; 1132176649Srpaulo table[j].id16 = sets[i].spec[0]; 1133176649Srpaulo table[j].power = sets[i].power; 1134176649Srpaulo ++j; 1135176649Srpaulo } 1136176649Srpaulo } 1137143902Snjl } 1138179445Sjhb /* restore saved setting */ 1139179445Sjhb est_set_id16(dev, saved_id16, 0); 1140143902Snjl 1141144881Snjl /* Mark end of table with a terminator. */ 1142176649Srpaulo bzero(&table[j], sizeof(freq_info)); 1143144881Snjl 1144143902Snjl sc->acpi_settings = TRUE; 1145143902Snjl *freqs = table; 1146143902Snjl error = 0; 1147143902Snjl 1148143902Snjlout: 1149143902Snjl if (sets) 1150143902Snjl free(sets, M_TEMP); 1151143902Snjl if (error && table) 1152143902Snjl free(table, M_DEVBUF); 1153143902Snjl return (error); 1154143902Snjl} 1155143902Snjl 1156143902Snjlstatic int 1157158446Snjlest_table_info(device_t dev, uint64_t msr, freq_info **freqs) 1158143902Snjl{ 1159143902Snjl cpu_info *p; 1160142140Snjl uint32_t id; 1161142140Snjl 1162158446Snjl /* Find a table which matches (vendor, id32). */ 1163142140Snjl id = msr >> 32; 1164142140Snjl for (p = ESTprocs; p->id32 != 0; p++) { 1165185341Sjkim if (p->vendor_id == cpu_vendor_id && p->id32 == id) 1166142140Snjl break; 1167142140Snjl } 1168142140Snjl if (p->id32 == 0) 1169142140Snjl return (EOPNOTSUPP); 1170142140Snjl 1171142140Snjl /* Make sure the current setpoint is valid. */ 1172143902Snjl if (est_get_current(p->freqtab) == NULL) { 1173143902Snjl device_printf(dev, "current setting not found in table\n"); 1174142140Snjl return (EOPNOTSUPP); 1175143902Snjl } 1176142140Snjl 1177142140Snjl *freqs = p->freqtab; 1178142140Snjl return (0); 1179142140Snjl} 1180142140Snjl 1181182048Sjhbstatic int 1182182048Sjhbbus_speed_ok(int bus) 1183182048Sjhb{ 1184182048Sjhb 1185182048Sjhb switch (bus) { 1186182048Sjhb case 100: 1187182048Sjhb case 133: 1188182048Sjhb case 333: 1189182048Sjhb return (1); 1190182048Sjhb default: 1191182048Sjhb return (0); 1192182048Sjhb } 1193182048Sjhb} 1194182048Sjhb 1195182048Sjhb/* 1196182048Sjhb * Flesh out a simple rate table containing the high and low frequencies 1197182048Sjhb * based on the current clock speed and the upper 32 bits of the MSR. 1198182048Sjhb */ 1199182048Sjhbstatic int 1200182048Sjhbest_msr_info(device_t dev, uint64_t msr, freq_info **freqs) 1201182048Sjhb{ 1202182048Sjhb struct est_softc *sc; 1203182048Sjhb freq_info *fp; 1204182048Sjhb int bus, freq, volts; 1205182048Sjhb uint16_t id; 1206182048Sjhb 1207182201Sjhb if (!msr_info_enabled) 1208182201Sjhb return (EOPNOTSUPP); 1209182201Sjhb 1210182048Sjhb /* Figure out the bus clock. */ 1211182048Sjhb freq = tsc_freq / 1000000; 1212182048Sjhb id = msr >> 32; 1213182048Sjhb bus = freq / (id >> 8); 1214182048Sjhb device_printf(dev, "Guessed bus clock (high) of %d MHz\n", bus); 1215182048Sjhb if (!bus_speed_ok(bus)) { 1216182048Sjhb /* We may be running on the low frequency. */ 1217182048Sjhb id = msr >> 48; 1218182048Sjhb bus = freq / (id >> 8); 1219182048Sjhb device_printf(dev, "Guessed bus clock (low) of %d MHz\n", bus); 1220182048Sjhb if (!bus_speed_ok(bus)) 1221182048Sjhb return (EOPNOTSUPP); 1222182048Sjhb 1223182048Sjhb /* Calculate high frequency. */ 1224182048Sjhb id = msr >> 32; 1225182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1226182048Sjhb } 1227182048Sjhb 1228182048Sjhb /* Fill out a new freq table containing just the high and low freqs. */ 1229182048Sjhb sc = device_get_softc(dev); 1230182048Sjhb fp = malloc(sizeof(freq_info) * 3, M_DEVBUF, M_WAITOK | M_ZERO); 1231182048Sjhb 1232182048Sjhb /* First, the high frequency. */ 1233182048Sjhb volts = id & 0xff; 1234182048Sjhb if (volts != 0) { 1235182048Sjhb volts <<= 4; 1236182048Sjhb volts += 700; 1237182048Sjhb } 1238182048Sjhb fp[0].freq = freq; 1239182048Sjhb fp[0].volts = volts; 1240182048Sjhb fp[0].id16 = id; 1241182048Sjhb fp[0].power = CPUFREQ_VAL_UNKNOWN; 1242182048Sjhb device_printf(dev, "Guessed high setting of %d MHz @ %d Mv\n", freq, 1243182048Sjhb volts); 1244182048Sjhb 1245182048Sjhb /* Second, the low frequency. */ 1246182048Sjhb id = msr >> 48; 1247182048Sjhb freq = ((id >> 8) & 0xff) * bus; 1248182048Sjhb volts = id & 0xff; 1249182048Sjhb if (volts != 0) { 1250182048Sjhb volts <<= 4; 1251182048Sjhb volts += 700; 1252182048Sjhb } 1253182048Sjhb fp[1].freq = freq; 1254182048Sjhb fp[1].volts = volts; 1255182048Sjhb fp[1].id16 = id; 1256182048Sjhb fp[1].power = CPUFREQ_VAL_UNKNOWN; 1257182048Sjhb device_printf(dev, "Guessed low setting of %d MHz @ %d Mv\n", freq, 1258182048Sjhb volts); 1259182048Sjhb 1260182048Sjhb /* Table is already terminated due to M_ZERO. */ 1261182048Sjhb sc->msr_settings = TRUE; 1262182048Sjhb *freqs = fp; 1263182048Sjhb return (0); 1264182048Sjhb} 1265182048Sjhb 1266176649Srpaulostatic void 1267176649Srpauloest_get_id16(uint16_t *id16_p) 1268176649Srpaulo{ 1269176649Srpaulo *id16_p = rdmsr(MSR_PERF_STATUS) & 0xffff; 1270176649Srpaulo} 1271176649Srpaulo 1272176649Srpaulostatic int 1273176649Srpauloest_set_id16(device_t dev, uint16_t id16, int need_check) 1274176649Srpaulo{ 1275176649Srpaulo uint64_t msr; 1276176649Srpaulo uint16_t new_id16; 1277176649Srpaulo int ret = 0; 1278176649Srpaulo 1279176649Srpaulo /* Read the current register, mask out the old, set the new id. */ 1280176649Srpaulo msr = rdmsr(MSR_PERF_CTL); 1281176649Srpaulo msr = (msr & ~0xffff) | id16; 1282176649Srpaulo wrmsr(MSR_PERF_CTL, msr); 1283176649Srpaulo 1284176649Srpaulo /* Wait a short while for the new setting. XXX Is this necessary? */ 1285176649Srpaulo DELAY(EST_TRANS_LAT); 1286176649Srpaulo 1287176649Srpaulo if (need_check) { 1288176649Srpaulo est_get_id16(&new_id16); 1289176649Srpaulo if (new_id16 != id16) { 1290176649Srpaulo if (bootverbose) 1291176649Srpaulo device_printf(dev, "Invalid id16 (set, cur) " 1292176649Srpaulo "= (%u, %u)\n", id16, new_id16); 1293176649Srpaulo ret = ENXIO; 1294176649Srpaulo } 1295176649Srpaulo } 1296176649Srpaulo return (ret); 1297176649Srpaulo} 1298176649Srpaulo 1299143902Snjlstatic freq_info * 1300143902Snjlest_get_current(freq_info *freq_list) 1301142140Snjl{ 1302143902Snjl freq_info *f; 1303142140Snjl int i; 1304142140Snjl uint16_t id16; 1305142140Snjl 1306142140Snjl /* 1307142140Snjl * Try a few times to get a valid value. Sometimes, if the CPU 1308142140Snjl * is in the middle of an asynchronous transition (i.e., P4TCC), 1309142140Snjl * we get a temporary invalid result. 1310142140Snjl */ 1311142140Snjl for (i = 0; i < 5; i++) { 1312176649Srpaulo est_get_id16(&id16); 1313142140Snjl for (f = freq_list; f->id16 != 0; f++) { 1314142140Snjl if (f->id16 == id16) 1315142140Snjl return (f); 1316142140Snjl } 1317142140Snjl DELAY(100); 1318142140Snjl } 1319142140Snjl return (NULL); 1320142140Snjl} 1321142140Snjl 1322142140Snjlstatic int 1323142140Snjlest_settings(device_t dev, struct cf_setting *sets, int *count) 1324142140Snjl{ 1325142140Snjl struct est_softc *sc; 1326143902Snjl freq_info *f; 1327142140Snjl int i; 1328142140Snjl 1329142140Snjl sc = device_get_softc(dev); 1330142140Snjl if (*count < EST_MAX_SETTINGS) 1331142140Snjl return (E2BIG); 1332142140Snjl 1333142140Snjl i = 0; 1334142394Snjl for (f = sc->freq_list; f->freq != 0; f++, i++) { 1335142140Snjl sets[i].freq = f->freq; 1336142140Snjl sets[i].volts = f->volts; 1337143902Snjl sets[i].power = f->power; 1338142140Snjl sets[i].lat = EST_TRANS_LAT; 1339142140Snjl sets[i].dev = dev; 1340142140Snjl } 1341142394Snjl *count = i; 1342142140Snjl 1343142140Snjl return (0); 1344142140Snjl} 1345142140Snjl 1346142140Snjlstatic int 1347142140Snjlest_set(device_t dev, const struct cf_setting *set) 1348142140Snjl{ 1349142140Snjl struct est_softc *sc; 1350143902Snjl freq_info *f; 1351142140Snjl 1352142140Snjl /* Find the setting matching the requested one. */ 1353142140Snjl sc = device_get_softc(dev); 1354142140Snjl for (f = sc->freq_list; f->freq != 0; f++) { 1355142140Snjl if (f->freq == set->freq) 1356142140Snjl break; 1357142140Snjl } 1358142140Snjl if (f->freq == 0) 1359142140Snjl return (EINVAL); 1360142140Snjl 1361142140Snjl /* Read the current register, mask out the old, set the new id. */ 1362176649Srpaulo est_set_id16(dev, f->id16, 0); 1363142140Snjl 1364142140Snjl return (0); 1365142140Snjl} 1366142140Snjl 1367142140Snjlstatic int 1368142140Snjlest_get(device_t dev, struct cf_setting *set) 1369142140Snjl{ 1370142140Snjl struct est_softc *sc; 1371143902Snjl freq_info *f; 1372142140Snjl 1373142140Snjl sc = device_get_softc(dev); 1374142140Snjl f = est_get_current(sc->freq_list); 1375142140Snjl if (f == NULL) 1376142140Snjl return (ENXIO); 1377142140Snjl 1378142140Snjl set->freq = f->freq; 1379142140Snjl set->volts = f->volts; 1380143902Snjl set->power = f->power; 1381142140Snjl set->lat = EST_TRANS_LAT; 1382142140Snjl set->dev = dev; 1383142140Snjl return (0); 1384142140Snjl} 1385142140Snjl 1386142140Snjlstatic int 1387142140Snjlest_type(device_t dev, int *type) 1388142140Snjl{ 1389142140Snjl 1390142140Snjl if (type == NULL) 1391142140Snjl return (EINVAL); 1392142140Snjl 1393142140Snjl *type = CPUFREQ_TYPE_ABSOLUTE; 1394142140Snjl return (0); 1395142140Snjl} 1396