est.c revision 144881
10Sstevel@tonic-gate/*- 211038SRao.Shoaib@Sun.COM * Copyright (c) 2004 Colin Percival 30Sstevel@tonic-gate * Copyright (c) 2005 Nate Lawson 40Sstevel@tonic-gate * All rights reserved. 50Sstevel@tonic-gate * 60Sstevel@tonic-gate * Redistribution and use in source and binary forms, with or without 70Sstevel@tonic-gate * modification, are permitted providing that the following conditions 80Sstevel@tonic-gate * are met: 911038SRao.Shoaib@Sun.COM * 1. Redistributions of source code must retain the above copyright 1011038SRao.Shoaib@Sun.COM * notice, this list of conditions and the following disclaimer. 1111038SRao.Shoaib@Sun.COM * 2. Redistributions in binary form must reproduce the above copyright 1211038SRao.Shoaib@Sun.COM * notice, this list of conditions and the following disclaimer in the 1311038SRao.Shoaib@Sun.COM * documentation and/or other materials provided with the distribution. 1411038SRao.Shoaib@Sun.COM * 1511038SRao.Shoaib@Sun.COM * THIS SOFTWARE IS PROVIDED BY THE AUTHOR``AS IS'' AND ANY EXPRESS OR 160Sstevel@tonic-gate * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 170Sstevel@tonic-gate * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 180Sstevel@tonic-gate * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 1911038SRao.Shoaib@Sun.COM * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 200Sstevel@tonic-gate * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 210Sstevel@tonic-gate * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 220Sstevel@tonic-gate * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 230Sstevel@tonic-gate * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 240Sstevel@tonic-gate * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 250Sstevel@tonic-gate * POSSIBILITY OF SUCH DAMAGE. 260Sstevel@tonic-gate */ 270Sstevel@tonic-gate 280Sstevel@tonic-gate#include <sys/cdefs.h> 290Sstevel@tonic-gate__FBSDID("$FreeBSD: head/sys/i386/cpufreq/est.c 144881 2005-04-10 19:57:47Z njl $"); 300Sstevel@tonic-gate 310Sstevel@tonic-gate#include <sys/param.h> 320Sstevel@tonic-gate#include <sys/bus.h> 330Sstevel@tonic-gate#include <sys/cpu.h> 340Sstevel@tonic-gate#include <sys/kernel.h> 350Sstevel@tonic-gate#include <sys/malloc.h> 360Sstevel@tonic-gate#include <sys/module.h> 370Sstevel@tonic-gate#include <sys/smp.h> 380Sstevel@tonic-gate#include <sys/systm.h> 390Sstevel@tonic-gate 400Sstevel@tonic-gate#include "cpufreq_if.h" 410Sstevel@tonic-gate#include <machine/md_var.h> 420Sstevel@tonic-gate 430Sstevel@tonic-gate#include <contrib/dev/acpica/acpi.h> 440Sstevel@tonic-gate#include <dev/acpica/acpivar.h> 450Sstevel@tonic-gate#include "acpi_if.h" 460Sstevel@tonic-gate 470Sstevel@tonic-gate/* Status/control registers (from the IA-32 System Programming Guide). */ 480Sstevel@tonic-gate#define MSR_PERF_STATUS 0x198 490Sstevel@tonic-gate#define MSR_PERF_CTL 0x199 500Sstevel@tonic-gate 510Sstevel@tonic-gate/* Register and bit for enabling SpeedStep. */ 520Sstevel@tonic-gate#define MSR_MISC_ENABLE 0x1a0 530Sstevel@tonic-gate#define MSR_SS_ENABLE (1<<16) 540Sstevel@tonic-gate 550Sstevel@tonic-gate/* Frequency and MSR control values. */ 560Sstevel@tonic-gatetypedef struct { 570Sstevel@tonic-gate uint16_t freq; 580Sstevel@tonic-gate uint16_t volts; 590Sstevel@tonic-gate uint16_t id16; 600Sstevel@tonic-gate int power; 610Sstevel@tonic-gate} freq_info; 620Sstevel@tonic-gate 630Sstevel@tonic-gate/* Identifying characteristics of a processor and supported frequencies. */ 640Sstevel@tonic-gatetypedef struct { 650Sstevel@tonic-gate const char *vendor; 660Sstevel@tonic-gate uint32_t id32; 670Sstevel@tonic-gate uint32_t bus_clk; 680Sstevel@tonic-gate freq_info *freqtab; 690Sstevel@tonic-gate} cpu_info; 700Sstevel@tonic-gate 710Sstevel@tonic-gatestruct est_softc { 720Sstevel@tonic-gate device_t dev; 730Sstevel@tonic-gate int acpi_settings; 740Sstevel@tonic-gate freq_info *freq_list; 750Sstevel@tonic-gate}; 760Sstevel@tonic-gate 770Sstevel@tonic-gate/* Convert MHz and mV into IDs for passing to the MSR. */ 780Sstevel@tonic-gate#define ID16(MHz, mV, bus_clk) \ 7911038SRao.Shoaib@Sun.COM (((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4)) 800Sstevel@tonic-gate#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \ 810Sstevel@tonic-gate ((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk))) 820Sstevel@tonic-gate 830Sstevel@tonic-gate/* Format for storing IDs in our table. */ 840Sstevel@tonic-gate#define FREQ_INFO(MHz, mV, bus_clk) \ 850Sstevel@tonic-gate { MHz, mV, ID16(MHz, mV, bus_clk), CPUFREQ_VAL_UNKNOWN } 860Sstevel@tonic-gate#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \ 870Sstevel@tonic-gate { GenuineIntel, ID32(zhi, vhi, zlo, vlo, bus_clk), bus_clk, tab } 880Sstevel@tonic-gate 890Sstevel@tonic-gateconst char GenuineIntel[] = "GenuineIntel"; 900Sstevel@tonic-gate 910Sstevel@tonic-gate/* Default bus clock value for Centrino processors. */ 920Sstevel@tonic-gate#define INTEL_BUS_CLK 100 930Sstevel@tonic-gate 940Sstevel@tonic-gate/* XXX Update this if new CPUs have more settings. */ 950Sstevel@tonic-gate#define EST_MAX_SETTINGS 10 960Sstevel@tonic-gateCTASSERT(EST_MAX_SETTINGS <= MAX_SETTINGS); 970Sstevel@tonic-gate 980Sstevel@tonic-gate/* Estimate in microseconds of latency for performing a transition. */ 990Sstevel@tonic-gate#define EST_TRANS_LAT 10 1000Sstevel@tonic-gate 1010Sstevel@tonic-gate/* 1020Sstevel@tonic-gate * Frequency (MHz) and voltage (mV) settings. Data from the 1030Sstevel@tonic-gate * Intel Pentium M Processor Datasheet (Order Number 252612), Table 5. 1040Sstevel@tonic-gate * 1050Sstevel@tonic-gate * Dothan processors have multiple VID#s with different settings for 1060Sstevel@tonic-gate * each VID#. Since we can't uniquely identify this info 1070Sstevel@tonic-gate * without undisclosed methods from Intel, we can't support newer 1080Sstevel@tonic-gate * processors with this table method. If ACPI Px states are supported, 1090Sstevel@tonic-gate * we get info from them. 1100Sstevel@tonic-gate */ 1110Sstevel@tonic-gatestatic freq_info PM17_130[] = { 11211038SRao.Shoaib@Sun.COM /* 130nm 1.70GHz Pentium M */ 11311038SRao.Shoaib@Sun.COM FREQ_INFO(1700, 1484, INTEL_BUS_CLK), 11411038SRao.Shoaib@Sun.COM FREQ_INFO(1400, 1308, INTEL_BUS_CLK), 1150Sstevel@tonic-gate FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 1160Sstevel@tonic-gate FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 1170Sstevel@tonic-gate FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 1180Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1190Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1200Sstevel@tonic-gate}; 1210Sstevel@tonic-gatestatic freq_info PM16_130[] = { 1220Sstevel@tonic-gate /* 130nm 1.60GHz Pentium M */ 1230Sstevel@tonic-gate FREQ_INFO(1600, 1484, INTEL_BUS_CLK), 1240Sstevel@tonic-gate FREQ_INFO(1400, 1420, INTEL_BUS_CLK), 1250Sstevel@tonic-gate FREQ_INFO(1200, 1276, INTEL_BUS_CLK), 1260Sstevel@tonic-gate FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 1270Sstevel@tonic-gate FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 12811038SRao.Shoaib@Sun.COM FREQ_INFO( 600, 956, INTEL_BUS_CLK), 12911038SRao.Shoaib@Sun.COM FREQ_INFO( 0, 0, 1), 13011038SRao.Shoaib@Sun.COM}; 1310Sstevel@tonic-gatestatic freq_info PM15_130[] = { 1320Sstevel@tonic-gate /* 130nm 1.50GHz Pentium M */ 1330Sstevel@tonic-gate FREQ_INFO(1500, 1484, INTEL_BUS_CLK), 1340Sstevel@tonic-gate FREQ_INFO(1400, 1452, INTEL_BUS_CLK), 1350Sstevel@tonic-gate FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 1360Sstevel@tonic-gate FREQ_INFO(1000, 1228, INTEL_BUS_CLK), 1370Sstevel@tonic-gate FREQ_INFO( 800, 1116, INTEL_BUS_CLK), 1380Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1390Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1400Sstevel@tonic-gate}; 1410Sstevel@tonic-gatestatic freq_info PM14_130[] = { 1420Sstevel@tonic-gate /* 130nm 1.40GHz Pentium M */ 1430Sstevel@tonic-gate FREQ_INFO(1400, 1484, INTEL_BUS_CLK), 1440Sstevel@tonic-gate FREQ_INFO(1200, 1436, INTEL_BUS_CLK), 14511038SRao.Shoaib@Sun.COM FREQ_INFO(1000, 1308, INTEL_BUS_CLK), 1460Sstevel@tonic-gate FREQ_INFO( 800, 1180, INTEL_BUS_CLK), 1470Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1480Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1490Sstevel@tonic-gate}; 1500Sstevel@tonic-gatestatic freq_info PM13_130[] = { 1510Sstevel@tonic-gate /* 130nm 1.30GHz Pentium M */ 1520Sstevel@tonic-gate FREQ_INFO(1300, 1388, INTEL_BUS_CLK), 1530Sstevel@tonic-gate FREQ_INFO(1200, 1356, INTEL_BUS_CLK), 1540Sstevel@tonic-gate FREQ_INFO(1000, 1292, INTEL_BUS_CLK), 1550Sstevel@tonic-gate FREQ_INFO( 800, 1260, INTEL_BUS_CLK), 1560Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1570Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1580Sstevel@tonic-gate}; 1590Sstevel@tonic-gatestatic freq_info PM13_LV_130[] = { 1600Sstevel@tonic-gate /* 130nm 1.30GHz Low Voltage Pentium M */ 1610Sstevel@tonic-gate FREQ_INFO(1300, 1180, INTEL_BUS_CLK), 1620Sstevel@tonic-gate FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 1630Sstevel@tonic-gate FREQ_INFO(1100, 1100, INTEL_BUS_CLK), 1640Sstevel@tonic-gate FREQ_INFO(1000, 1020, INTEL_BUS_CLK), 1650Sstevel@tonic-gate FREQ_INFO( 900, 1004, INTEL_BUS_CLK), 1660Sstevel@tonic-gate FREQ_INFO( 800, 988, INTEL_BUS_CLK), 1670Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1680Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1690Sstevel@tonic-gate}; 1700Sstevel@tonic-gatestatic freq_info PM12_LV_130[] = { 1710Sstevel@tonic-gate /* 130 nm 1.20GHz Low Voltage Pentium M */ 1720Sstevel@tonic-gate FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 1730Sstevel@tonic-gate FREQ_INFO(1100, 1164, INTEL_BUS_CLK), 1740Sstevel@tonic-gate FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 1750Sstevel@tonic-gate FREQ_INFO( 900, 1020, INTEL_BUS_CLK), 1760Sstevel@tonic-gate FREQ_INFO( 800, 1004, INTEL_BUS_CLK), 1770Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1780Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1790Sstevel@tonic-gate}; 1800Sstevel@tonic-gatestatic freq_info PM11_LV_130[] = { 1810Sstevel@tonic-gate /* 130 nm 1.10GHz Low Voltage Pentium M */ 1820Sstevel@tonic-gate FREQ_INFO(1100, 1180, INTEL_BUS_CLK), 1830Sstevel@tonic-gate FREQ_INFO(1000, 1164, INTEL_BUS_CLK), 1840Sstevel@tonic-gate FREQ_INFO( 900, 1100, INTEL_BUS_CLK), 1850Sstevel@tonic-gate FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 1860Sstevel@tonic-gate FREQ_INFO( 600, 956, INTEL_BUS_CLK), 1870Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1880Sstevel@tonic-gate}; 1890Sstevel@tonic-gatestatic freq_info PM11_ULV_130[] = { 1900Sstevel@tonic-gate /* 130 nm 1.10GHz Ultra Low Voltage Pentium M */ 1910Sstevel@tonic-gate FREQ_INFO(1100, 1004, INTEL_BUS_CLK), 1920Sstevel@tonic-gate FREQ_INFO(1000, 988, INTEL_BUS_CLK), 1930Sstevel@tonic-gate FREQ_INFO( 900, 972, INTEL_BUS_CLK), 1940Sstevel@tonic-gate FREQ_INFO( 800, 956, INTEL_BUS_CLK), 1950Sstevel@tonic-gate FREQ_INFO( 600, 844, INTEL_BUS_CLK), 1960Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 1970Sstevel@tonic-gate}; 1980Sstevel@tonic-gatestatic freq_info PM10_ULV_130[] = { 1990Sstevel@tonic-gate /* 130 nm 1.00GHz Ultra Low Voltage Pentium M */ 2000Sstevel@tonic-gate FREQ_INFO(1000, 1004, INTEL_BUS_CLK), 2010Sstevel@tonic-gate FREQ_INFO( 900, 988, INTEL_BUS_CLK), 2020Sstevel@tonic-gate FREQ_INFO( 800, 972, INTEL_BUS_CLK), 2030Sstevel@tonic-gate FREQ_INFO( 600, 844, INTEL_BUS_CLK), 2040Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 2050Sstevel@tonic-gate}; 2060Sstevel@tonic-gate 2070Sstevel@tonic-gate/* 2080Sstevel@tonic-gate * Data from "Intel Pentium M Processor on 90nm Process with 2090Sstevel@tonic-gate * 2-MB L2 Cache Datasheet", Order Number 302189, Table 5. 2100Sstevel@tonic-gate */ 2110Sstevel@tonic-gatestatic freq_info PM_765A_90[] = { 2120Sstevel@tonic-gate /* 90 nm 2.10GHz Pentium M, VID #A */ 2130Sstevel@tonic-gate FREQ_INFO(2100, 1340, INTEL_BUS_CLK), 2140Sstevel@tonic-gate FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 2150Sstevel@tonic-gate FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 2160Sstevel@tonic-gate FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 2170Sstevel@tonic-gate FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 2180Sstevel@tonic-gate FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 2190Sstevel@tonic-gate FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 2200Sstevel@tonic-gate FREQ_INFO( 600, 988, INTEL_BUS_CLK), 2210Sstevel@tonic-gate FREQ_INFO( 0, 0, 1), 2220Sstevel@tonic-gate}; 22311038SRao.Shoaib@Sun.COMstatic freq_info PM_765B_90[] = { 224 /* 90 nm 2.10GHz Pentium M, VID #B */ 225 FREQ_INFO(2100, 1324, INTEL_BUS_CLK), 226 FREQ_INFO(1800, 1260, INTEL_BUS_CLK), 227 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 228 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 229 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 230 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 231 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 232 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 233 FREQ_INFO( 0, 0, 1), 234}; 235static freq_info PM_765C_90[] = { 236 /* 90 nm 2.10GHz Pentium M, VID #C */ 237 FREQ_INFO(2100, 1308, INTEL_BUS_CLK), 238 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 239 FREQ_INFO(1600, 1212, INTEL_BUS_CLK), 240 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 241 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 242 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 243 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 244 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 245 FREQ_INFO( 0, 0, 1), 246}; 247static freq_info PM_765E_90[] = { 248 /* 90 nm 2.10GHz Pentium M, VID #E */ 249 FREQ_INFO(2100, 1356, INTEL_BUS_CLK), 250 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 251 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 252 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 253 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 254 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 255 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 256 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 257 FREQ_INFO( 0, 0, 1), 258}; 259static freq_info PM_755A_90[] = { 260 /* 90 nm 2.00GHz Pentium M, VID #A */ 261 FREQ_INFO(2000, 1340, INTEL_BUS_CLK), 262 FREQ_INFO(1800, 1292, INTEL_BUS_CLK), 263 FREQ_INFO(1600, 1244, INTEL_BUS_CLK), 264 FREQ_INFO(1400, 1196, INTEL_BUS_CLK), 265 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 266 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 267 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 268 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 269 FREQ_INFO( 0, 0, 1), 270}; 271static freq_info PM_755B_90[] = { 272 /* 90 nm 2.00GHz Pentium M, VID #B */ 273 FREQ_INFO(2000, 1324, INTEL_BUS_CLK), 274 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 275 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 276 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 277 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 278 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 279 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 280 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 281 FREQ_INFO( 0, 0, 1), 282}; 283static freq_info PM_755C_90[] = { 284 /* 90 nm 2.00GHz Pentium M, VID #C */ 285 FREQ_INFO(2000, 1308, INTEL_BUS_CLK), 286 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 287 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 288 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 289 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 290 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 291 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 292 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 293 FREQ_INFO( 0, 0, 1), 294}; 295static freq_info PM_755D_90[] = { 296 /* 90 nm 2.00GHz Pentium M, VID #D */ 297 FREQ_INFO(2000, 1276, INTEL_BUS_CLK), 298 FREQ_INFO(1800, 1244, INTEL_BUS_CLK), 299 FREQ_INFO(1600, 1196, INTEL_BUS_CLK), 300 FREQ_INFO(1400, 1164, INTEL_BUS_CLK), 301 FREQ_INFO(1200, 1116, INTEL_BUS_CLK), 302 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 303 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 304 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 305 FREQ_INFO( 0, 0, 1), 306}; 307static freq_info PM_745A_90[] = { 308 /* 90 nm 1.80GHz Pentium M, VID #A */ 309 FREQ_INFO(1800, 1340, INTEL_BUS_CLK), 310 FREQ_INFO(1600, 1292, INTEL_BUS_CLK), 311 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 312 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 313 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 314 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 315 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 316 FREQ_INFO( 0, 0, 1), 317}; 318static freq_info PM_745B_90[] = { 319 /* 90 nm 1.80GHz Pentium M, VID #B */ 320 FREQ_INFO(1800, 1324, INTEL_BUS_CLK), 321 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 322 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 323 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 324 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 325 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 326 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 327 FREQ_INFO( 0, 0, 1), 328}; 329static freq_info PM_745C_90[] = { 330 /* 90 nm 1.80GHz Pentium M, VID #C */ 331 FREQ_INFO(1800, 1308, INTEL_BUS_CLK), 332 FREQ_INFO(1600, 1260, INTEL_BUS_CLK), 333 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 334 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 335 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 336 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 337 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 338 FREQ_INFO( 0, 0, 1), 339}; 340static freq_info PM_745D_90[] = { 341 /* 90 nm 1.80GHz Pentium M, VID #D */ 342 FREQ_INFO(1800, 1276, INTEL_BUS_CLK), 343 FREQ_INFO(1600, 1228, INTEL_BUS_CLK), 344 FREQ_INFO(1400, 1180, INTEL_BUS_CLK), 345 FREQ_INFO(1200, 1132, INTEL_BUS_CLK), 346 FREQ_INFO(1000, 1084, INTEL_BUS_CLK), 347 FREQ_INFO( 800, 1036, INTEL_BUS_CLK), 348 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 349 FREQ_INFO( 0, 0, 1), 350}; 351static freq_info PM_735A_90[] = { 352 /* 90 nm 1.70GHz Pentium M, VID #A */ 353 FREQ_INFO(1700, 1340, INTEL_BUS_CLK), 354 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 355 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 356 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 357 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 358 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 359 FREQ_INFO( 0, 0, 1), 360}; 361static freq_info PM_735B_90[] = { 362 /* 90 nm 1.70GHz Pentium M, VID #B */ 363 FREQ_INFO(1700, 1324, INTEL_BUS_CLK), 364 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 365 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 366 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 367 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 368 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 369 FREQ_INFO( 0, 0, 1), 370}; 371static freq_info PM_735C_90[] = { 372 /* 90 nm 1.70GHz Pentium M, VID #C */ 373 FREQ_INFO(1700, 1308, INTEL_BUS_CLK), 374 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 375 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 376 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 377 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 378 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 379 FREQ_INFO( 0, 0, 1), 380}; 381static freq_info PM_735D_90[] = { 382 /* 90 nm 1.70GHz Pentium M, VID #D */ 383 FREQ_INFO(1700, 1276, INTEL_BUS_CLK), 384 FREQ_INFO(1400, 1212, INTEL_BUS_CLK), 385 FREQ_INFO(1200, 1148, INTEL_BUS_CLK), 386 FREQ_INFO(1000, 1100, INTEL_BUS_CLK), 387 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 388 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 389 FREQ_INFO( 0, 0, 1), 390}; 391static freq_info PM_725A_90[] = { 392 /* 90 nm 1.60GHz Pentium M, VID #A */ 393 FREQ_INFO(1600, 1340, INTEL_BUS_CLK), 394 FREQ_INFO(1400, 1276, INTEL_BUS_CLK), 395 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 396 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 397 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 398 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 399 FREQ_INFO( 0, 0, 1), 400}; 401static freq_info PM_725B_90[] = { 402 /* 90 nm 1.60GHz Pentium M, VID #B */ 403 FREQ_INFO(1600, 1324, INTEL_BUS_CLK), 404 FREQ_INFO(1400, 1260, INTEL_BUS_CLK), 405 FREQ_INFO(1200, 1196, INTEL_BUS_CLK), 406 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 407 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 408 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 409 FREQ_INFO( 0, 0, 1), 410}; 411static freq_info PM_725C_90[] = { 412 /* 90 nm 1.60GHz Pentium M, VID #C */ 413 FREQ_INFO(1600, 1308, INTEL_BUS_CLK), 414 FREQ_INFO(1400, 1244, INTEL_BUS_CLK), 415 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 416 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 417 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 418 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 419 FREQ_INFO( 0, 0, 1), 420}; 421static freq_info PM_725D_90[] = { 422 /* 90 nm 1.60GHz Pentium M, VID #D */ 423 FREQ_INFO(1600, 1276, INTEL_BUS_CLK), 424 FREQ_INFO(1400, 1228, INTEL_BUS_CLK), 425 FREQ_INFO(1200, 1164, INTEL_BUS_CLK), 426 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 427 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 428 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 429 FREQ_INFO( 0, 0, 1), 430}; 431static freq_info PM_715A_90[] = { 432 /* 90 nm 1.50GHz Pentium M, VID #A */ 433 FREQ_INFO(1500, 1340, INTEL_BUS_CLK), 434 FREQ_INFO(1200, 1228, INTEL_BUS_CLK), 435 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 436 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 437 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 438 FREQ_INFO( 0, 0, 1), 439}; 440static freq_info PM_715B_90[] = { 441 /* 90 nm 1.50GHz Pentium M, VID #B */ 442 FREQ_INFO(1500, 1324, INTEL_BUS_CLK), 443 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 444 FREQ_INFO(1000, 1148, INTEL_BUS_CLK), 445 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 446 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 447 FREQ_INFO( 0, 0, 1), 448}; 449static freq_info PM_715C_90[] = { 450 /* 90 nm 1.50GHz Pentium M, VID #C */ 451 FREQ_INFO(1500, 1308, INTEL_BUS_CLK), 452 FREQ_INFO(1200, 1212, INTEL_BUS_CLK), 453 FREQ_INFO(1000, 1132, INTEL_BUS_CLK), 454 FREQ_INFO( 800, 1068, INTEL_BUS_CLK), 455 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 456 FREQ_INFO( 0, 0, 1), 457}; 458static freq_info PM_715D_90[] = { 459 /* 90 nm 1.50GHz Pentium M, VID #D */ 460 FREQ_INFO(1500, 1276, INTEL_BUS_CLK), 461 FREQ_INFO(1200, 1180, INTEL_BUS_CLK), 462 FREQ_INFO(1000, 1116, INTEL_BUS_CLK), 463 FREQ_INFO( 800, 1052, INTEL_BUS_CLK), 464 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 465 FREQ_INFO( 0, 0, 1), 466}; 467static freq_info PM_738_90[] = { 468 /* 90 nm 1.40GHz Low Voltage Pentium M */ 469 FREQ_INFO(1400, 1116, INTEL_BUS_CLK), 470 FREQ_INFO(1300, 1116, INTEL_BUS_CLK), 471 FREQ_INFO(1200, 1100, INTEL_BUS_CLK), 472 FREQ_INFO(1100, 1068, INTEL_BUS_CLK), 473 FREQ_INFO(1000, 1052, INTEL_BUS_CLK), 474 FREQ_INFO( 900, 1036, INTEL_BUS_CLK), 475 FREQ_INFO( 800, 1020, INTEL_BUS_CLK), 476 FREQ_INFO( 600, 988, INTEL_BUS_CLK), 477 FREQ_INFO( 0, 0, 1), 478}; 479static freq_info PM_733_90[] = { 480 /* 90 nm 1.10GHz Ultra Low Voltage Pentium M */ 481 FREQ_INFO(1100, 940, INTEL_BUS_CLK), 482 FREQ_INFO(1000, 924, INTEL_BUS_CLK), 483 FREQ_INFO( 900, 892, INTEL_BUS_CLK), 484 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 485 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 486 FREQ_INFO( 0, 0, 1), 487}; 488static freq_info PM_723_90[] = { 489 /* 90 nm 1.00GHz Ultra Low Voltage Pentium M */ 490 FREQ_INFO(1000, 940, INTEL_BUS_CLK), 491 FREQ_INFO( 900, 908, INTEL_BUS_CLK), 492 FREQ_INFO( 800, 876, INTEL_BUS_CLK), 493 FREQ_INFO( 600, 812, INTEL_BUS_CLK), 494 FREQ_INFO( 0, 0, 1), 495}; 496 497static cpu_info ESTprocs[] = { 498 INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK), 499 INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK), 500 INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK), 501 INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK), 502 INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK), 503 INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK), 504 INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK), 505 INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK), 506 INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK), 507 INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK), 508 INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK), 509 INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK), 510 INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK), 511 INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK), 512 INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK), 513 INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK), 514 INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK), 515 INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK), 516 INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK), 517 INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK), 518 INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK), 519 INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK), 520 INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK), 521 INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK), 522 INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK), 523 INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK), 524 INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK), 525 INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK), 526 INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK), 527 INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK), 528 INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK), 529 INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK), 530 INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK), 531 INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK), 532 INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK), 533 INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK), 534 INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK), 535 { NULL, 0, 0, NULL }, 536}; 537 538static void est_identify(driver_t *driver, device_t parent); 539static int est_features(driver_t *driver, u_int *features); 540static int est_probe(device_t parent); 541static int est_attach(device_t parent); 542static int est_detach(device_t parent); 543static int est_get_info(device_t dev); 544static int est_acpi_info(device_t dev, freq_info **freqs); 545static int est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk, 546 freq_info **freqs); 547static freq_info *est_get_current(freq_info *freq_list); 548static int est_settings(device_t dev, struct cf_setting *sets, int *count); 549static int est_set(device_t dev, const struct cf_setting *set); 550static int est_get(device_t dev, struct cf_setting *set); 551static int est_type(device_t dev, int *type); 552 553static device_method_t est_methods[] = { 554 /* Device interface */ 555 DEVMETHOD(device_identify, est_identify), 556 DEVMETHOD(device_probe, est_probe), 557 DEVMETHOD(device_attach, est_attach), 558 DEVMETHOD(device_detach, est_detach), 559 560 /* cpufreq interface */ 561 DEVMETHOD(cpufreq_drv_set, est_set), 562 DEVMETHOD(cpufreq_drv_get, est_get), 563 DEVMETHOD(cpufreq_drv_type, est_type), 564 DEVMETHOD(cpufreq_drv_settings, est_settings), 565 566 /* ACPI interface */ 567 DEVMETHOD(acpi_get_features, est_features), 568 569 {0, 0} 570}; 571 572static driver_t est_driver = { 573 "est", 574 est_methods, 575 sizeof(struct est_softc), 576}; 577 578static devclass_t est_devclass; 579DRIVER_MODULE(est, cpu, est_driver, est_devclass, 0, 0); 580 581static int 582est_features(driver_t *driver, u_int *features) 583{ 584 585 /* Notify the ACPI CPU that we support direct access to MSRs */ 586 *features = ACPI_CAP_PERF_MSRS; 587 return (0); 588} 589 590static void 591est_identify(driver_t *driver, device_t parent) 592{ 593 device_t child; 594 u_int p[4]; 595 596 /* Make sure we're not being doubly invoked. */ 597 if (device_find_child(parent, "est", -1) != NULL) 598 return; 599 600 /* Check that CPUID is supported and the vendor is Intel.*/ 601 if (cpu_high == 0 || strcmp(cpu_vendor, GenuineIntel) != 0) 602 return; 603 604 /* Read capability bits and check if the CPU supports EST. */ 605 do_cpuid(1, p); 606 if ((p[2] & 0x80) == 0) 607 return; 608 609 /* 610 * We add a child for each CPU since settings must be performed 611 * on each CPU in the SMP case. 612 */ 613 child = BUS_ADD_CHILD(parent, 0, "est", -1); 614 if (child == NULL) 615 device_printf(parent, "add est child failed\n"); 616} 617 618static int 619est_probe(device_t dev) 620{ 621 device_t perf_dev; 622 uint64_t msr; 623 int error, type; 624 625 if (resource_disabled("est", 0)) 626 return (ENXIO); 627 628 /* 629 * If the ACPI perf driver has attached and is not just offering 630 * info, let it manage things. 631 */ 632 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 633 if (perf_dev && device_is_attached(perf_dev)) { 634 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 635 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 636 return (ENXIO); 637 } 638 639 /* Attempt to enable SpeedStep if not currently enabled. */ 640 msr = rdmsr(MSR_MISC_ENABLE); 641 if ((msr & MSR_SS_ENABLE) == 0) { 642 wrmsr(MSR_MISC_ENABLE, msr | MSR_SS_ENABLE); 643 if (bootverbose) 644 device_printf(dev, "enabling SpeedStep\n"); 645 646 /* Check if the enable failed. */ 647 msr = rdmsr(MSR_MISC_ENABLE); 648 if ((msr & MSR_SS_ENABLE) == 0) { 649 device_printf(dev, "failed to enable SpeedStep\n"); 650 return (ENXIO); 651 } 652 } 653 654 device_set_desc(dev, "Enhanced SpeedStep Frequency Control"); 655 return (0); 656} 657 658static int 659est_attach(device_t dev) 660{ 661 struct est_softc *sc; 662 663 sc = device_get_softc(dev); 664 sc->dev = dev; 665 666 /* Check CPU for supported settings. */ 667 if (est_get_info(dev)) 668 return (ENXIO); 669 670 cpufreq_register(dev); 671 return (0); 672} 673 674static int 675est_detach(device_t dev) 676{ 677 struct est_softc *sc; 678 679 sc = device_get_softc(dev); 680 if (sc->acpi_settings) 681 free(sc->freq_list, M_DEVBUF); 682 return (ENXIO); 683} 684 685/* 686 * Probe for supported CPU settings. First, check our static table of 687 * settings. If no match, try using the ones offered by acpi_perf 688 * (i.e., _PSS). We use ACPI second because some systems (IBM R/T40 689 * series) export both legacy SMM IO-based access and direct MSR access 690 * but the direct access specifies invalid values for _PSS. 691 */ 692static int 693est_get_info(device_t dev) 694{ 695 struct est_softc *sc; 696 uint64_t msr; 697 int error; 698 699 sc = device_get_softc(dev); 700 msr = rdmsr(MSR_PERF_STATUS); 701 error = est_table_info(dev, msr, INTEL_BUS_CLK, &sc->freq_list); 702 if (error) 703 error = est_acpi_info(dev, &sc->freq_list); 704 705 if (error) { 706 printf( 707 "est: CPU supports Enhanced Speedstep, but is not recognized.\n" 708 "est: Please update driver or contact the maintainer.\n" 709 "est: cpu_vendor %s, msr %0jx, bus_clk, %x\n", 710 cpu_vendor, msr, INTEL_BUS_CLK); 711 return (ENXIO); 712 } 713 714 return (0); 715} 716 717static int 718est_acpi_info(device_t dev, freq_info **freqs) 719{ 720 struct est_softc *sc; 721 struct cf_setting *sets; 722 freq_info *table; 723 device_t perf_dev; 724 int count, error, i; 725 726 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 727 if (perf_dev == NULL || !device_is_attached(perf_dev)) 728 return (ENXIO); 729 730 /* Fetch settings from acpi_perf. */ 731 sc = device_get_softc(dev); 732 table = NULL; 733 sets = malloc(MAX_SETTINGS * sizeof(*sets), M_TEMP, M_NOWAIT); 734 if (sets == NULL) 735 return (ENOMEM); 736 error = CPUFREQ_DRV_SETTINGS(perf_dev, sets, &count); 737 if (error) 738 goto out; 739 740 /* Parse settings into our local table format. */ 741 table = malloc((count + 1) * sizeof(freq_info), M_DEVBUF, M_NOWAIT); 742 if (table == NULL) { 743 error = ENOMEM; 744 goto out; 745 } 746 for (i = 0; i < count; i++) { 747 /* 748 * TODO: Figure out validity checks for id16. Linux checks 749 * that the control and status values match. 750 */ 751 table[i].freq = sets[i].freq; 752 table[i].volts = sets[i].volts; 753 table[i].id16 = sets[i].spec[0]; 754 table[i].power = sets[i].power; 755 } 756 757 /* Mark end of table with a terminator. */ 758 bzero(&table[i], sizeof(freq_info)); 759 760 sc->acpi_settings = TRUE; 761 *freqs = table; 762 error = 0; 763 764out: 765 if (sets) 766 free(sets, M_TEMP); 767 if (error && table) 768 free(table, M_DEVBUF); 769 return (error); 770} 771 772static int 773est_table_info(device_t dev, uint64_t msr, uint32_t bus_clk, freq_info **freqs) 774{ 775 cpu_info *p; 776 uint32_t id; 777 778 /* Find a table which matches (vendor, id, bus_clk). */ 779 id = msr >> 32; 780 for (p = ESTprocs; p->id32 != 0; p++) { 781 if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id && 782 p->bus_clk == bus_clk) 783 break; 784 } 785 if (p->id32 == 0) 786 return (EOPNOTSUPP); 787 788 /* Make sure the current setpoint is valid. */ 789 if (est_get_current(p->freqtab) == NULL) { 790 device_printf(dev, "current setting not found in table\n"); 791 return (EOPNOTSUPP); 792 } 793 794 *freqs = p->freqtab; 795 return (0); 796} 797 798static freq_info * 799est_get_current(freq_info *freq_list) 800{ 801 freq_info *f; 802 int i; 803 uint16_t id16; 804 805 /* 806 * Try a few times to get a valid value. Sometimes, if the CPU 807 * is in the middle of an asynchronous transition (i.e., P4TCC), 808 * we get a temporary invalid result. 809 */ 810 for (i = 0; i < 5; i++) { 811 id16 = rdmsr(MSR_PERF_STATUS) & 0xffff; 812 for (f = freq_list; f->id16 != 0; f++) { 813 if (f->id16 == id16) 814 return (f); 815 } 816 DELAY(100); 817 } 818 return (NULL); 819} 820 821static int 822est_settings(device_t dev, struct cf_setting *sets, int *count) 823{ 824 struct est_softc *sc; 825 freq_info *f; 826 int i; 827 828 sc = device_get_softc(dev); 829 if (*count < EST_MAX_SETTINGS) 830 return (E2BIG); 831 832 i = 0; 833 for (f = sc->freq_list; f->freq != 0; f++, i++) { 834 sets[i].freq = f->freq; 835 sets[i].volts = f->volts; 836 sets[i].power = f->power; 837 sets[i].lat = EST_TRANS_LAT; 838 sets[i].dev = dev; 839 } 840 *count = i; 841 842 return (0); 843} 844 845static int 846est_set(device_t dev, const struct cf_setting *set) 847{ 848 struct est_softc *sc; 849 freq_info *f; 850 uint64_t msr; 851 852 /* Find the setting matching the requested one. */ 853 sc = device_get_softc(dev); 854 for (f = sc->freq_list; f->freq != 0; f++) { 855 if (f->freq == set->freq) 856 break; 857 } 858 if (f->freq == 0) 859 return (EINVAL); 860 861 /* Read the current register, mask out the old, set the new id. */ 862 msr = rdmsr(MSR_PERF_CTL); 863 msr = (msr & ~0xffff) | f->id16; 864 wrmsr(MSR_PERF_CTL, msr); 865 866 /* Wait a short while for the new setting. XXX Is this necessary? */ 867 DELAY(EST_TRANS_LAT); 868 869 return (0); 870} 871 872static int 873est_get(device_t dev, struct cf_setting *set) 874{ 875 struct est_softc *sc; 876 freq_info *f; 877 878 sc = device_get_softc(dev); 879 f = est_get_current(sc->freq_list); 880 if (f == NULL) 881 return (ENXIO); 882 883 set->freq = f->freq; 884 set->volts = f->volts; 885 set->power = f->power; 886 set->lat = EST_TRANS_LAT; 887 set->dev = dev; 888 return (0); 889} 890 891static int 892est_type(device_t dev, int *type) 893{ 894 895 if (type == NULL) 896 return (EINVAL); 897 898 *type = CPUFREQ_TYPE_ABSOLUTE; 899 return (0); 900} 901