ofw_pcibus.c revision 174117
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000, BSDi 5 * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice unmodified, this list of conditions, and the following 13 * disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: head/sys/sparc64/pci/ofw_pcibus.c 174117 2007-11-30 23:02:42Z marius $"); 32 33#include "opt_ofw_pci.h" 34 35#include <sys/param.h> 36#include <sys/bus.h> 37#include <sys/kernel.h> 38#include <sys/libkern.h> 39#include <sys/module.h> 40#include <sys/pciio.h> 41 42#include <dev/ofw/ofw_bus.h> 43#include <dev/ofw/ofw_bus_subr.h> 44#include <dev/ofw/ofw_pci.h> 45#include <dev/ofw/openfirm.h> 46 47#include <machine/bus.h> 48#include <machine/bus_common.h> 49#ifndef SUN4V 50#include <machine/iommureg.h> 51#endif 52#include <machine/resource.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pci_private.h> 57 58#include <sparc64/pci/ofw_pci.h> 59 60#include "pcib_if.h" 61#include "pci_if.h" 62 63/* Helper functions. */ 64static void ofw_pcibus_setup_device(device_t, u_int, u_int, u_int); 65 66/* Methods. */ 67static device_probe_t ofw_pcibus_probe; 68static device_attach_t ofw_pcibus_attach; 69static pci_assign_interrupt_t ofw_pcibus_assign_interrupt; 70static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo; 71 72static device_method_t ofw_pcibus_methods[] = { 73 /* Device interface */ 74 DEVMETHOD(device_probe, ofw_pcibus_probe), 75 DEVMETHOD(device_attach, ofw_pcibus_attach), 76 77 /* Bus interface */ 78 79 /* PCI interface */ 80 DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt), 81 82 /* ofw_bus interface */ 83 DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo), 84 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 85 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 86 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 87 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 88 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 89 90 { 0, 0 } 91}; 92 93struct ofw_pcibus_devinfo { 94 struct pci_devinfo opd_dinfo; 95 struct ofw_bus_devinfo opd_obdinfo; 96}; 97 98static devclass_t pci_devclass; 99 100DEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */, 101 pci_driver); 102DRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0); 103MODULE_VERSION(ofw_pcibus, 1); 104MODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1); 105 106static int 107ofw_pcibus_probe(device_t dev) 108{ 109 110 if (ofw_bus_get_node(dev) == 0) 111 return (ENXIO); 112 device_set_desc(dev, "OFW PCI bus"); 113 114 return (0); 115} 116 117/* 118 * Perform miscellaneous setups the firmware usually does not do for us. 119 */ 120static void 121ofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func) 122{ 123 uint32_t reg; 124 125 /* 126 * Initialize the latency timer register for busmaster devices to work 127 * properly. This is another task which the firmware does not always 128 * perform. The Min_Gnt register can be used to compute it's recommended 129 * value: it contains the desired latency in units of 1/4 us. To 130 * calculate the correct latency timer value, the clock frequency of 131 * the bus (defaulting to 33Mhz) should be used and no wait states 132 * should be assumed. 133 */ 134 if (OF_getprop(ofw_bus_get_node(bridge), "clock-frequency", ®, 135 sizeof(reg)) == -1) 136 reg = 33000000; 137 reg = PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_MINGNT, 1) * 138 reg / 1000000 / 4; 139 if (reg != 0) { 140#ifdef OFW_PCI_DEBUG 141 device_printf(bridge, "device %d/%d/%d: latency timer %d -> " 142 "%d\n", busno, slot, func, 143 PCIB_READ_CONFIG(bridge, busno, slot, func, 144 PCIR_LATTIMER, 1), reg); 145#endif /* OFW_PCI_DEBUG */ 146 PCIB_WRITE_CONFIG(bridge, busno, slot, func, 147 PCIR_LATTIMER, min(reg, 255), 1); 148 } 149 150#ifndef SUN4V 151 /* 152 * Compute a value to write into the cache line size register. 153 * The role of the streaming cache is unclear in write invalidate 154 * transfers, so it is made sure that it's line size is always reached. 155 * Generally, the cache line size is fixed at 64 bytes by Fireplane/ 156 * Safari, JBus and UPA. 157 */ 158 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ, 159 STRBUF_LINESZ / sizeof(uint32_t), 1); 160#endif 161 162 /* 163 * The preset in the intline register is usually wrong. Reset it to 255, 164 * so that the PCI code will reroute the interrupt if needed. 165 */ 166 PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE, 167 PCI_INVALID_IRQ, 1); 168} 169 170static int 171ofw_pcibus_attach(device_t dev) 172{ 173 device_t pcib; 174 struct ofw_pci_register pcir; 175 struct ofw_pcibus_devinfo *dinfo; 176 phandle_t node, child; 177 u_int busno, domain, func, slot; 178 179 pcib = device_get_parent(dev); 180 181 domain = pcib_get_domain(dev); 182 /* 183 * Ask the bridge for the bus number - in some cases, we need to 184 * renumber buses, so the firmware information cannot be trusted. 185 */ 186 busno = pcib_get_bus(dev); 187 if (bootverbose) 188 device_printf(dev, "domain=%d, physical bus=%d\n", 189 domain, busno); 190 191 node = ofw_bus_get_node(dev); 192 193#ifndef SUN4V 194 /* Add the PCI side of the HOST-PCI bridge itself to the bus. */ 195 if (strcmp(device_get_name(device_get_parent(pcib)), "nexus") == 0 && 196 (dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, 197 domain, busno, 0, 0, sizeof(*dinfo))) != NULL) { 198 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, node) != 0) 199 pci_freecfg((struct pci_devinfo *)dinfo); 200 else 201 pci_add_child(dev, (struct pci_devinfo *)dinfo); 202 } 203#endif 204 205 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 206 if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1) 207 continue; 208 slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 209 func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 210 /* Some OFW device trees contain dupes. */ 211 if (pci_find_dbsf(domain, busno, slot, func) != NULL) 212 continue; 213 ofw_pcibus_setup_device(pcib, busno, slot, func); 214 dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, 215 domain, busno, slot, func, sizeof(*dinfo)); 216 if (dinfo == NULL) 217 continue; 218 if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 219 0) { 220 pci_freecfg((struct pci_devinfo *)dinfo); 221 continue; 222 } 223 pci_add_child(dev, (struct pci_devinfo *)dinfo); 224 } 225 226 return (bus_generic_attach(dev)); 227} 228 229static int 230ofw_pcibus_assign_interrupt(device_t dev, device_t child) 231{ 232 ofw_pci_intr_t intr; 233 int isz; 234 235 isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr, 236 sizeof(intr)); 237 if (isz != sizeof(intr)) { 238 /* No property; our best guess is the intpin. */ 239 intr = pci_get_intpin(child); 240 } else if (intr >= 255) { 241 /* 242 * A fully specified interrupt (including IGN), as present on 243 * SPARCengine Ultra AX and e450. Extract the INO and return it. 244 */ 245 return (INTINO(intr)); 246 } 247 /* 248 * If we got intr from a property, it may or may not be an intpin. 249 * For on-board devices, it frequently is not, and is completely out 250 * of the valid intpin range. For PCI slots, it hopefully is, otherwise 251 * we will have trouble interfacing with non-OFW buses such as cardbus. 252 * Since we cannot tell which it is without violating layering, we 253 * will always use the route_interrupt method, and treat exceptions on 254 * the level they become apparent. 255 */ 256 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr)); 257} 258 259static const struct ofw_bus_devinfo * 260ofw_pcibus_get_devinfo(device_t bus, device_t dev) 261{ 262 struct ofw_pcibus_devinfo *dinfo; 263 264 dinfo = device_get_ivars(dev); 265 return (&dinfo->opd_obdinfo); 266} 267