ofw_pcibus.c revision 172394
1117119Stmm/*- 2117119Stmm * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3117119Stmm * Copyright (c) 2000, Michael Smith <msmith@freebsd.org> 4117119Stmm * Copyright (c) 2000, BSDi 5117119Stmm * Copyright (c) 2003, Thomas Moestl <tmm@FreeBSD.org> 6117119Stmm * All rights reserved. 7117119Stmm * 8117119Stmm * Redistribution and use in source and binary forms, with or without 9117119Stmm * modification, are permitted provided that the following conditions 10117119Stmm * are met: 11117119Stmm * 1. Redistributions of source code must retain the above copyright 12117119Stmm * notice unmodified, this list of conditions, and the following 13117119Stmm * disclaimer. 14117119Stmm * 2. Redistributions in binary form must reproduce the above copyright 15117119Stmm * notice, this list of conditions and the following disclaimer in the 16117119Stmm * documentation and/or other materials provided with the distribution. 17117119Stmm * 18117119Stmm * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19117119Stmm * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20117119Stmm * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21117119Stmm * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22117119Stmm * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23117119Stmm * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24117119Stmm * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25117119Stmm * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26117119Stmm * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27117119Stmm * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28117119Stmm */ 29117119Stmm 30152684Smarius#include <sys/cdefs.h> 31152684Smarius__FBSDID("$FreeBSD: head/sys/sparc64/pci/ofw_pcibus.c 172394 2007-09-30 11:05:18Z marius $"); 32152684Smarius 33117119Stmm#include "opt_ofw_pci.h" 34133589Smarius 35117119Stmm#include <sys/param.h> 36117119Stmm#include <sys/bus.h> 37117119Stmm#include <sys/kernel.h> 38117119Stmm#include <sys/libkern.h> 39117119Stmm#include <sys/module.h> 40117119Stmm#include <sys/pciio.h> 41117119Stmm 42133589Smarius#include <dev/ofw/ofw_bus.h> 43152684Smarius#include <dev/ofw/ofw_bus_subr.h> 44133589Smarius#include <dev/ofw/ofw_pci.h> 45117119Stmm#include <dev/ofw/openfirm.h> 46117119Stmm 47117119Stmm#include <machine/bus.h> 48117119Stmm#include <machine/bus_common.h> 49163146Skmacy#ifndef SUN4V 50169793Smarius#include <machine/iommureg.h> 51163146Skmacy#endif 52117119Stmm#include <machine/resource.h> 53117119Stmm 54117119Stmm#include <dev/pci/pcireg.h> 55117119Stmm#include <dev/pci/pcivar.h> 56117119Stmm#include <dev/pci/pci_private.h> 57117119Stmm 58117119Stmm#include <sparc64/pci/ofw_pci.h> 59117119Stmm 60117119Stmm#include "pcib_if.h" 61117119Stmm#include "pci_if.h" 62117119Stmm 63117119Stmm/* Helper functions. */ 64117119Stmmstatic void ofw_pcibus_setup_device(device_t, u_int, u_int, u_int); 65117119Stmm 66117119Stmm/* Methods. */ 67117119Stmmstatic device_probe_t ofw_pcibus_probe; 68117119Stmmstatic device_attach_t ofw_pcibus_attach; 69117119Stmmstatic pci_assign_interrupt_t ofw_pcibus_assign_interrupt; 70152684Smariusstatic ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo; 71117119Stmm 72117119Stmmstatic device_method_t ofw_pcibus_methods[] = { 73117119Stmm /* Device interface */ 74117119Stmm DEVMETHOD(device_probe, ofw_pcibus_probe), 75117119Stmm DEVMETHOD(device_attach, ofw_pcibus_attach), 76117119Stmm 77117119Stmm /* Bus interface */ 78117119Stmm 79117119Stmm /* PCI interface */ 80117119Stmm DEVMETHOD(pci_assign_interrupt, ofw_pcibus_assign_interrupt), 81117119Stmm 82133589Smarius /* ofw_bus interface */ 83152684Smarius DEVMETHOD(ofw_bus_get_devinfo, ofw_pcibus_get_devinfo), 84152684Smarius DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 85152684Smarius DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 86152684Smarius DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 87152684Smarius DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 88152684Smarius DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 89117119Stmm 90117119Stmm { 0, 0 } 91117119Stmm}; 92117119Stmm 93117119Stmmstruct ofw_pcibus_devinfo { 94117119Stmm struct pci_devinfo opd_dinfo; 95152684Smarius struct ofw_bus_devinfo opd_obdinfo; 96117119Stmm}; 97117119Stmm 98154600Sjhbstatic devclass_t pci_devclass; 99117119Stmm 100170887SmariusDEFINE_CLASS_1(pci, ofw_pcibus_driver, ofw_pcibus_methods, 1 /* no softc */, 101170887Smarius pci_driver); 102117119StmmDRIVER_MODULE(ofw_pcibus, pcib, ofw_pcibus_driver, pci_devclass, 0, 0); 103117119StmmMODULE_VERSION(ofw_pcibus, 1); 104117119StmmMODULE_DEPEND(ofw_pcibus, pci, 1, 1, 1); 105117119Stmm 106117119Stmmstatic int 107117119Stmmofw_pcibus_probe(device_t dev) 108117119Stmm{ 109117119Stmm 110133589Smarius if (ofw_bus_get_node(dev) == 0) 111117119Stmm return (ENXIO); 112117119Stmm device_set_desc(dev, "OFW PCI bus"); 113117119Stmm 114117119Stmm return (0); 115117119Stmm} 116117119Stmm 117117119Stmm/* 118117119Stmm * Perform miscellaneous setups the firmware usually does not do for us. 119117119Stmm */ 120117119Stmmstatic void 121117119Stmmofw_pcibus_setup_device(device_t bridge, u_int busno, u_int slot, u_int func) 122117119Stmm{ 123172333Smarius uint32_t reg; 124172333Smarius 125117119Stmm /* 126117119Stmm * Initialize the latency timer register for busmaster devices to work 127117119Stmm * properly. This is another task which the firmware does not always 128117119Stmm * perform. The Min_Gnt register can be used to compute it's recommended 129117119Stmm * value: it contains the desired latency in units of 1/4 us. To 130172333Smarius * calculate the correct latency timer value, the clock frequency of 131172333Smarius * the bus (defaulting to 33Mhz) should be used and no wait states 132172333Smarius * should be assumed. 133117119Stmm */ 134172333Smarius if (OF_getprop(ofw_bus_get_node(bridge), "clock-frequency", ®, 135172333Smarius sizeof(reg)) == -1) 136172333Smarius reg = 33000000; 137172333Smarius reg = PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_MINGNT, 1) * 138172333Smarius reg / 1000000 / 4; 139172333Smarius if (reg != 0) { 140117119Stmm#ifdef OFW_PCI_DEBUG 141117119Stmm device_printf(bridge, "device %d/%d/%d: latency timer %d -> " 142117119Stmm "%d\n", busno, slot, func, 143117119Stmm PCIB_READ_CONFIG(bridge, busno, slot, func, 144172333Smarius PCIR_LATTIMER, 1), reg); 145117119Stmm#endif /* OFW_PCI_DEBUG */ 146117119Stmm PCIB_WRITE_CONFIG(bridge, busno, slot, func, 147172333Smarius PCIR_LATTIMER, min(reg, 255), 1); 148117119Stmm } 149117119Stmm 150163146Skmacy#ifndef SUN4V 151117119Stmm /* 152117119Stmm * Compute a value to write into the cache line size register. 153117119Stmm * The role of the streaming cache is unclear in write invalidate 154117119Stmm * transfers, so it is made sure that it's line size is always reached. 155172333Smarius * Generally, the cache line size is fixed at 64 bytes by Fireplane/ 156172333Smarius * Safari, JBus and UPA. 157117119Stmm */ 158117119Stmm PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ, 159172333Smarius STRBUF_LINESZ / sizeof(uint32_t), 1); 160169793Smarius#endif 161117119Stmm 162117119Stmm /* 163117119Stmm * The preset in the intline register is usually wrong. Reset it to 255, 164117119Stmm * so that the PCI code will reroute the interrupt if needed. 165117119Stmm */ 166117119Stmm PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE, 167117119Stmm PCI_INVALID_IRQ, 1); 168117119Stmm} 169117119Stmm 170117119Stmmstatic int 171117119Stmmofw_pcibus_attach(device_t dev) 172117119Stmm{ 173153057Smarius device_t pcib; 174117119Stmm struct ofw_pci_register pcir; 175117119Stmm struct ofw_pcibus_devinfo *dinfo; 176117119Stmm phandle_t node, child; 177172394Smarius u_int busno, domain, func, slot; 178117119Stmm 179153057Smarius pcib = device_get_parent(dev); 180153057Smarius 181172394Smarius domain = pcib_get_domain(dev); 182117119Stmm /* 183117119Stmm * Ask the bridge for the bus number - in some cases, we need to 184117119Stmm * renumber buses, so the firmware information cannot be trusted. 185117119Stmm */ 186117119Stmm busno = pcib_get_bus(dev); 187117119Stmm if (bootverbose) 188172394Smarius device_printf(dev, "domain=%d, physical bus=%d\n", 189172394Smarius domain, busno); 190117119Stmm 191133589Smarius node = ofw_bus_get_node(dev); 192117119Stmm for (child = OF_child(node); child != 0; child = OF_peer(child)) { 193152684Smarius if (OF_getprop(child, "reg", &pcir, sizeof(pcir)) == -1) 194140512Smarius continue; 195117119Stmm slot = OFW_PCI_PHYS_HI_DEVICE(pcir.phys_hi); 196117119Stmm func = OFW_PCI_PHYS_HI_FUNCTION(pcir.phys_hi); 197172394Smarius /* Some OFW device trees contain dupes. */ 198172394Smarius if (pci_find_dbsf(domain, busno, slot, func) != NULL) 199165885Smarius continue; 200117119Stmm ofw_pcibus_setup_device(pcib, busno, slot, func); 201117119Stmm dinfo = (struct ofw_pcibus_devinfo *)pci_read_device(pcib, 202172394Smarius domain, busno, slot, func, sizeof(*dinfo)); 203152684Smarius if (dinfo == NULL) 204152684Smarius continue; 205152684Smarius if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 206152684Smarius 0) { 207152684Smarius pci_freecfg((struct pci_devinfo *)dinfo); 208152684Smarius continue; 209152684Smarius } 210152684Smarius pci_add_child(dev, (struct pci_devinfo *)dinfo); 211117119Stmm } 212117119Stmm 213117119Stmm return (bus_generic_attach(dev)); 214117119Stmm} 215117119Stmm 216117119Stmmstatic int 217117119Stmmofw_pcibus_assign_interrupt(device_t dev, device_t child) 218117119Stmm{ 219117119Stmm ofw_pci_intr_t intr; 220117119Stmm int isz; 221117119Stmm 222152684Smarius isz = OF_getprop(ofw_bus_get_node(child), "interrupts", &intr, 223152684Smarius sizeof(intr)); 224117119Stmm if (isz != sizeof(intr)) { 225117119Stmm /* No property; our best guess is the intpin. */ 226152684Smarius intr = pci_get_intpin(child); 227117119Stmm } else if (intr >= 255) { 228117119Stmm /* 229117119Stmm * A fully specified interrupt (including IGN), as present on 230117119Stmm * SPARCengine Ultra AX and e450. Extract the INO and return it. 231117119Stmm */ 232117119Stmm return (INTINO(intr)); 233117119Stmm } 234117119Stmm /* 235117119Stmm * If we got intr from a property, it may or may not be an intpin. 236117119Stmm * For on-board devices, it frequently is not, and is completely out 237117119Stmm * of the valid intpin range. For PCI slots, it hopefully is, otherwise 238117119Stmm * we will have trouble interfacing with non-OFW buses such as cardbus. 239117119Stmm * Since we cannot tell which it is without violating layering, we 240117119Stmm * will always use the route_interrupt method, and treat exceptions on 241117119Stmm * the level they become apparent. 242117119Stmm */ 243117119Stmm return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child, intr)); 244117119Stmm} 245117119Stmm 246152684Smariusstatic const struct ofw_bus_devinfo * 247152684Smariusofw_pcibus_get_devinfo(device_t bus, device_t dev) 248133589Smarius{ 249133589Smarius struct ofw_pcibus_devinfo *dinfo; 250133589Smarius 251133589Smarius dinfo = device_get_ivars(dev); 252152684Smarius return (&dinfo->opd_obdinfo); 253133589Smarius} 254