platform_mpc85xx.c revision 224611
1192067Snwhitehorn/*- 2192067Snwhitehorn * Copyright (c) 2008-2009 Semihalf, Rafal Jaworowski 3192067Snwhitehorn * All rights reserved. 4192067Snwhitehorn * 5192067Snwhitehorn * Redistribution and use in source and binary forms, with or without 6192067Snwhitehorn * modification, are permitted provided that the following conditions 7192067Snwhitehorn * are met: 8192067Snwhitehorn * 9192067Snwhitehorn * 1. Redistributions of source code must retain the above copyright 10192067Snwhitehorn * notice, this list of conditions and the following disclaimer. 11192067Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 12192067Snwhitehorn * notice, this list of conditions and the following disclaimer in the 13192067Snwhitehorn * documentation and/or other materials provided with the distribution. 14192067Snwhitehorn * 15192067Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16192067Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17192067Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18192067Snwhitehorn * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19192067Snwhitehorn * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20192067Snwhitehorn * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21192067Snwhitehorn * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22192067Snwhitehorn * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23192067Snwhitehorn * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24192067Snwhitehorn * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25192067Snwhitehorn */ 26192067Snwhitehorn 27192067Snwhitehorn#include <sys/cdefs.h> 28192067Snwhitehorn__FBSDID("$FreeBSD: head/sys/powerpc/booke/platform_bare.c 224611 2011-08-02 15:35:43Z marcel $"); 29192067Snwhitehorn 30192067Snwhitehorn#include <sys/param.h> 31192067Snwhitehorn#include <sys/systm.h> 32192067Snwhitehorn#include <sys/kernel.h> 33192067Snwhitehorn#include <sys/bus.h> 34192067Snwhitehorn#include <sys/pcpu.h> 35192067Snwhitehorn#include <sys/proc.h> 36192067Snwhitehorn#include <sys/smp.h> 37192067Snwhitehorn 38192067Snwhitehorn#include <machine/bus.h> 39192067Snwhitehorn#include <machine/cpu.h> 40192067Snwhitehorn#include <machine/hid.h> 41192067Snwhitehorn#include <machine/platform.h> 42192067Snwhitehorn#include <machine/platformvar.h> 43192067Snwhitehorn#include <machine/smp.h> 44192067Snwhitehorn#include <machine/spr.h> 45192067Snwhitehorn#include <machine/vmparam.h> 46192067Snwhitehorn 47209908Sraj#include <dev/fdt/fdt_common.h> 48209908Sraj#include <dev/ofw/ofw_bus.h> 49209908Sraj#include <dev/ofw/ofw_bus_subr.h> 50209908Sraj#include <dev/ofw/openfirm.h> 51209908Sraj 52192067Snwhitehorn#include <powerpc/mpc85xx/mpc85xx.h> 53192067Snwhitehorn 54192067Snwhitehorn#include "platform_if.h" 55192067Snwhitehorn 56192532Sraj#ifdef SMP 57192532Srajextern void *ap_pcpu; 58192532Srajextern uint8_t __boot_page[]; /* Boot page body */ 59192532Srajextern uint32_t kernload_ap; /* Kernel physical load address */ 60192532Sraj#endif 61192532Sraj 62217523Smarcelextern uint32_t *bootinfo; 63217523Smarcel 64193492Srajstatic int cpu, maxcpu; 65192067Snwhitehorn 66192067Snwhitehornstatic int bare_probe(platform_t); 67192067Snwhitehornstatic void bare_mem_regions(platform_t, struct mem_region **phys, int *physsz, 68192067Snwhitehorn struct mem_region **avail, int *availsz); 69192067Snwhitehornstatic u_long bare_timebase_freq(platform_t, struct cpuref *cpuref); 70192067Snwhitehornstatic int bare_smp_first_cpu(platform_t, struct cpuref *cpuref); 71192067Snwhitehornstatic int bare_smp_next_cpu(platform_t, struct cpuref *cpuref); 72192067Snwhitehornstatic int bare_smp_get_bsp(platform_t, struct cpuref *cpuref); 73192067Snwhitehornstatic int bare_smp_start_cpu(platform_t, struct pcpu *cpu); 74192067Snwhitehorn 75212054Snwhitehornstatic void e500_reset(platform_t); 76212054Snwhitehorn 77192067Snwhitehornstatic platform_method_t bare_methods[] = { 78192067Snwhitehorn PLATFORMMETHOD(platform_probe, bare_probe), 79192067Snwhitehorn PLATFORMMETHOD(platform_mem_regions, bare_mem_regions), 80192067Snwhitehorn PLATFORMMETHOD(platform_timebase_freq, bare_timebase_freq), 81192067Snwhitehorn 82192067Snwhitehorn PLATFORMMETHOD(platform_smp_first_cpu, bare_smp_first_cpu), 83192067Snwhitehorn PLATFORMMETHOD(platform_smp_next_cpu, bare_smp_next_cpu), 84192067Snwhitehorn PLATFORMMETHOD(platform_smp_get_bsp, bare_smp_get_bsp), 85192067Snwhitehorn PLATFORMMETHOD(platform_smp_start_cpu, bare_smp_start_cpu), 86192067Snwhitehorn 87212453Smav PLATFORMMETHOD(platform_reset, e500_reset), 88212054Snwhitehorn 89192067Snwhitehorn { 0, 0 } 90192067Snwhitehorn}; 91192067Snwhitehorn 92192067Snwhitehornstatic platform_def_t bare_platform = { 93192067Snwhitehorn "bare metal", 94192067Snwhitehorn bare_methods, 95192067Snwhitehorn 0 96192067Snwhitehorn}; 97192067Snwhitehorn 98192067SnwhitehornPLATFORM_DEF(bare_platform); 99192067Snwhitehorn 100192067Snwhitehornstatic int 101192067Snwhitehornbare_probe(platform_t plat) 102192067Snwhitehorn{ 103209908Sraj uint32_t ver, sr; 104209908Sraj int i, law_max, tgt; 105192067Snwhitehorn 106193492Sraj ver = SVR_VER(mfspr(SPR_SVR)); 107193492Sraj switch (ver & ~0x0008) { /* Mask Security Enabled bit */ 108193492Sraj case SVR_P4080: 109193492Sraj maxcpu = 8; 110193492Sraj break; 111193492Sraj case SVR_P4040: 112209908Sraj maxcpu = 4; 113209908Sraj break; 114209908Sraj case SVR_MPC8572: 115209908Sraj case SVR_P1020: 116209908Sraj case SVR_P2020: 117209908Sraj maxcpu = 2; 118209908Sraj break; 119209908Sraj default: 120209908Sraj maxcpu = 1; 121209908Sraj break; 122209908Sraj } 123209908Sraj 124209908Sraj /* 125209908Sraj * Clear local access windows. Skip DRAM entries, so we don't shoot 126209908Sraj * ourselves in the foot. 127209908Sraj */ 128209908Sraj law_max = law_getmax(); 129192067Snwhitehorn for (i = 0; i < law_max; i++) { 130192067Snwhitehorn sr = ccsr_read4(OCP85XX_LAWSR(i)); 131192067Snwhitehorn if ((sr & 0x80000000) == 0) 132192067Snwhitehorn continue; 133192067Snwhitehorn tgt = (sr & 0x01f00000) >> 20; 134192067Snwhitehorn if (tgt == OCP85XX_TGTIF_RAM1 || tgt == OCP85XX_TGTIF_RAM2 || 135192067Snwhitehorn tgt == OCP85XX_TGTIF_RAM_INTL) 136192067Snwhitehorn continue; 137192067Snwhitehorn 138192067Snwhitehorn ccsr_write4(OCP85XX_LAWSR(i), sr & 0x7fffffff); 139209908Sraj } 140209908Sraj 141192067Snwhitehorn return (BUS_PROBE_GENERIC); 142209908Sraj} 143209908Sraj 144209908Sraj#define MEM_REGIONS 8 145209908Srajstatic struct mem_region avail_regions[MEM_REGIONS]; 146209908Sraj 147209908Srajvoid 148209908Srajbare_mem_regions(platform_t plat, struct mem_region **phys, int *physsz, 149209908Sraj struct mem_region **avail, int *availsz) 150209908Sraj{ 151209908Sraj uint32_t memsize; 152192067Snwhitehorn int i, rv; 153192067Snwhitehorn 154192067Snwhitehorn rv = fdt_get_mem_regions(avail_regions, availsz, &memsize); 155192067Snwhitehorn 156192067Snwhitehorn if (rv != 0) 157192067Snwhitehorn return; 158192067Snwhitehorn 159192067Snwhitehorn for (i = 0; i < *availsz; i++) { 160192067Snwhitehorn if (avail_regions[i].mr_start < 1048576) { 161192067Snwhitehorn avail_regions[i].mr_size = 162192067Snwhitehorn avail_regions[i].mr_size - 163192067Snwhitehorn (1048576 - avail_regions[i].mr_start); 164192067Snwhitehorn avail_regions[i].mr_start = 1048576; 165217523Smarcel } 166209908Sraj } 167209908Sraj *avail = avail_regions; 168192067Snwhitehorn 169217523Smarcel /* On the bare metal platform phys == avail memory */ 170217523Smarcel *physsz = *availsz; 171217523Smarcel *phys = *avail; 172209908Sraj} 173209908Sraj 174209908Srajstatic u_long 175209908Srajbare_timebase_freq(platform_t plat, struct cpuref *cpuref) 176209908Sraj{ 177209908Sraj u_long ticks; 178217523Smarcel phandle_t cpus, child; 179209908Sraj pcell_t freq; 180209908Sraj 181209908Sraj if (bootinfo != NULL) 182217523Smarcel if (bootinfo[0] == 1) { 183192067Snwhitehorn /* Backward compatibility. See 8-STABLE. */ 184192067Snwhitehorn ticks = bootinfo[3] >> 3; 185192067Snwhitehorn } else { 186192067Snwhitehorn /* Compatbility with Juniper's loader. */ 187217523Smarcel ticks = bootinfo[5] >> 3; 188217523Smarcel } else 189217523Smarcel ticks = 0; 190209908Sraj 191192067Snwhitehorn if ((cpus = OF_finddevice("/cpus")) == 0) 192192067Snwhitehorn goto out; 193192067Snwhitehorn 194192067Snwhitehorn if ((child = OF_child(cpus)) == 0) 195192067Snwhitehorn goto out; 196192067Snwhitehorn 197192067Snwhitehorn freq = 0; 198192067Snwhitehorn if (OF_getprop(child, "bus-frequency", (void *)&freq, 199192067Snwhitehorn sizeof(freq)) <= 0) 200192067Snwhitehorn goto out; 201192067Snwhitehorn 202192067Snwhitehorn /* 203192067Snwhitehorn * Time Base and Decrementer are updated every 8 CCB bus clocks. 204192067Snwhitehorn * HID0[SEL_TBCLK] = 0 205192067Snwhitehorn */ 206192067Snwhitehorn if (freq != 0) 207192067Snwhitehorn ticks = freq / 8; 208192067Snwhitehorn 209192067Snwhitehornout: 210192067Snwhitehorn if (ticks <= 0) 211192067Snwhitehorn panic("Unable to determine timebase frequency!"); 212192067Snwhitehorn 213192067Snwhitehorn return (ticks); 214192067Snwhitehorn} 215193492Sraj 216192067Snwhitehornstatic int 217192067Snwhitehornbare_smp_first_cpu(platform_t plat, struct cpuref *cpuref) 218192067Snwhitehorn{ 219192067Snwhitehorn 220192067Snwhitehorn cpu = 0; 221192067Snwhitehorn cpuref->cr_cpuid = cpu; 222192067Snwhitehorn cpuref->cr_hwref = cpuref->cr_cpuid; 223192067Snwhitehorn if (bootverbose) 224192067Snwhitehorn printf("powerpc_smp_first_cpu: cpuid %d\n", cpuref->cr_cpuid); 225192067Snwhitehorn cpu++; 226192067Snwhitehorn 227192067Snwhitehorn return (0); 228192067Snwhitehorn} 229192067Snwhitehorn 230192067Snwhitehornstatic int 231192067Snwhitehornbare_smp_next_cpu(platform_t plat, struct cpuref *cpuref) 232192067Snwhitehorn{ 233192067Snwhitehorn 234192067Snwhitehorn if (cpu >= maxcpu) 235192067Snwhitehorn return (ENOENT); 236192067Snwhitehorn 237192067Snwhitehorn cpuref->cr_cpuid = cpu++; 238192067Snwhitehorn cpuref->cr_hwref = cpuref->cr_cpuid; 239192532Sraj if (bootverbose) 240192532Sraj printf("powerpc_smp_next_cpu: cpuid %d\n", cpuref->cr_cpuid); 241192532Sraj 242192067Snwhitehorn return (0); 243192532Sraj} 244192532Sraj 245192532Srajstatic int 246192532Srajbare_smp_get_bsp(platform_t plat, struct cpuref *cpuref) 247192532Sraj{ 248192532Sraj 249192532Sraj cpuref->cr_cpuid = mfspr(SPR_PIR); 250192532Sraj cpuref->cr_hwref = cpuref->cr_cpuid; 251192532Sraj 252192532Sraj return (0); 253192532Sraj} 254192532Sraj 255192532Srajstatic int 256192532Srajbare_smp_start_cpu(platform_t plat, struct pcpu *pc) 257192532Sraj{ 258192532Sraj#ifdef SMP 259192532Sraj uint32_t bptr, eebpcr; 260192532Sraj int timeout; 261192532Sraj 262192532Sraj eebpcr = ccsr_read4(OCP85XX_EEBPCR); 263192532Sraj if ((eebpcr & (1 << (pc->pc_cpuid + 24))) != 0) { 264192532Sraj printf("%s: CPU=%d already out of hold-off state!\n", 265192532Sraj __func__, pc->pc_cpuid); 266192532Sraj return (ENXIO); 267192532Sraj } 268192532Sraj 269192532Sraj ap_pcpu = pc; 270192532Sraj __asm __volatile("msync; isync"); 271192532Sraj 272192067Snwhitehorn /* 273192067Snwhitehorn * Set BPTR to the physical address of the boot page 274192532Sraj */ 275192067Snwhitehorn bptr = ((uint32_t)__boot_page - KERNBASE) + kernload_ap; 276212054Snwhitehorn ccsr_write4(OCP85XX_BPTR, (bptr >> 12) | 0x80000000); 277212054Snwhitehorn 278212054Snwhitehorn /* 279212054Snwhitehorn * Release AP from hold-off state 280212054Snwhitehorn */ 281212054Snwhitehorn eebpcr |= (1 << (pc->pc_cpuid + 24)); 282212054Snwhitehorn ccsr_write4(OCP85XX_EEBPCR, eebpcr); 283212054Snwhitehorn __asm __volatile("isync; msync"); 284212054Snwhitehorn 285212054Snwhitehorn timeout = 500; 286212054Snwhitehorn while (!pc->pc_awake && timeout--) 287212054Snwhitehorn DELAY(1000); /* wait 1ms */ 288212054Snwhitehorn 289212054Snwhitehorn return ((pc->pc_awake) ? 0 : EBUSY); 290212054Snwhitehorn#else 291212054Snwhitehorn /* No SMP support */ 292212054Snwhitehorn return (ENXIO); 293212054Snwhitehorn#endif 294212054Snwhitehorn} 295212054Snwhitehorn 296212054Snwhitehornstatic void 297212054Snwhitehorne500_reset(platform_t plat) 298212054Snwhitehorn{ 299212054Snwhitehorn 300212054Snwhitehorn /* 301212054Snwhitehorn * Try the dedicated reset register first. 302212054Snwhitehorn * If the SoC doesn't have one, we'll fall 303 * back to using the debug control register. 304 */ 305 ccsr_write4(OCP85XX_RSTCR, 2); 306 307 /* Clear DBCR0, disables debug interrupts and events. */ 308 mtspr(SPR_DBCR0, 0); 309 __asm __volatile("isync"); 310 311 /* Enable Debug Interrupts in MSR. */ 312 mtmsr(mfmsr() | PSL_DE); 313 314 /* Enable debug interrupts and issue reset. */ 315 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); 316 317 printf("Reset failed...\n"); 318 while (1); 319} 320 321