psl.h revision 209975
1139825Simp/*- 277957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 377957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 477957Sbenno * All rights reserved. 577957Sbenno * 677957Sbenno * Redistribution and use in source and binary forms, with or without 777957Sbenno * modification, are permitted provided that the following conditions 877957Sbenno * are met: 977957Sbenno * 1. Redistributions of source code must retain the above copyright 1077957Sbenno * notice, this list of conditions and the following disclaimer. 1177957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1277957Sbenno * notice, this list of conditions and the following disclaimer in the 1377957Sbenno * documentation and/or other materials provided with the distribution. 1477957Sbenno * 3. All advertising materials mentioning features or use of this software 1577957Sbenno * must display the following acknowledgement: 1677957Sbenno * This product includes software developed by TooLs GmbH. 1777957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 1877957Sbenno * derived from this software without specific prior written permission. 1977957Sbenno * 2077957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 2177957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2277957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2377957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2477957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2577957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2677957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2777957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2877957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2977957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3077957Sbenno * 3196905Sbenno * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ 3277957Sbenno * $FreeBSD: head/sys/powerpc/include/psl.h 209975 2010-07-13 05:32:19Z nwhitehorn $ 3377957Sbenno */ 3477957Sbenno 3577957Sbenno#ifndef _MACHINE_PSL_H_ 3677957Sbenno#define _MACHINE_PSL_H_ 3777957Sbenno 38176770Sraj#if defined(E500) 3977957Sbenno/* 40176770Sraj * Machine State Register (MSR) - e500 core 41176770Sraj * 42176770Sraj * The PowerPC e500 does not implement the following bits: 43176770Sraj * 44176770Sraj * FP, FE0, FE1 - reserved, always cleared, setting has no effect. 45176770Sraj * 46176770Sraj */ 47209975Snwhitehorn#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ 48209975Snwhitehorn#define PSL_SPE 0x02000000UL /* SPE enable */ 49209975Snwhitehorn#define PSL_WE 0x00040000UL /* Wait state enable */ 50209975Snwhitehorn#define PSL_CE 0x00020000UL /* Critical interrupt enable */ 51209975Snwhitehorn#define PSL_EE 0x00008000UL /* External interrupt enable */ 52209975Snwhitehorn#define PSL_PR 0x00004000UL /* User mode */ 53209975Snwhitehorn#define PSL_FP 0x00002000UL /* Floating point available */ 54209975Snwhitehorn#define PSL_ME 0x00001000UL /* Machine check interrupt enable */ 55209975Snwhitehorn#define PSL_FE0 0x00000800UL /* Floating point exception mode 0 */ 56209975Snwhitehorn#define PSL_UBLE 0x00000400UL /* BTB lock enable */ 57209975Snwhitehorn#define PSL_DE 0x00000200UL /* Debug interrupt enable */ 58209975Snwhitehorn#define PSL_FE1 0x00000100UL /* Floating point exception mode 1 */ 59209975Snwhitehorn#define PSL_IS 0x00000020UL /* Instruction address space */ 60209975Snwhitehorn#define PSL_DS 0x00000010UL /* Data address space */ 61209975Snwhitehorn#define PSL_PMM 0x00000004UL /* Performance monitor mark */ 62176770Sraj 63209975Snwhitehorn#define PSL_FE_DFLT 0x00000000UL /* default == none */ 64209950Snwhitehorn 65176770Sraj/* Initial kernel MSR, use IS=1 ad DS=1. */ 66176770Sraj#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) 67176770Sraj#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) 68176770Sraj#define PSL_USERSET (PSL_KERNSET | PSL_PR) 69176770Sraj 70176770Sraj#else /* if defined(E500) */ 71176770Sraj/* 7277957Sbenno * Machine State Register (MSR) 7377957Sbenno * 7477957Sbenno * The PowerPC 601 does not implement the following bits: 7577957Sbenno * 7696905Sbenno * VEC, POW, ILE, BE, RI, LE[*] 7777957Sbenno * 7877957Sbenno * [*] Little-endian mode on the 601 is implemented in the HID0 register. 7977957Sbenno */ 8077957Sbenno 81209975Snwhitehorn#ifdef __powerpc64__ 82209975Snwhitehorn#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */ 83209975Snwhitehorn#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */ 84209975Snwhitehorn#endif 85209975Snwhitehorn 86209975Snwhitehorn#define PSL_VEC 0x02000000UL /* AltiVec vector unit available */ 87209975Snwhitehorn#define PSL_POW 0x00040000UL /* power management */ 88209975Snwhitehorn#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ 89209975Snwhitehorn#define PSL_EE 0x00008000UL /* external interrupt enable */ 90209975Snwhitehorn#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ 91209975Snwhitehorn#define PSL_FP 0x00002000UL /* floating point enable */ 92209975Snwhitehorn#define PSL_ME 0x00001000UL /* machine check enable */ 93209975Snwhitehorn#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ 94209975Snwhitehorn#define PSL_SE 0x00000400UL /* single-step trace enable */ 95209975Snwhitehorn#define PSL_BE 0x00000200UL /* branch trace enable */ 96209975Snwhitehorn#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ 97209975Snwhitehorn#define PSL_IP 0x00000040UL /* interrupt prefix */ 98209975Snwhitehorn#define PSL_IR 0x00000020UL /* instruction address relocation */ 99209975Snwhitehorn#define PSL_DR 0x00000010UL /* data address relocation */ 100209975Snwhitehorn#define PSL_PMM 0x00000004UL /* performance monitor mark */ 101209975Snwhitehorn#define PSL_RI 0x00000002UL /* recoverable interrupt */ 102209975Snwhitehorn#define PSL_LE 0x00000001UL /* endian mode (1 == le) */ 103209975Snwhitehorn 10477957Sbenno#define PSL_601_MASK ~(PSL_POW|PSL_ILE|PSL_BE|PSL_RI|PSL_LE) 10577957Sbenno 10677957Sbenno/* 10777957Sbenno * Floating-point exception modes: 10877957Sbenno */ 10977957Sbenno#define PSL_FE_DIS 0 /* none */ 11077957Sbenno#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */ 11177957Sbenno#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */ 11277957Sbenno#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ 11377957Sbenno#define PSL_FE_DFLT PSL_FE_DIS /* default == none */ 11477957Sbenno 11577957Sbenno/* 11677957Sbenno * Note that PSL_POW and PSL_ILE are not in the saved copy of the MSR 11777957Sbenno */ 11877957Sbenno#define PSL_MBO 0 11977957Sbenno#define PSL_MBZ 0 12077957Sbenno 121209975Snwhitehorn#ifdef __powerpc64__ 122209975Snwhitehorn#define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) 123209975Snwhitehorn#else 124138220Sgrehan#define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) 125209975Snwhitehorn#endif 126138220Sgrehan#define PSL_USERSET (PSL_KERNSET | PSL_PR) 12777957Sbenno 12877957Sbenno#define PSL_USERSTATIC (PSL_USERSET | PSL_IP | 0x87c0008c) 12977957Sbenno 130176770Sraj#endif /* if defined(E500) */ 13177957Sbenno#endif /* _MACHINE_PSL_H_ */ 132