1139825Simp/*- 277957Sbenno * Copyright (C) 1995, 1996 Wolfgang Solfrank. 377957Sbenno * Copyright (C) 1995, 1996 TooLs GmbH. 477957Sbenno * All rights reserved. 577957Sbenno * 677957Sbenno * Redistribution and use in source and binary forms, with or without 777957Sbenno * modification, are permitted provided that the following conditions 877957Sbenno * are met: 977957Sbenno * 1. Redistributions of source code must retain the above copyright 1077957Sbenno * notice, this list of conditions and the following disclaimer. 1177957Sbenno * 2. Redistributions in binary form must reproduce the above copyright 1277957Sbenno * notice, this list of conditions and the following disclaimer in the 1377957Sbenno * documentation and/or other materials provided with the distribution. 1477957Sbenno * 3. All advertising materials mentioning features or use of this software 1577957Sbenno * must display the following acknowledgement: 1677957Sbenno * This product includes software developed by TooLs GmbH. 1777957Sbenno * 4. The name of TooLs GmbH may not be used to endorse or promote products 1877957Sbenno * derived from this software without specific prior written permission. 1977957Sbenno * 2077957Sbenno * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR 2177957Sbenno * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 2277957Sbenno * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 2377957Sbenno * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2477957Sbenno * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 2577957Sbenno * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 2677957Sbenno * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 2777957Sbenno * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 2877957Sbenno * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 2977957Sbenno * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3077957Sbenno * 3196905Sbenno * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $ 3277957Sbenno * $FreeBSD: releng/10.2/sys/powerpc/include/psl.h 271171 2014-09-05 15:13:41Z jhibbits $ 3377957Sbenno */ 3477957Sbenno 3577957Sbenno#ifndef _MACHINE_PSL_H_ 3677957Sbenno#define _MACHINE_PSL_H_ 3777957Sbenno 3877957Sbenno/* 39265972Sian * Machine State Register (MSR) - All cores 40176770Sraj */ 41265972Sian#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */ 42265972Sian#define PSL_EE 0x00008000UL /* external interrupt enable */ 43265972Sian#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */ 44265972Sian#define PSL_FP 0x00002000UL /* floating point enable */ 45265972Sian#define PSL_ME 0x00001000UL /* machine check enable */ 46265972Sian#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */ 47265972Sian#define PSL_BE 0x00000200UL /* branch trace enable */ 48265972Sian#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */ 49265972Sian#define PSL_PMM 0x00000004UL /* performance monitor mark */ 50265972Sian 51265972Sian/* Machine State Register - Book-E cores */ 52209975Snwhitehorn#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */ 53209975Snwhitehorn#define PSL_WE 0x00040000UL /* Wait state enable */ 54209975Snwhitehorn#define PSL_CE 0x00020000UL /* Critical interrupt enable */ 55265972Sian#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */ 56265972Sian#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/ 57209975Snwhitehorn#define PSL_DE 0x00000200UL /* Debug interrupt enable */ 58209975Snwhitehorn#define PSL_IS 0x00000020UL /* Instruction address space */ 59209975Snwhitehorn#define PSL_DS 0x00000010UL /* Data address space */ 60176770Sraj 61265972Sian/* Machine State Register (MSR) - AIM cores */ 62209975Snwhitehorn#ifdef __powerpc64__ 63209975Snwhitehorn#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */ 64209975Snwhitehorn#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */ 65209975Snwhitehorn#endif 66209975Snwhitehorn 67209975Snwhitehorn#define PSL_POW 0x00040000UL /* power management */ 68209975Snwhitehorn#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */ 69209975Snwhitehorn#define PSL_SE 0x00000400UL /* single-step trace enable */ 70265972Sian#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */ 71209975Snwhitehorn#define PSL_IR 0x00000020UL /* instruction address relocation */ 72209975Snwhitehorn#define PSL_DR 0x00000010UL /* data address relocation */ 73209975Snwhitehorn#define PSL_RI 0x00000002UL /* recoverable interrupt */ 74209975Snwhitehorn#define PSL_LE 0x00000001UL /* endian mode (1 == le) */ 75209975Snwhitehorn 7677957Sbenno/* 7777957Sbenno * Floating-point exception modes: 7877957Sbenno */ 7977957Sbenno#define PSL_FE_DIS 0 /* none */ 8077957Sbenno#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */ 8177957Sbenno#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */ 8277957Sbenno#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */ 8377957Sbenno#define PSL_FE_DFLT PSL_FE_DIS /* default == none */ 8477957Sbenno 85265972Sian#if defined(BOOKE_E500) 86265972Sian/* Initial kernel MSR, use IS=1 ad DS=1. */ 87265972Sian#define PSL_KERNSET_INIT (PSL_IS | PSL_DS) 88265972Sian#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE) 89271171Sjhibbits#define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */ 90265972Sian#elif defined(BOOKE_PPC4XX) 91265972Sian#define PSL_KERNSET (PSL_CE | PSL_ME | PSL_EE | PSL_FP) 92271171Sjhibbits#define PSL_SRR1_MASK 0x00000000UL /* No mask on Book-E */ 93265972Sian#elif defined(AIM) 94209975Snwhitehorn#ifdef __powerpc64__ 95209975Snwhitehorn#define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) 96209975Snwhitehorn#else 97138220Sgrehan#define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI) 98209975Snwhitehorn#endif 99271171Sjhibbits#define PSL_SRR1_MASK 0x783f0000UL /* Bits 1-4, 10-15 (ppc32), 33-36, 42-47 (ppc64) */ 100265972Sian#endif 101265972Sian 102138220Sgrehan#define PSL_USERSET (PSL_KERNSET | PSL_PR) 103271171Sjhibbits#define PSL_USERSTATIC (~(PSL_VEC | PSL_FP | PSL_FE0 | PSL_FE1) & ~PSL_SRR1_MASK) 10477957Sbenno 10577957Sbenno#endif /* _MACHINE_PSL_H_ */ 106