if_rlreg.h revision 150720
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_rlreg.h 150720 2005-09-29 16:52:19Z jhb $ 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 41#define RL_IDR3 0x0003 42#define RL_IDR4 0x0004 43#define RL_IDR5 0x0005 44 /* 0006-0007 reserved */ 45#define RL_MAR0 0x0008 /* Multicast hash table */ 46#define RL_MAR1 0x0009 47#define RL_MAR2 0x000A 48#define RL_MAR3 0x000B 49#define RL_MAR4 0x000C 50#define RL_MAR5 0x000D 51#define RL_MAR6 0x000E 52#define RL_MAR7 0x000F 53 54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 58 59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 63 64#define RL_RXADDR 0x0030 /* RX ring start address */ 65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67#define RL_COMMAND 0x0037 /* command register */ 68#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70#define RL_IMR 0x003C /* interrupt mask register */ 71#define RL_ISR 0x003E /* interrupt status register */ 72#define RL_TXCFG 0x0040 /* transmit config */ 73#define RL_RXCFG 0x0044 /* receive config */ 74#define RL_TIMERCNT 0x0048 /* timer count register */ 75#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76#define RL_EECMD 0x0050 /* EEPROM command register */ 77#define RL_CFG0 0x0051 /* config register #0 */ 78#define RL_CFG1 0x0052 /* config register #1 */ 79 /* 0053-0057 reserved */ 80#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 81 /* 0059-005A reserved */ 82#define RL_MII 0x005A /* 8129 chip only */ 83#define RL_HALTCLK 0x005B 84#define RL_MULTIINTR 0x005C /* multiple interrupt */ 85#define RL_PCIREV 0x005E /* PCI revision value */ 86 /* 005F reserved */ 87#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 88 89/* Direct PHY access registers only available on 8139 */ 90#define RL_BMCR 0x0062 /* PHY basic mode control */ 91#define RL_BMSR 0x0064 /* PHY basic mode status */ 92#define RL_ANAR 0x0066 /* PHY autoneg advert */ 93#define RL_LPAR 0x0068 /* PHY link partner ability */ 94#define RL_ANER 0x006A /* PHY autoneg expansion */ 95 96#define RL_DISCCNT 0x006C /* disconnect counter */ 97#define RL_FALSECAR 0x006E /* false carrier counter */ 98#define RL_NWAYTST 0x0070 /* NWAY test register */ 99#define RL_RX_ER 0x0072 /* RX_ER counter */ 100#define RL_CSCFG 0x0074 /* CS configuration register */ 101 102/* 103 * When operating in special C+ mode, some of the registers in an 104 * 8139C+ chip have different definitions. These are also used for 105 * the 8169 gigE chip. 106 */ 107#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113#define RL_CFG2 0x0053 114#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115#define RL_TXSTART 0x00D9 /* 8 bits */ 116#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 120 121/* 122 * Registers specific to the 8169 gigE chip 123 */ 124#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125#define RL_PHYAR 0x0060 126#define RL_TBICSR 0x0064 127#define RL_TBI_ANAR 0x0068 128#define RL_TBI_LPAR 0x006A 129#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131#define RL_GTXSTART 0x0038 /* 16 bits */ 132 133/* 134 * TX config register bits 135 */ 136#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 137#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 138#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 139#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 141#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142#define RL_TXCFG_HWREV 0x7CC00000 143 144#define RL_LOOPTEST_OFF 0x00000000 145#define RL_LOOPTEST_ON 0x00020000 146#define RL_LOOPTEST_ON_CPLUS 0x00060000 147 148#define RL_HWREV_8169 0x00000000 149#define RL_HWREV_8169S 0x04000000 150#define RL_HWREV_8169SB 0x10000000 151#define RL_HWREV_8110S 0x00800000 152#define RL_HWREV_8139 0x60000000 153#define RL_HWREV_8139A 0x70000000 154#define RL_HWREV_8139AG 0x70800000 155#define RL_HWREV_8139B 0x78000000 156#define RL_HWREV_8130 0x7C000000 157#define RL_HWREV_8139C 0x74000000 158#define RL_HWREV_8139D 0x74400000 159#define RL_HWREV_8139CPLUS 0x74800000 160#define RL_HWREV_8101 0x74c00000 161#define RL_HWREV_8100 0x78800000 162 163#define RL_TXDMA_16BYTES 0x00000000 164#define RL_TXDMA_32BYTES 0x00000100 165#define RL_TXDMA_64BYTES 0x00000200 166#define RL_TXDMA_128BYTES 0x00000300 167#define RL_TXDMA_256BYTES 0x00000400 168#define RL_TXDMA_512BYTES 0x00000500 169#define RL_TXDMA_1024BYTES 0x00000600 170#define RL_TXDMA_2048BYTES 0x00000700 171 172/* 173 * Transmit descriptor status register bits. 174 */ 175#define RL_TXSTAT_LENMASK 0x00001FFF 176#define RL_TXSTAT_OWN 0x00002000 177#define RL_TXSTAT_TX_UNDERRUN 0x00004000 178#define RL_TXSTAT_TX_OK 0x00008000 179#define RL_TXSTAT_EARLY_THRESH 0x003F0000 180#define RL_TXSTAT_COLLCNT 0x0F000000 181#define RL_TXSTAT_CARR_HBEAT 0x10000000 182#define RL_TXSTAT_OUTOFWIN 0x20000000 183#define RL_TXSTAT_TXABRT 0x40000000 184#define RL_TXSTAT_CARRLOSS 0x80000000 185 186/* 187 * Interrupt status register bits. 188 */ 189#define RL_ISR_RX_OK 0x0001 190#define RL_ISR_RX_ERR 0x0002 191#define RL_ISR_TX_OK 0x0004 192#define RL_ISR_TX_ERR 0x0008 193#define RL_ISR_RX_OVERRUN 0x0010 194#define RL_ISR_PKT_UNDERRUN 0x0020 195#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 196#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 197#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 198#define RL_ISR_SWI 0x0100 /* C+ only */ 199#define RL_ISR_CABLE_LEN_CHGD 0x2000 200#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 201#define RL_ISR_TIMEOUT_EXPIRED 0x4000 202#define RL_ISR_SYSTEM_ERR 0x8000 203 204#define RL_INTRS \ 205 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 206 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 207 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 208 209#define RL_INTRS_CPLUS \ 210 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 211 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 212 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 213 214/* 215 * Media status register. (8139 only) 216 */ 217#define RL_MEDIASTAT_RXPAUSE 0x01 218#define RL_MEDIASTAT_TXPAUSE 0x02 219#define RL_MEDIASTAT_LINK 0x04 220#define RL_MEDIASTAT_SPEED10 0x08 221#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 222#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 223 224/* 225 * Receive config register. 226 */ 227#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 228#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 229#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 230#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 231#define RL_RXCFG_RX_RUNT 0x00000010 232#define RL_RXCFG_RX_ERRPKT 0x00000020 233#define RL_RXCFG_WRAP 0x00000080 234#define RL_RXCFG_MAXDMA 0x00000700 235#define RL_RXCFG_BUFSZ 0x00001800 236#define RL_RXCFG_FIFOTHRESH 0x0000E000 237#define RL_RXCFG_EARLYTHRESH 0x07000000 238 239#define RL_RXDMA_16BYTES 0x00000000 240#define RL_RXDMA_32BYTES 0x00000100 241#define RL_RXDMA_64BYTES 0x00000200 242#define RL_RXDMA_128BYTES 0x00000300 243#define RL_RXDMA_256BYTES 0x00000400 244#define RL_RXDMA_512BYTES 0x00000500 245#define RL_RXDMA_1024BYTES 0x00000600 246#define RL_RXDMA_UNLIMITED 0x00000700 247 248#define RL_RXBUF_8 0x00000000 249#define RL_RXBUF_16 0x00000800 250#define RL_RXBUF_32 0x00001000 251#define RL_RXBUF_64 0x00001800 252 253#define RL_RXFIFO_16BYTES 0x00000000 254#define RL_RXFIFO_32BYTES 0x00002000 255#define RL_RXFIFO_64BYTES 0x00004000 256#define RL_RXFIFO_128BYTES 0x00006000 257#define RL_RXFIFO_256BYTES 0x00008000 258#define RL_RXFIFO_512BYTES 0x0000A000 259#define RL_RXFIFO_1024BYTES 0x0000C000 260#define RL_RXFIFO_NOTHRESH 0x0000E000 261 262/* 263 * Bits in RX status header (included with RX'ed packet 264 * in ring buffer). 265 */ 266#define RL_RXSTAT_RXOK 0x00000001 267#define RL_RXSTAT_ALIGNERR 0x00000002 268#define RL_RXSTAT_CRCERR 0x00000004 269#define RL_RXSTAT_GIANT 0x00000008 270#define RL_RXSTAT_RUNT 0x00000010 271#define RL_RXSTAT_BADSYM 0x00000020 272#define RL_RXSTAT_BROAD 0x00002000 273#define RL_RXSTAT_INDIV 0x00004000 274#define RL_RXSTAT_MULTI 0x00008000 275#define RL_RXSTAT_LENMASK 0xFFFF0000 276 277#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 278/* 279 * Command register. 280 */ 281#define RL_CMD_EMPTY_RXBUF 0x0001 282#define RL_CMD_TX_ENB 0x0004 283#define RL_CMD_RX_ENB 0x0008 284#define RL_CMD_RESET 0x0010 285 286/* 287 * EEPROM control register 288 */ 289#define RL_EE_DATAOUT 0x01 /* Data out */ 290#define RL_EE_DATAIN 0x02 /* Data in */ 291#define RL_EE_CLK 0x04 /* clock */ 292#define RL_EE_SEL 0x08 /* chip select */ 293#define RL_EE_MODE (0x40|0x80) 294 295#define RL_EEMODE_OFF 0x00 296#define RL_EEMODE_AUTOLOAD 0x40 297#define RL_EEMODE_PROGRAM 0x80 298#define RL_EEMODE_WRITECFG (0x80|0x40) 299 300/* 9346 EEPROM commands */ 301#define RL_EECMD_WRITE 0x140 302#define RL_EECMD_READ_6BIT 0x180 303#define RL_EECMD_READ_8BIT 0x600 304#define RL_EECMD_ERASE 0x1c0 305 306#define RL_EE_ID 0x00 307#define RL_EE_PCI_VID 0x01 308#define RL_EE_PCI_DID 0x02 309/* Location of station address inside EEPROM */ 310#define RL_EE_EADDR 0x07 311 312/* 313 * MII register (8129 only) 314 */ 315#define RL_MII_CLK 0x01 316#define RL_MII_DATAIN 0x02 317#define RL_MII_DATAOUT 0x04 318#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 319 320/* 321 * Config 0 register 322 */ 323#define RL_CFG0_ROM0 0x01 324#define RL_CFG0_ROM1 0x02 325#define RL_CFG0_ROM2 0x04 326#define RL_CFG0_PL0 0x08 327#define RL_CFG0_PL1 0x10 328#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 329#define RL_CFG0_PCS 0x40 330#define RL_CFG0_SCR 0x80 331 332/* 333 * Config 1 register 334 */ 335#define RL_CFG1_PWRDWN 0x01 336#define RL_CFG1_SLEEP 0x02 337#define RL_CFG1_IOMAP 0x04 338#define RL_CFG1_MEMMAP 0x08 339#define RL_CFG1_RSVD 0x10 340#define RL_CFG1_DRVLOAD 0x20 341#define RL_CFG1_LED0 0x40 342#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 343#define RL_CFG1_LED1 0x80 344 345/* 346 * 8139C+ register definitions 347 */ 348 349/* RL_DUMPSTATS_LO register */ 350 351#define RL_DUMPSTATS_START 0x00000008 352 353/* Transmit start register */ 354 355#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 356#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 357#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 358 359/* 360 * Config 2 register, 8139C+/8169/8169S/8110S only 361 */ 362#define RL_CFG2_BUSFREQ 0x07 363#define RL_CFG2_BUSWIDTH 0x08 364#define RL_CFG2_AUXPWRSTS 0x10 365 366#define RL_BUSFREQ_33MHZ 0x00 367#define RL_BUSFREQ_66MHZ 0x01 368 369#define RL_BUSWIDTH_32BITS 0x00 370#define RL_BUSWIDTH_64BITS 0x08 371 372/* C+ mode command register */ 373 374#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 375#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 376#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 377#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 378#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 379#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 380 381/* C+ early transmit threshold */ 382 383#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 384 385/* 386 * Gigabit PHY access register (8169 only) 387 */ 388 389#define RL_PHYAR_PHYDATA 0x0000FFFF 390#define RL_PHYAR_PHYREG 0x001F0000 391#define RL_PHYAR_BUSY 0x80000000 392 393/* 394 * Gigabit media status (8169 only) 395 */ 396#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 397#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 398#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 399#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 400#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 401#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 402#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 403#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 404 405/* 406 * The RealTek doesn't use a fragment-based descriptor mechanism. 407 * Instead, there are only four register sets, each or which represents 408 * one 'descriptor.' Basically, each TX descriptor is just a contiguous 409 * packet buffer (32-bit aligned!) and we place the buffer addresses in 410 * the registers so the chip knows where they are. 411 * 412 * We can sort of kludge together the same kind of buffer management 413 * used in previous drivers, but we have to do buffer copies almost all 414 * the time, so it doesn't really buy us much. 415 * 416 * For reception, there's just one large buffer where the chip stores 417 * all received packets. 418 */ 419 420#define RL_RX_BUF_SZ RL_RXBUF_64 421#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 422#define RL_TX_LIST_CNT 4 423#define RL_MIN_FRAMELEN 60 424#define RL_TXTHRESH(x) ((x) << 11) 425#define RL_TX_THRESH_INIT 96 426#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 427#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 428#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 429 430#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 431#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 432 433#define RL_ETHER_ALIGN 2 434 435struct rl_chain_data { 436 uint16_t cur_rx; 437 uint8_t *rl_rx_buf; 438 uint8_t *rl_rx_buf_ptr; 439 bus_dmamap_t rl_rx_dmamap; 440 441 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 442 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 443 uint8_t last_tx; 444 uint8_t cur_tx; 445}; 446 447#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 448#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 449#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 450#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 451#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 452#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 453#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 454#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 455#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 456 457struct rl_type { 458 uint16_t rl_vid; 459 uint16_t rl_did; 460 int rl_basetype; 461 char *rl_name; 462}; 463 464struct rl_hwrev { 465 uint32_t rl_rev; 466 int rl_type; 467 char *rl_desc; 468}; 469 470struct rl_mii_frame { 471 uint8_t mii_stdelim; 472 uint8_t mii_opcode; 473 uint8_t mii_phyaddr; 474 uint8_t mii_regaddr; 475 uint8_t mii_turnaround; 476 uint16_t mii_data; 477}; 478 479/* 480 * MII constants 481 */ 482#define RL_MII_STARTDELIM 0x01 483#define RL_MII_READOP 0x02 484#define RL_MII_WRITEOP 0x01 485#define RL_MII_TURNAROUND 0x02 486 487#define RL_8129 1 488#define RL_8139 2 489#define RL_8139CPLUS 3 490#define RL_8169 4 491 492#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 493 (x)->rl_type == RL_8169) 494 495/* 496 * The 8139C+ and 8160 gigE chips support descriptor-based TX 497 * and RX. In fact, they even support TCP large send. Descriptors 498 * must be allocated in contiguous blocks that are aligned on a 499 * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 500 */ 501 502/* 503 * RX/TX descriptor definition. When large send mode is enabled, the 504 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 505 * the checksum offload bits are disabled. The structure layout is 506 * the same for RX and TX descriptors 507 */ 508 509struct rl_desc { 510 uint32_t rl_cmdstat; 511 uint32_t rl_vlanctl; 512 uint32_t rl_bufaddr_lo; 513 uint32_t rl_bufaddr_hi; 514}; 515 516#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 517#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 518#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 519#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 520#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 521#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 522#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 523#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 524#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 525#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 526 527#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 528#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 529 530/* 531 * Error bits are valid only on the last descriptor of a frame 532 * (i.e. RL_TDESC_CMD_EOF == 1) 533 */ 534 535#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 536#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 537#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 538#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 539#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 540#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 541#define RL_TDESC_STAT_OWN 0x80000000 542 543/* 544 * RX descriptor cmd/vlan definitions 545 */ 546 547#define RL_RDESC_CMD_EOR 0x40000000 548#define RL_RDESC_CMD_OWN 0x80000000 549#define RL_RDESC_CMD_BUFLEN 0x00001FFF 550 551#define RL_RDESC_STAT_OWN 0x80000000 552#define RL_RDESC_STAT_EOR 0x40000000 553#define RL_RDESC_STAT_SOF 0x20000000 554#define RL_RDESC_STAT_EOF 0x10000000 555#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 556#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 557#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 558#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 559#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 560#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 561#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 562#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 563#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 564#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 565#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 566#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 567#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 568#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 569#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 570#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 571#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 572 RL_RDESC_STAT_CRCERR) 573 574#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 575 (rl_vlandata valid)*/ 576#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 577 578#define RL_PROTOID_NONIP 0x00000000 579#define RL_PROTOID_TCPIP 0x00010000 580#define RL_PROTOID_UDPIP 0x00020000 581#define RL_PROTOID_IP 0x00030000 582#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 583 RL_PROTOID_TCPIP) 584#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 585 RL_PROTOID_UDPIP) 586 587/* 588 * Statistics counter structure (8139C+ and 8169 only) 589 */ 590struct rl_stats { 591 uint32_t rl_tx_pkts_lo; 592 uint32_t rl_tx_pkts_hi; 593 uint32_t rl_tx_errs_lo; 594 uint32_t rl_tx_errs_hi; 595 uint32_t rl_tx_errs; 596 uint16_t rl_missed_pkts; 597 uint16_t rl_rx_framealign_errs; 598 uint32_t rl_tx_onecoll; 599 uint32_t rl_tx_multicolls; 600 uint32_t rl_rx_ucasts_hi; 601 uint32_t rl_rx_ucasts_lo; 602 uint32_t rl_rx_bcasts_lo; 603 uint32_t rl_rx_bcasts_hi; 604 uint32_t rl_rx_mcasts; 605 uint16_t rl_tx_aborts; 606 uint16_t rl_rx_underruns; 607}; 608 609/* 610 * Rx/Tx descriptor parameters (8139C+ and 8169 only) 611 * 612 * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 613 * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 614 * due to the 8139C+. We need to put the number of descriptors in the ring 615 * structure and use that value instead. 616 */ 617#if !defined(__i386__) && !defined(__amd64__) 618#define RE_FIXUP_RX 1 619#endif 620 621#define RL_TX_DESC_CNT 64 622#define RL_RX_DESC_CNT RL_TX_DESC_CNT 623#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 624#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 625#define RL_RING_ALIGN 256 626#define RL_IFQ_MAXLEN 512 627#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 628#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 629#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 630#define RL_PKTSZ(x) ((x)/* >> 3*/) 631#ifdef RE_FIXUP_RX 632#define RE_ETHER_ALIGN sizeof(uint64_t) 633#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 634#else 635#define RE_ETHER_ALIGN 0 636#define RE_RX_DESC_BUFLEN MCLBYTES 637#endif 638 639#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 640#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 641 642/* see comment in dev/re/if_re.c */ 643#define RL_JUMBO_FRAMELEN 7440 644#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 645 646struct rl_softc; 647 648struct rl_dmaload_arg { 649 struct rl_softc *sc; 650 int rl_idx; 651 int rl_maxsegs; 652 uint32_t rl_flags; 653 struct rl_desc *rl_ring; 654}; 655 656struct rl_list_data { 657 struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 658 struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 659 int rl_tx_prodidx; 660 int rl_rx_prodidx; 661 int rl_tx_considx; 662 int rl_tx_free; 663 bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 664 bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 665 bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 666 bus_dma_tag_t rl_stag; /* stats mapping tag */ 667 bus_dmamap_t rl_smap; /* stats map */ 668 struct rl_stats *rl_stats; 669 bus_addr_t rl_stats_addr; 670 bus_dma_tag_t rl_rx_list_tag; 671 bus_dmamap_t rl_rx_list_map; 672 struct rl_desc *rl_rx_list; 673 bus_addr_t rl_rx_list_addr; 674 bus_dma_tag_t rl_tx_list_tag; 675 bus_dmamap_t rl_tx_list_map; 676 struct rl_desc *rl_tx_list; 677 bus_addr_t rl_tx_list_addr; 678}; 679 680struct rl_softc { 681 struct ifnet *rl_ifp; /* interface info */ 682 bus_space_handle_t rl_bhandle; /* bus space handle */ 683 bus_space_tag_t rl_btag; /* bus space tag */ 684 struct resource *rl_res; 685 struct resource *rl_irq; 686 void *rl_intrhand; 687 device_t rl_miibus; 688 bus_dma_tag_t rl_parent_tag; 689 bus_dma_tag_t rl_tag; 690 uint8_t rl_type; 691 int rl_eecmd_read; 692 uint8_t rl_stats_no_timeout; 693 int rl_txthresh; 694 struct rl_chain_data rl_cdata; 695 struct rl_list_data rl_ldata; 696 struct callout rl_stat_callout; 697 struct mtx rl_mtx; 698 struct mbuf *rl_head; 699 struct mbuf *rl_tail; 700 uint32_t rl_hwrev; 701 uint32_t rl_rxlenmask; 702 int rl_testmode; 703 int suspended; /* 0 = normal 1 = suspended */ 704#ifdef DEVICE_POLLING 705 int rxcycles; 706#endif 707}; 708 709#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 710#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 711#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 712 713/* 714 * register space access macros 715 */ 716#define CSR_WRITE_STREAM_4(sc, reg, val) \ 717 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 718#define CSR_WRITE_4(sc, reg, val) \ 719 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 720#define CSR_WRITE_2(sc, reg, val) \ 721 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 722#define CSR_WRITE_1(sc, reg, val) \ 723 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 724 725#define CSR_READ_4(sc, reg) \ 726 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 727#define CSR_READ_2(sc, reg) \ 728 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 729#define CSR_READ_1(sc, reg) \ 730 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 731 732#define RL_TIMEOUT 1000 733 734/* 735 * General constants that are fun to know. 736 * 737 * RealTek PCI vendor ID 738 */ 739#define RT_VENDORID 0x10EC 740 741/* 742 * RealTek chip device IDs. 743 */ 744#define RT_DEVICEID_8129 0x8129 745#define RT_DEVICEID_8138 0x8138 746#define RT_DEVICEID_8139 0x8139 747#define RT_DEVICEID_8169 0x8169 748#define RT_DEVICEID_8100 0x8100 749 750#define RT_REVID_8139CPLUS 0x20 751 752/* 753 * Accton PCI vendor ID 754 */ 755#define ACCTON_VENDORID 0x1113 756 757/* 758 * Accton MPX 5030/5038 device ID. 759 */ 760#define ACCTON_DEVICEID_5030 0x1211 761 762/* 763 * Nortel PCI vendor ID 764 */ 765#define NORTEL_VENDORID 0x126C 766 767/* 768 * Delta Electronics Vendor ID. 769 */ 770#define DELTA_VENDORID 0x1500 771 772/* 773 * Delta device IDs. 774 */ 775#define DELTA_DEVICEID_8139 0x1360 776 777/* 778 * Addtron vendor ID. 779 */ 780#define ADDTRON_VENDORID 0x4033 781 782/* 783 * Addtron device IDs. 784 */ 785#define ADDTRON_DEVICEID_8139 0x1360 786 787/* 788 * D-Link vendor ID. 789 */ 790#define DLINK_VENDORID 0x1186 791 792/* 793 * D-Link DFE-530TX+ device ID 794 */ 795#define DLINK_DEVICEID_530TXPLUS 0x1300 796 797/* 798 * D-Link DFE-5280T device ID 799 */ 800#define DLINK_DEVICEID_528T 0x4300 801 802/* 803 * D-Link DFE-690TXD device ID 804 */ 805#define DLINK_DEVICEID_690TXD 0x1340 806 807/* 808 * Corega K.K vendor ID 809 */ 810#define COREGA_VENDORID 0x1259 811 812/* 813 * Corega FEther CB-TXD device ID 814 */ 815#define COREGA_DEVICEID_FETHERCBTXD 0xa117 816 817/* 818 * Corega FEtherII CB-TXD device ID 819 */ 820#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 821 822/* 823 * Corega CG-LAPCIGT device ID 824 */ 825#define COREGA_DEVICEID_CGLAPCIGT 0xc107 826 827/* 828 * Peppercon vendor ID 829 */ 830#define PEPPERCON_VENDORID 0x1743 831 832/* 833 * Peppercon ROL-F device ID 834 */ 835#define PEPPERCON_DEVICEID_ROLF 0x8139 836 837/* 838 * Planex Communications, Inc. vendor ID 839 */ 840#define PLANEX_VENDORID 0x14ea 841 842/* 843 * Planex FNW-3800-TX device ID 844 */ 845#define PLANEX_DEVICEID_FNW3800TX 0xab07 846 847/* 848 * LevelOne vendor ID 849 */ 850#define LEVEL1_VENDORID 0x018A 851 852/* 853 * LevelOne FPC-0106TX devide ID 854 */ 855#define LEVEL1_DEVICEID_FPC0106TX 0x0106 856 857/* 858 * Compaq vendor ID 859 */ 860#define CP_VENDORID 0x021B 861 862/* 863 * Edimax vendor ID 864 */ 865#define EDIMAX_VENDORID 0x13D1 866 867/* 868 * Edimax EP-4103DL cardbus device ID 869 */ 870#define EDIMAX_DEVICEID_EP4103DL 0xAB06 871 872/* 873 * PCI low memory base and low I/O base register, and 874 * other PCI registers. 875 */ 876 877#define RL_PCI_VENDOR_ID 0x00 878#define RL_PCI_DEVICE_ID 0x02 879#define RL_PCI_COMMAND 0x04 880#define RL_PCI_STATUS 0x06 881#define RL_PCI_CLASSCODE 0x09 882#define RL_PCI_LATENCY_TIMER 0x0D 883#define RL_PCI_HEADER_TYPE 0x0E 884#define RL_PCI_LOIO 0x10 885#define RL_PCI_LOMEM 0x14 886#define RL_PCI_BIOSROM 0x30 887#define RL_PCI_INTLINE 0x3C 888#define RL_PCI_INTPIN 0x3D 889#define RL_PCI_MINGNT 0x3E 890#define RL_PCI_MINLAT 0x0F 891#define RL_PCI_RESETOPT 0x48 892#define RL_PCI_EEPROM_DATA 0x4C 893 894#define RL_PCI_CAPID 0x50 /* 8 bits */ 895#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 896#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 897#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 898 899#define RL_PSTATE_MASK 0x0003 900#define RL_PSTATE_D0 0x0000 901#define RL_PSTATE_D1 0x0002 902#define RL_PSTATE_D2 0x0002 903#define RL_PSTATE_D3 0x0003 904#define RL_PME_EN 0x0010 905#define RL_PME_STATUS 0x8000 906