if_rlreg.h revision 50703
140516Swpaul/* 240516Swpaul * Copyright (c) 1997, 1998 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 50703 1999-08-31 14:45:51Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 7940516Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 10240516Swpaul 10340516Swpaul/* 10440516Swpaul * TX config register bits 10540516Swpaul */ 10640516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 10745633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 10840516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 10945633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 11045633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 11140516Swpaul 11245633Swpaul#define RL_TXDMA_16BYTES 0x00000000 11345633Swpaul#define RL_TXDMA_32BYTES 0x00000100 11445633Swpaul#define RL_TXDMA_64BYTES 0x00000200 11545633Swpaul#define RL_TXDMA_128BYTES 0x00000300 11645633Swpaul#define RL_TXDMA_256BYTES 0x00000400 11745633Swpaul#define RL_TXDMA_512BYTES 0x00000500 11845633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 11945633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 12045633Swpaul 12140516Swpaul/* 12240516Swpaul * Transmit descriptor status register bits. 12340516Swpaul */ 12440516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 12540516Swpaul#define RL_TXSTAT_OWN 0x00002000 12640516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 12740516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 12840516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 12940516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 13040516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 13140516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 13240516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 13340516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 13440516Swpaul 13540516Swpaul/* 13640516Swpaul * Interrupt status register bits. 13740516Swpaul */ 13840516Swpaul#define RL_ISR_RX_OK 0x0001 13940516Swpaul#define RL_ISR_RX_ERR 0x0002 14040516Swpaul#define RL_ISR_TX_OK 0x0004 14140516Swpaul#define RL_ISR_TX_ERR 0x0008 14240516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 14340516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 14440516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 14540516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 14640516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 14740516Swpaul 14840516Swpaul#define RL_INTRS \ 14940516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 15040516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 15140516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 15240516Swpaul 15340516Swpaul/* 15440516Swpaul * Media status register. (8139 only) 15540516Swpaul */ 15640516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 15740516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 15840516Swpaul#define RL_MEDIASTAT_LINK 0x04 15940516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 16040516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 16140516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 16240516Swpaul 16340516Swpaul/* 16440516Swpaul * Receive config register. 16540516Swpaul */ 16640516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 16740516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 16840516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 16940516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 17040516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 17140516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 17240516Swpaul#define RL_RXCFG_WRAP 0x00000080 17345633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 17445633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 17545633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 17645633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 17740516Swpaul 17845633Swpaul#define RL_RXDMA_16BYTES 0x00000000 17945633Swpaul#define RL_RXDMA_32BYTES 0x00000100 18045633Swpaul#define RL_RXDMA_64BYTES 0x00000200 18145633Swpaul#define RL_RXDMA_128BYTES 0x00000300 18245633Swpaul#define RL_RXDMA_256BYTES 0x00000400 18345633Swpaul#define RL_RXDMA_512BYTES 0x00000500 18445633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 18545633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 18645633Swpaul 18740516Swpaul#define RL_RXBUF_8 0x00000000 18840516Swpaul#define RL_RXBUF_16 0x00000800 18940516Swpaul#define RL_RXBUF_32 0x00001000 19045633Swpaul#define RL_RXBUF_64 0x00001800 19140516Swpaul 19245633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 19345633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 19445633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 19545633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 19645633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 19745633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 19845633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 19945633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 20045633Swpaul 20140516Swpaul/* 20240516Swpaul * Bits in RX status header (included with RX'ed packet 20340516Swpaul * in ring buffer). 20440516Swpaul */ 20540516Swpaul#define RL_RXSTAT_RXOK 0x00000001 20640516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 20740516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 20840516Swpaul#define RL_RXSTAT_GIANT 0x00000008 20940516Swpaul#define RL_RXSTAT_RUNT 0x00000010 21040516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 21140516Swpaul#define RL_RXSTAT_BROAD 0x00002000 21240516Swpaul#define RL_RXSTAT_INDIV 0x00004000 21340516Swpaul#define RL_RXSTAT_MULTI 0x00008000 21440516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 21540516Swpaul 21640516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 21740516Swpaul/* 21840516Swpaul * Command register. 21940516Swpaul */ 22040516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 22140516Swpaul#define RL_CMD_TX_ENB 0x0004 22240516Swpaul#define RL_CMD_RX_ENB 0x0008 22340516Swpaul#define RL_CMD_RESET 0x0010 22440516Swpaul 22540516Swpaul/* 22640516Swpaul * EEPROM control register 22740516Swpaul */ 22840516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 22940516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 23040516Swpaul#define RL_EE_CLK 0x04 /* clock */ 23140516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 23240516Swpaul#define RL_EE_MODE (0x40|0x80) 23340516Swpaul 23440516Swpaul#define RL_EEMODE_OFF 0x00 23540516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 23640516Swpaul#define RL_EEMODE_PROGRAM 0x80 23740516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 23840516Swpaul 23940516Swpaul/* 9346 EEPROM commands */ 24040516Swpaul#define RL_EECMD_WRITE 0x140 24140516Swpaul#define RL_EECMD_READ 0x180 24240516Swpaul#define RL_EECMD_ERASE 0x1c0 24340516Swpaul 24440516Swpaul#define RL_EE_ID 0x00 24540516Swpaul#define RL_EE_PCI_VID 0x01 24640516Swpaul#define RL_EE_PCI_DID 0x02 24740516Swpaul/* Location of station address inside EEPROM */ 24840516Swpaul#define RL_EE_EADDR 0x07 24940516Swpaul 25040516Swpaul/* 25140516Swpaul * MII register (8129 only) 25240516Swpaul */ 25340516Swpaul#define RL_MII_CLK 0x01 25440516Swpaul#define RL_MII_DATAIN 0x02 25540516Swpaul#define RL_MII_DATAOUT 0x04 25640516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 25740516Swpaul 25840516Swpaul/* 25940516Swpaul * Config 0 register 26040516Swpaul */ 26140516Swpaul#define RL_CFG0_ROM0 0x01 26240516Swpaul#define RL_CFG0_ROM1 0x02 26340516Swpaul#define RL_CFG0_ROM2 0x04 26440516Swpaul#define RL_CFG0_PL0 0x08 26540516Swpaul#define RL_CFG0_PL1 0x10 26640516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 26740516Swpaul#define RL_CFG0_PCS 0x40 26840516Swpaul#define RL_CFG0_SCR 0x80 26940516Swpaul 27040516Swpaul/* 27140516Swpaul * Config 1 register 27240516Swpaul */ 27340516Swpaul#define RL_CFG1_PWRDWN 0x01 27440516Swpaul#define RL_CFG1_SLEEP 0x02 27540516Swpaul#define RL_CFG1_IOMAP 0x04 27640516Swpaul#define RL_CFG1_MEMMAP 0x08 27740516Swpaul#define RL_CFG1_RSVD 0x10 27840516Swpaul#define RL_CFG1_DRVLOAD 0x20 27940516Swpaul#define RL_CFG1_LED0 0x40 28040516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 28140516Swpaul#define RL_CFG1_LED1 0x80 28240516Swpaul 28340516Swpaul/* 28440516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 28540516Swpaul * Instead, there are only four register sets, each or which represents 28640516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 28740516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 28840516Swpaul * the registers so the chip knows where they are. 28940516Swpaul * 29040516Swpaul * We can sort of kludge together the same kind of buffer management 29140516Swpaul * used in previous drivers, but we have to do buffer copies almost all 29240516Swpaul * the time, so it doesn't really buy us much. 29340516Swpaul * 29440516Swpaul * For reception, there's just one large buffer where the chip stores 29540516Swpaul * all received packets. 29640516Swpaul */ 29740516Swpaul 29840516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 29940516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 30040516Swpaul#define RL_TX_LIST_CNT 4 30140516Swpaul#define RL_MIN_FRAMELEN 60 30248056Swpaul#define RL_TX_EARLYTHRESH (256 << 11) 30348056Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 30450703Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 30550703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 30640516Swpaul 30745633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 30845633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 30940516Swpaul 31048028Swpaul#define RL_ETHER_ALIGN 2 31148028Swpaul 31240516Swpaulstruct rl_chain_data { 31340516Swpaul u_int16_t cur_rx; 31440516Swpaul caddr_t rl_rx_buf; 31548028Swpaul caddr_t rl_rx_buf_ptr; 31640516Swpaul 31745633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 31845633Swpaul u_int8_t last_tx; 31945633Swpaul u_int8_t cur_tx; 32040516Swpaul}; 32140516Swpaul 32245633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 32345633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 32445633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 32545633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 32645633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 32745633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 32845633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 32945633Swpaul 33040516Swpaulstruct rl_type { 33140516Swpaul u_int16_t rl_vid; 33240516Swpaul u_int16_t rl_did; 33340516Swpaul char *rl_name; 33440516Swpaul}; 33540516Swpaul 33640516Swpaulstruct rl_mii_frame { 33740516Swpaul u_int8_t mii_stdelim; 33840516Swpaul u_int8_t mii_opcode; 33940516Swpaul u_int8_t mii_phyaddr; 34040516Swpaul u_int8_t mii_regaddr; 34140516Swpaul u_int8_t mii_turnaround; 34240516Swpaul u_int16_t mii_data; 34340516Swpaul}; 34440516Swpaul 34540516Swpaul/* 34640516Swpaul * MII constants 34740516Swpaul */ 34840516Swpaul#define RL_MII_STARTDELIM 0x01 34940516Swpaul#define RL_MII_READOP 0x02 35040516Swpaul#define RL_MII_WRITEOP 0x01 35140516Swpaul#define RL_MII_TURNAROUND 0x02 35240516Swpaul 35340516Swpaul#define RL_8129 1 35440516Swpaul#define RL_8139 2 35540516Swpaul 35640516Swpaulstruct rl_softc { 35740516Swpaul struct arpcom arpcom; /* interface info */ 35841569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 35941569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 36050703Swpaul struct resource *rl_res; 36150703Swpaul struct resource *rl_irq; 36250703Swpaul void *rl_intrhand; 36350703Swpaul device_t rl_miibus; 36440516Swpaul u_int8_t rl_unit; /* interface number */ 36540516Swpaul u_int8_t rl_type; 36640516Swpaul u_int8_t rl_stats_no_timeout; 36740516Swpaul struct rl_chain_data rl_cdata; 36850703Swpaul struct callout_handle rl_stat_ch; 36940516Swpaul}; 37040516Swpaul 37140516Swpaul/* 37240516Swpaul * register space access macros 37340516Swpaul */ 37440516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 37541569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 37640516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 37741569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 37840516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 37941569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 38040516Swpaul 38141569Swpaul#define CSR_READ_4(sc, reg) \ 38241569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 38341569Swpaul#define CSR_READ_2(sc, reg) \ 38441569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 38541569Swpaul#define CSR_READ_1(sc, reg) \ 38641569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 38740516Swpaul 38840516Swpaul#define RL_TIMEOUT 1000 38940516Swpaul 39040516Swpaul/* 39140516Swpaul * General constants that are fun to know. 39240516Swpaul * 39340516Swpaul * RealTek PCI vendor ID 39440516Swpaul */ 39540516Swpaul#define RT_VENDORID 0x10EC 39640516Swpaul 39740516Swpaul/* 39840516Swpaul * RealTek chip device IDs. 39940516Swpaul */ 40040516Swpaul#define RT_DEVICEID_8129 0x8129 40140516Swpaul#define RT_DEVICEID_8139 0x8139 40240516Swpaul 40340516Swpaul/* 40444238Swpaul * Accton PCI vendor ID 40544238Swpaul */ 40644238Swpaul#define ACCTON_VENDORID 0x1113 40744238Swpaul 40844238Swpaul/* 40941243Swpaul * Accton MPX 5030/5038 device ID. 41041243Swpaul */ 41141243Swpaul#define ACCTON_DEVICEID_5030 0x1211 41241243Swpaul 41341243Swpaul/* 41444238Swpaul * Delta Electronics Vendor ID. 41544238Swpaul */ 41644238Swpaul#define DELTA_VENDORID 0x1500 41744238Swpaul 41844238Swpaul/* 41944238Swpaul * Delta device IDs. 42044238Swpaul */ 42144238Swpaul#define DELTA_DEVICEID_8139 0x1360 42244238Swpaul 42344238Swpaul/* 42444238Swpaul * Addtron vendor ID. 42544238Swpaul */ 42644238Swpaul#define ADDTRON_VENDORID 0x4033 42744238Swpaul 42844238Swpaul/* 42944238Swpaul * Addtron device IDs. 43044238Swpaul */ 43144238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 43244238Swpaul 43344238Swpaul/* 43440516Swpaul * PCI low memory base and low I/O base register, and 43550703Swpaul * other PCI registers. 43640516Swpaul */ 43740516Swpaul 43840516Swpaul#define RL_PCI_VENDOR_ID 0x00 43940516Swpaul#define RL_PCI_DEVICE_ID 0x02 44040516Swpaul#define RL_PCI_COMMAND 0x04 44140516Swpaul#define RL_PCI_STATUS 0x06 44240516Swpaul#define RL_PCI_CLASSCODE 0x09 44340516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 44440516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 44540516Swpaul#define RL_PCI_LOIO 0x10 44640516Swpaul#define RL_PCI_LOMEM 0x14 44740516Swpaul#define RL_PCI_BIOSROM 0x30 44840516Swpaul#define RL_PCI_INTLINE 0x3C 44940516Swpaul#define RL_PCI_INTPIN 0x3D 45040516Swpaul#define RL_PCI_MINGNT 0x3E 45140516Swpaul#define RL_PCI_MINLAT 0x0F 45240516Swpaul#define RL_PCI_RESETOPT 0x48 45340516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 45440516Swpaul 45550097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 45650097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 45750097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 45850097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 45940516Swpaul 46040516Swpaul#define RL_PSTATE_MASK 0x0003 46140516Swpaul#define RL_PSTATE_D0 0x0000 46240516Swpaul#define RL_PSTATE_D1 0x0002 46340516Swpaul#define RL_PSTATE_D2 0x0002 46440516Swpaul#define RL_PSTATE_D3 0x0003 46540516Swpaul#define RL_PME_EN 0x0010 46640516Swpaul#define RL_PME_STATUS 0x8000 46740516Swpaul 46848028Swpaul#ifdef __alpha__ 46948028Swpaul#undef vtophys 47048028Swpaul#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 47148028Swpaul#endif 472