if_rlreg.h revision 232145
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 232145 2012-02-25 04:54:51Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39215018Syongari#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40215018Syongari#define RL_IDR2 0x0002 41215018Syongari#define RL_IDR3 0x0003 42215018Syongari#define RL_IDR4 0x0004 43215018Syongari#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 45215018Syongari#define RL_MAR0 0x0008 /* Multicast hash table */ 46215018Syongari#define RL_MAR1 0x0009 47215018Syongari#define RL_MAR2 0x000A 48215018Syongari#define RL_MAR3 0x000B 49215018Syongari#define RL_MAR4 0x000C 50215018Syongari#define RL_MAR5 0x000D 51215018Syongari#define RL_MAR6 0x000E 52215018Syongari#define RL_MAR7 0x000F 5340516Swpaul 54215018Syongari#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55215018Syongari#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56215018Syongari#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57215018Syongari#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 59215018Syongari#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60215018Syongari#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61215018Syongari#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62215018Syongari#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 64215018Syongari#define RL_RXADDR 0x0030 /* RX ring start address */ 65215018Syongari#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66215018Syongari#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67215018Syongari#define RL_COMMAND 0x0037 /* command register */ 68215018Syongari#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69215018Syongari#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70215018Syongari#define RL_IMR 0x003C /* interrupt mask register */ 71215018Syongari#define RL_ISR 0x003E /* interrupt status register */ 72215018Syongari#define RL_TXCFG 0x0040 /* transmit config */ 73215018Syongari#define RL_RXCFG 0x0044 /* receive config */ 74215018Syongari#define RL_TIMERCNT 0x0048 /* timer count register */ 75215018Syongari#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76215018Syongari#define RL_EECMD 0x0050 /* EEPROM command register */ 77232145Syongari 78232145Syongari/* RTL8139/RTL8139C+ only */ 79232145Syongari#define RL_8139_CFG0 0x0051 /* config register #0 */ 80232145Syongari#define RL_8139_CFG1 0x0052 /* config register #1 */ 81232145Syongari#define RL_8139_CFG3 0x0059 /* config register #3 */ 82232145Syongari#define RL_8139_CFG4 0x005A /* config register #4 */ 83232145Syongari#define RL_8139_CFG5 0x00D8 /* config register #5 */ 84232145Syongari 85215018Syongari#define RL_CFG0 0x0051 /* config register #0 */ 86215018Syongari#define RL_CFG1 0x0052 /* config register #1 */ 87176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 88176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 89176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 90176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 91176754Syongari /* 0057 reserved */ 92215018Syongari#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 9340516Swpaul /* 0059-005A reserved */ 94215018Syongari#define RL_MII 0x005A /* 8129 chip only */ 95215018Syongari#define RL_HALTCLK 0x005B 96215018Syongari#define RL_MULTIINTR 0x005C /* multiple interrupt */ 97215018Syongari#define RL_PCIREV 0x005E /* PCI revision value */ 9840516Swpaul /* 005F reserved */ 99215018Syongari#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 10040516Swpaul 10140516Swpaul/* Direct PHY access registers only available on 8139 */ 102215018Syongari#define RL_BMCR 0x0062 /* PHY basic mode control */ 103215018Syongari#define RL_BMSR 0x0064 /* PHY basic mode status */ 104215018Syongari#define RL_ANAR 0x0066 /* PHY autoneg advert */ 105215018Syongari#define RL_LPAR 0x0068 /* PHY link partner ability */ 106215018Syongari#define RL_ANER 0x006A /* PHY autoneg expansion */ 10740516Swpaul 108215018Syongari#define RL_DISCCNT 0x006C /* disconnect counter */ 109215018Syongari#define RL_FALSECAR 0x006E /* false carrier counter */ 110215018Syongari#define RL_NWAYTST 0x0070 /* NWAY test register */ 111215018Syongari#define RL_RX_ER 0x0072 /* RX_ER counter */ 112215018Syongari#define RL_CSCFG 0x0074 /* CS configuration register */ 11340516Swpaul 114117388Swpaul/* 115117388Swpaul * When operating in special C+ mode, some of the registers in an 116117388Swpaul * 8139C+ chip have different definitions. These are also used for 117117388Swpaul * the 8169 gigE chip. 118117388Swpaul */ 119215018Syongari#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 120215018Syongari#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 121215018Syongari#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 122215018Syongari#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 123215018Syongari#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 124215018Syongari#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 125215018Syongari#define RL_CFG2 0x0053 126215018Syongari#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 127215018Syongari#define RL_TXSTART 0x00D9 /* 8 bits */ 128215018Syongari#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 129215018Syongari#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 130215018Syongari#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 131215018Syongari#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 13240516Swpaul 13340516Swpaul/* 134117388Swpaul * Registers specific to the 8169 gigE chip 135117388Swpaul */ 136215018Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 137215018Syongari#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 138215018Syongari#define RL_PHYAR 0x0060 139215018Syongari#define RL_TBICSR 0x0064 140215018Syongari#define RL_TBI_ANAR 0x0068 141215018Syongari#define RL_TBI_LPAR 0x006A 142215018Syongari#define RL_GMEDIASTAT 0x006C /* 8 bits */ 143215018Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 144215018Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 145215018Syongari#define RL_PMCH 0x006F /* 8 bits */ 146215018Syongari#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 147215018Syongari#define RL_INTRMOD 0x00E2 /* 16 bits */ 148117388Swpaul 149117388Swpaul/* 15040516Swpaul * TX config register bits 15140516Swpaul */ 152215018Syongari#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 153215018Syongari#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 154227914Syongari#define RL_TXCFG_QUEUE_EMPTY 0x00000800 /* 8168E-VL or higher */ 155215018Syongari#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 156215018Syongari#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 157215018Syongari#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 158215018Syongari#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 159215018Syongari#define RL_TXCFG_HWREV 0x7CC00000 16040516Swpaul 161215018Syongari#define RL_LOOPTEST_OFF 0x00000000 162215018Syongari#define RL_LOOPTEST_ON 0x00020000 163215018Syongari#define RL_LOOPTEST_ON_CPLUS 0x00060000 164119868Swpaul 165159962Swpaul/* Known revision codes. */ 166117388Swpaul 167215018Syongari#define RL_HWREV_8169 0x00000000 168215018Syongari#define RL_HWREV_8169S 0x00800000 169215018Syongari#define RL_HWREV_8110S 0x04000000 170215018Syongari#define RL_HWREV_8169_8110SB 0x10000000 171215018Syongari#define RL_HWREV_8169_8110SC 0x18000000 172218760Syongari#define RL_HWREV_8401E 0x24000000 173215018Syongari#define RL_HWREV_8102EL 0x24800000 174215018Syongari#define RL_HWREV_8102EL_SPIN1 0x24C00000 175215018Syongari#define RL_HWREV_8168D 0x28000000 176215018Syongari#define RL_HWREV_8168DP 0x28800000 177215018Syongari#define RL_HWREV_8168E 0x2C000000 178217498Syongari#define RL_HWREV_8168E_VL 0x2C800000 179217524Syongari#define RL_HWREV_8168B_SPIN1 0x30000000 180215018Syongari#define RL_HWREV_8100E 0x30800000 181215018Syongari#define RL_HWREV_8101E 0x34000000 182215018Syongari#define RL_HWREV_8102E 0x34800000 183215018Syongari#define RL_HWREV_8103E 0x34C00000 184217524Syongari#define RL_HWREV_8168B_SPIN2 0x38000000 185217524Syongari#define RL_HWREV_8168B_SPIN3 0x38400000 186215018Syongari#define RL_HWREV_8168C 0x3C000000 187215018Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 188215018Syongari#define RL_HWREV_8168CP 0x3C800000 189217911Syongari#define RL_HWREV_8105E 0x40800000 190227638Syongari#define RL_HWREV_8105E_SPIN1 0x40C00000 191227587Syongari#define RL_HWREV_8402 0x44000000 192227639Syongari#define RL_HWREV_8168F 0x48000000 193227590Syongari#define RL_HWREV_8411 0x48800000 194215018Syongari#define RL_HWREV_8139 0x60000000 195215018Syongari#define RL_HWREV_8139A 0x70000000 196215018Syongari#define RL_HWREV_8139AG 0x70800000 197215018Syongari#define RL_HWREV_8139B 0x78000000 198215018Syongari#define RL_HWREV_8130 0x7C000000 199215018Syongari#define RL_HWREV_8139C 0x74000000 200215018Syongari#define RL_HWREV_8139D 0x74400000 201215018Syongari#define RL_HWREV_8139CPLUS 0x74800000 202215018Syongari#define RL_HWREV_8101 0x74C00000 203215018Syongari#define RL_HWREV_8100 0x78800000 204215018Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 205215018Syongari#define RL_HWREV_8169_8110SCE 0x98000000 206159962Swpaul 207215018Syongari#define RL_TXDMA_16BYTES 0x00000000 208215018Syongari#define RL_TXDMA_32BYTES 0x00000100 209215018Syongari#define RL_TXDMA_64BYTES 0x00000200 210215018Syongari#define RL_TXDMA_128BYTES 0x00000300 211215018Syongari#define RL_TXDMA_256BYTES 0x00000400 212215018Syongari#define RL_TXDMA_512BYTES 0x00000500 213215018Syongari#define RL_TXDMA_1024BYTES 0x00000600 214215018Syongari#define RL_TXDMA_2048BYTES 0x00000700 21545633Swpaul 21640516Swpaul/* 21740516Swpaul * Transmit descriptor status register bits. 21840516Swpaul */ 219215018Syongari#define RL_TXSTAT_LENMASK 0x00001FFF 220215018Syongari#define RL_TXSTAT_OWN 0x00002000 221215018Syongari#define RL_TXSTAT_TX_UNDERRUN 0x00004000 222215018Syongari#define RL_TXSTAT_TX_OK 0x00008000 223215018Syongari#define RL_TXSTAT_EARLY_THRESH 0x003F0000 224215018Syongari#define RL_TXSTAT_COLLCNT 0x0F000000 225215018Syongari#define RL_TXSTAT_CARR_HBEAT 0x10000000 226215018Syongari#define RL_TXSTAT_OUTOFWIN 0x20000000 227215018Syongari#define RL_TXSTAT_TXABRT 0x40000000 228215018Syongari#define RL_TXSTAT_CARRLOSS 0x80000000 22940516Swpaul 23040516Swpaul/* 23140516Swpaul * Interrupt status register bits. 23240516Swpaul */ 233215018Syongari#define RL_ISR_RX_OK 0x0001 234215018Syongari#define RL_ISR_RX_ERR 0x0002 235215018Syongari#define RL_ISR_TX_OK 0x0004 236215018Syongari#define RL_ISR_TX_ERR 0x0008 237215018Syongari#define RL_ISR_RX_OVERRUN 0x0010 238215018Syongari#define RL_ISR_PKT_UNDERRUN 0x0020 239215018Syongari#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 240215018Syongari#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 241215018Syongari#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 242215018Syongari#define RL_ISR_SWI 0x0100 /* C+ only */ 243215018Syongari#define RL_ISR_CABLE_LEN_CHGD 0x2000 244215018Syongari#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 245215018Syongari#define RL_ISR_TIMEOUT_EXPIRED 0x4000 246215018Syongari#define RL_ISR_SYSTEM_ERR 0x8000 24740516Swpaul 248215018Syongari#define RL_INTRS \ 24940516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 25040516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 25140516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 25240516Swpaul 253159962Swpaul#ifdef RE_TX_MODERATION 254215018Syongari#define RL_INTRS_CPLUS \ 255119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 256117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 257117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 258159962Swpaul#else 259215018Syongari#define RL_INTRS_CPLUS \ 260159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 261159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 262159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 263159962Swpaul#endif 264117388Swpaul 26540516Swpaul/* 26640516Swpaul * Media status register. (8139 only) 26740516Swpaul */ 268215018Syongari#define RL_MEDIASTAT_RXPAUSE 0x01 269215018Syongari#define RL_MEDIASTAT_TXPAUSE 0x02 270215018Syongari#define RL_MEDIASTAT_LINK 0x04 271215018Syongari#define RL_MEDIASTAT_SPEED10 0x08 272215018Syongari#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 273215018Syongari#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 27440516Swpaul 27540516Swpaul/* 27640516Swpaul * Receive config register. 27740516Swpaul */ 278215018Syongari#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 279215018Syongari#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 280215018Syongari#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 281215018Syongari#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 282215018Syongari#define RL_RXCFG_RX_RUNT 0x00000010 283215018Syongari#define RL_RXCFG_RX_ERRPKT 0x00000020 284215018Syongari#define RL_RXCFG_WRAP 0x00000080 285215018Syongari#define RL_RXCFG_MAXDMA 0x00000700 286215018Syongari#define RL_RXCFG_BUFSZ 0x00001800 287215018Syongari#define RL_RXCFG_FIFOTHRESH 0x0000E000 288215018Syongari#define RL_RXCFG_EARLYTHRESH 0x07000000 28940516Swpaul 290215018Syongari#define RL_RXDMA_16BYTES 0x00000000 291215018Syongari#define RL_RXDMA_32BYTES 0x00000100 292215018Syongari#define RL_RXDMA_64BYTES 0x00000200 293215018Syongari#define RL_RXDMA_128BYTES 0x00000300 294215018Syongari#define RL_RXDMA_256BYTES 0x00000400 295215018Syongari#define RL_RXDMA_512BYTES 0x00000500 296215018Syongari#define RL_RXDMA_1024BYTES 0x00000600 297215018Syongari#define RL_RXDMA_UNLIMITED 0x00000700 29845633Swpaul 299215018Syongari#define RL_RXBUF_8 0x00000000 300215018Syongari#define RL_RXBUF_16 0x00000800 301215018Syongari#define RL_RXBUF_32 0x00001000 302215018Syongari#define RL_RXBUF_64 0x00001800 30340516Swpaul 304215018Syongari#define RL_RXFIFO_16BYTES 0x00000000 305215018Syongari#define RL_RXFIFO_32BYTES 0x00002000 306215018Syongari#define RL_RXFIFO_64BYTES 0x00004000 307215018Syongari#define RL_RXFIFO_128BYTES 0x00006000 308215018Syongari#define RL_RXFIFO_256BYTES 0x00008000 309215018Syongari#define RL_RXFIFO_512BYTES 0x0000A000 310215018Syongari#define RL_RXFIFO_1024BYTES 0x0000C000 311215018Syongari#define RL_RXFIFO_NOTHRESH 0x0000E000 31245633Swpaul 31340516Swpaul/* 31440516Swpaul * Bits in RX status header (included with RX'ed packet 31540516Swpaul * in ring buffer). 31640516Swpaul */ 317215018Syongari#define RL_RXSTAT_RXOK 0x00000001 318215018Syongari#define RL_RXSTAT_ALIGNERR 0x00000002 319215018Syongari#define RL_RXSTAT_CRCERR 0x00000004 320215018Syongari#define RL_RXSTAT_GIANT 0x00000008 321215018Syongari#define RL_RXSTAT_RUNT 0x00000010 322215018Syongari#define RL_RXSTAT_BADSYM 0x00000020 323215018Syongari#define RL_RXSTAT_BROAD 0x00002000 324215018Syongari#define RL_RXSTAT_INDIV 0x00004000 325215018Syongari#define RL_RXSTAT_MULTI 0x00008000 326215018Syongari#define RL_RXSTAT_LENMASK 0xFFFF0000 32740516Swpaul 328215018Syongari#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 32940516Swpaul/* 33040516Swpaul * Command register. 33140516Swpaul */ 332215018Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 333215018Syongari#define RL_CMD_TX_ENB 0x0004 334215018Syongari#define RL_CMD_RX_ENB 0x0008 335215018Syongari#define RL_CMD_RESET 0x0010 336215018Syongari#define RL_CMD_STOPREQ 0x0080 33740516Swpaul 33840516Swpaul/* 339184515Simp * Twister register values. These are completely undocumented and derived 340184515Simp * from public sources. 341184515Simp */ 342215018Syongari#define RL_CSCFG_LINK_OK 0x0400 343215018Syongari#define RL_CSCFG_CHANGE 0x0800 344215018Syongari#define RL_CSCFG_STATUS 0xf000 345215018Syongari#define RL_CSCFG_ROW3 0x7000 346215018Syongari#define RL_CSCFG_ROW2 0x3000 347215018Syongari#define RL_CSCFG_ROW1 0x1000 348215018Syongari#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 349215018Syongari#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 350184515Simp 351215018Syongari#define RL_NWAYTST_RESET 0 352215018Syongari#define RL_NWAYTST_CBL_TEST 0x20 353184515Simp 354215018Syongari#define RL_PARA78 0x78 355215018Syongari#define RL_PARA78_DEF 0x78fa8388 356215018Syongari#define RL_PARA7C 0x7C 357215018Syongari#define RL_PARA7C_DEF 0xcb38de43 358215018Syongari#define RL_PARA7C_RETUNE 0xfb38de03 359184515Simp/* 36040516Swpaul * EEPROM control register 36140516Swpaul */ 362215018Syongari#define RL_EE_DATAOUT 0x01 /* Data out */ 363215018Syongari#define RL_EE_DATAIN 0x02 /* Data in */ 364215018Syongari#define RL_EE_CLK 0x04 /* clock */ 365215018Syongari#define RL_EE_SEL 0x08 /* chip select */ 366215018Syongari#define RL_EE_MODE (0x40|0x80) 36740516Swpaul 368215018Syongari#define RL_EEMODE_OFF 0x00 369215018Syongari#define RL_EEMODE_AUTOLOAD 0x40 370215018Syongari#define RL_EEMODE_PROGRAM 0x80 371215018Syongari#define RL_EEMODE_WRITECFG (0x80|0x40) 37240516Swpaul 37340516Swpaul/* 9346 EEPROM commands */ 374215018Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 375215018Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 376159962Swpaul 377215018Syongari#define RL_9346_WRITE 0x5 378215018Syongari#define RL_9346_READ 0x6 379215018Syongari#define RL_9346_ERASE 0x7 380215018Syongari#define RL_9346_EWEN 0x4 381215018Syongari#define RL_9346_EWEN_ADDR 0x30 382215018Syongari#define RL_9456_EWDS 0x4 383215018Syongari#define RL_9346_EWDS_ADDR 0x00 384159962Swpaul 385215018Syongari#define RL_EECMD_WRITE 0x140 386215018Syongari#define RL_EECMD_READ_6BIT 0x180 387215018Syongari#define RL_EECMD_READ_8BIT 0x600 388215018Syongari#define RL_EECMD_ERASE 0x1c0 38940516Swpaul 390215018Syongari#define RL_EE_ID 0x00 391215018Syongari#define RL_EE_PCI_VID 0x01 392215018Syongari#define RL_EE_PCI_DID 0x02 39340516Swpaul/* Location of station address inside EEPROM */ 394215018Syongari#define RL_EE_EADDR 0x07 39540516Swpaul 39640516Swpaul/* 39740516Swpaul * MII register (8129 only) 39840516Swpaul */ 399215018Syongari#define RL_MII_CLK 0x01 400215018Syongari#define RL_MII_DATAIN 0x02 401215018Syongari#define RL_MII_DATAOUT 0x04 402215018Syongari#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 40340516Swpaul 40440516Swpaul/* 40540516Swpaul * Config 0 register 40640516Swpaul */ 407215018Syongari#define RL_CFG0_ROM0 0x01 408215018Syongari#define RL_CFG0_ROM1 0x02 409215018Syongari#define RL_CFG0_ROM2 0x04 410215018Syongari#define RL_CFG0_PL0 0x08 411215018Syongari#define RL_CFG0_PL1 0x10 412215018Syongari#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 413215018Syongari#define RL_CFG0_PCS 0x40 414215018Syongari#define RL_CFG0_SCR 0x80 41540516Swpaul 41640516Swpaul/* 41740516Swpaul * Config 1 register 41840516Swpaul */ 419215018Syongari#define RL_CFG1_PWRDWN 0x01 420215019Syongari#define RL_CFG1_PME 0x01 421215018Syongari#define RL_CFG1_SLEEP 0x02 422215018Syongari#define RL_CFG1_VPDEN 0x02 423215018Syongari#define RL_CFG1_IOMAP 0x04 424215018Syongari#define RL_CFG1_MEMMAP 0x08 425215018Syongari#define RL_CFG1_RSVD 0x10 426176754Syongari#define RL_CFG1_LWACT 0x10 427215018Syongari#define RL_CFG1_DRVLOAD 0x20 428215018Syongari#define RL_CFG1_LED0 0x40 429215018Syongari#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 430215018Syongari#define RL_CFG1_LED1 0x80 43140516Swpaul 43240516Swpaul/* 433176754Syongari * Config 2 register 434176754Syongari */ 435176754Syongari#define RL_CFG2_PCI33MHZ 0x00 436176754Syongari#define RL_CFG2_PCI66MHZ 0x01 437176754Syongari#define RL_CFG2_PCI64BIT 0x08 438176754Syongari#define RL_CFG2_AUXPWR 0x10 439177522Syongari#define RL_CFG2_MSI 0x20 440176754Syongari 441176754Syongari/* 442176754Syongari * Config 3 register 443176754Syongari */ 444176754Syongari#define RL_CFG3_GRANTSEL 0x80 445176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 446176754Syongari#define RL_CFG3_WOL_LINK 0x10 447217499Syongari#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 448176754Syongari#define RL_CFG3_FAST_B2B 0x01 449176754Syongari 450176754Syongari/* 451176754Syongari * Config 4 register 452176754Syongari */ 453176754Syongari#define RL_CFG4_LWPTN 0x04 454176754Syongari#define RL_CFG4_LWPME 0x10 455217499Syongari#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 456176754Syongari 457176754Syongari/* 458176754Syongari * Config 5 register 459176754Syongari */ 460176754Syongari#define RL_CFG5_WOL_BCAST 0x40 461176754Syongari#define RL_CFG5_WOL_MCAST 0x20 462176754Syongari#define RL_CFG5_WOL_UCAST 0x10 463176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 464176754Syongari#define RL_CFG5_PME_STS 0x01 465176754Syongari 466176754Syongari/* 467117388Swpaul * 8139C+ register definitions 468117388Swpaul */ 469117388Swpaul 470117388Swpaul/* RL_DUMPSTATS_LO register */ 471117388Swpaul 472215018Syongari#define RL_DUMPSTATS_START 0x00000008 473117388Swpaul 474117388Swpaul/* Transmit start register */ 475117388Swpaul 476215018Syongari#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 477215018Syongari#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 478215018Syongari#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 479117388Swpaul 480120043Swpaul/* 481120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 482120043Swpaul */ 483215018Syongari#define RL_CFG2_BUSFREQ 0x07 484215018Syongari#define RL_CFG2_BUSWIDTH 0x08 485215018Syongari#define RL_CFG2_AUXPWRSTS 0x10 486120043Swpaul 487215018Syongari#define RL_BUSFREQ_33MHZ 0x00 488215018Syongari#define RL_BUSFREQ_66MHZ 0x01 489215019Syongari 490215018Syongari#define RL_BUSWIDTH_32BITS 0x00 491215018Syongari#define RL_BUSWIDTH_64BITS 0x08 492120043Swpaul 493117388Swpaul/* C+ mode command register */ 494117388Swpaul 495215018Syongari#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 496215018Syongari#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 497215018Syongari#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 498215018Syongari#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 499215018Syongari#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 500215018Syongari#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 501180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 502180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 503180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 504180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 505180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 506180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 507180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 508180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 509180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 510117388Swpaul 511117388Swpaul/* C+ early transmit threshold */ 512117388Swpaul 513215019Syongari#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 514117388Swpaul 515217902Syongari/* Timer interrupt register */ 516217902Syongari#define RL_TIMERINT_8169_VAL 0x00001FFF 517217902Syongari#define RL_TIMER_MIN 0 518217902Syongari#define RL_TIMER_MAX 65 /* 65.528us */ 519217902Syongari#define RL_TIMER_DEFAULT RL_TIMER_MAX 520217902Syongari#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 521217902Syongari#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 522217902Syongari 523117388Swpaul/* 524117388Swpaul * Gigabit PHY access register (8169 only) 525117388Swpaul */ 526117388Swpaul 527215018Syongari#define RL_PHYAR_PHYDATA 0x0000FFFF 528215018Syongari#define RL_PHYAR_PHYREG 0x001F0000 529215018Syongari#define RL_PHYAR_BUSY 0x80000000 530117388Swpaul 531117388Swpaul/* 532117388Swpaul * Gigabit media status (8169 only) 533117388Swpaul */ 534215018Syongari#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 535215018Syongari#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 536215018Syongari#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 537215018Syongari#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 538215018Syongari#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 539215018Syongari#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 540215018Syongari#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 541215018Syongari#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 542117388Swpaul 543117388Swpaul/* 54440516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 54540516Swpaul * Instead, there are only four register sets, each or which represents 54640516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 54740516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 54840516Swpaul * the registers so the chip knows where they are. 54940516Swpaul * 55040516Swpaul * We can sort of kludge together the same kind of buffer management 55140516Swpaul * used in previous drivers, but we have to do buffer copies almost all 55240516Swpaul * the time, so it doesn't really buy us much. 55340516Swpaul * 55440516Swpaul * For reception, there's just one large buffer where the chip stores 55540516Swpaul * all received packets. 55640516Swpaul */ 55740516Swpaul 558215018Syongari#define RL_RX_BUF_SZ RL_RXBUF_64 559215018Syongari#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 560215018Syongari#define RL_TX_LIST_CNT 4 561215018Syongari#define RL_MIN_FRAMELEN 60 562184240Syongari#define RL_TX_8139_BUF_ALIGN 4 563184240Syongari#define RL_RX_8139_BUF_ALIGN 8 564184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 565184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 566215019Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 567215018Syongari#define RL_TXTHRESH(x) ((x) << 11) 568215018Syongari#define RL_TX_THRESH_INIT 96 569215018Syongari#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 570215018Syongari#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 571215018Syongari#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 57240516Swpaul 573215018Syongari#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 574215018Syongari#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 57540516Swpaul 576215018Syongari#define RL_ETHER_ALIGN 2 57748028Swpaul 578177771Syongari/* 579177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 580177771Syongari */ 581177771Syongari#define RL_IP4CSUMTX_MINLEN 28 582177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 583177771Syongari 58440516Swpaulstruct rl_chain_data { 585131605Sbms uint16_t cur_rx; 586131605Sbms uint8_t *rl_rx_buf; 587131605Sbms uint8_t *rl_rx_buf_ptr; 58840516Swpaul 58945633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 59081713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 591184240Syongari bus_dma_tag_t rl_tx_tag; 592184240Syongari bus_dma_tag_t rl_rx_tag; 593184240Syongari bus_dmamap_t rl_rx_dmamap; 594184240Syongari bus_addr_t rl_rx_buf_paddr; 595131605Sbms uint8_t last_tx; 596131605Sbms uint8_t cur_tx; 59740516Swpaul}; 59840516Swpaul 599215018Syongari#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 600215018Syongari#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 601215018Syongari#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 602215018Syongari#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 603215018Syongari#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 604215018Syongari#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 605215018Syongari#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 606215018Syongari#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 607215018Syongari#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 60845633Swpaul 60940516Swpaulstruct rl_type { 610131605Sbms uint16_t rl_vid; 611131605Sbms uint16_t rl_did; 612117388Swpaul int rl_basetype; 613226995Smarius const char *rl_name; 61440516Swpaul}; 61540516Swpaul 616117388Swpaulstruct rl_hwrev { 617131605Sbms uint32_t rl_rev; 618117388Swpaul int rl_type; 619226995Smarius const char *rl_desc; 620217499Syongari int rl_max_mtu; 621117388Swpaul}; 622117388Swpaul 623215018Syongari#define RL_8129 1 624215018Syongari#define RL_8139 2 625215018Syongari#define RL_8139CPLUS 3 626215018Syongari#define RL_8169 4 62740516Swpaul 628215018Syongari#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 629117388Swpaul (x)->rl_type == RL_8169) 630117388Swpaul 631117388Swpaul/* 632117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 633117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 634117388Swpaul * must be allocated in contiguous blocks that are aligned on a 635117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 636117388Swpaul */ 637117388Swpaul 638117388Swpaul/* 639117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 640117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 641117388Swpaul * the checksum offload bits are disabled. The structure layout is 642117388Swpaul * the same for RX and TX descriptors 643117388Swpaul */ 644117388Swpaul 645117388Swpaulstruct rl_desc { 646131605Sbms uint32_t rl_cmdstat; 647131605Sbms uint32_t rl_vlanctl; 648131605Sbms uint32_t rl_bufaddr_lo; 649131605Sbms uint32_t rl_bufaddr_hi; 650117388Swpaul}; 651117388Swpaul 652215018Syongari#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 653215018Syongari#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 654215018Syongari#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 655215018Syongari#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 656215018Syongari#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 657215018Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 658215018Syongari#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 659215018Syongari#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 660215018Syongari#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 661215018Syongari#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 662215018Syongari#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 663117388Swpaul 664215018Syongari#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 665215018Syongari#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 666180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 667180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 668215019Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 669215019Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 670217246Syongari#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 671217246Syongari#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 672117388Swpaul 673117388Swpaul/* 674117388Swpaul * Error bits are valid only on the last descriptor of a frame 675117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 676117388Swpaul */ 677117388Swpaul 678215018Syongari#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 679215018Syongari#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 680215018Syongari#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 681215018Syongari#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 682215018Syongari#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 683215018Syongari#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 684215018Syongari#define RL_TDESC_STAT_OWN 0x80000000 685117388Swpaul 686117388Swpaul/* 687117388Swpaul * RX descriptor cmd/vlan definitions 688117388Swpaul */ 689117388Swpaul 690215018Syongari#define RL_RDESC_CMD_EOR 0x40000000 691215018Syongari#define RL_RDESC_CMD_OWN 0x80000000 692215018Syongari#define RL_RDESC_CMD_BUFLEN 0x00001FFF 693117388Swpaul 694215018Syongari#define RL_RDESC_STAT_OWN 0x80000000 695215018Syongari#define RL_RDESC_STAT_EOR 0x40000000 696215018Syongari#define RL_RDESC_STAT_SOF 0x20000000 697215018Syongari#define RL_RDESC_STAT_EOF 0x10000000 698215018Syongari#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 699215018Syongari#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 700215018Syongari#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 701215018Syongari#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 702215018Syongari#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 703215018Syongari#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 704215018Syongari#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 705215018Syongari#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 706215018Syongari#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 707215018Syongari#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 708215018Syongari#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 709180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 710180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 711215018Syongari#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 712215018Syongari#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 713215018Syongari#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 714215018Syongari#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 715215018Syongari#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 716215018Syongari#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 717135896Sjmg RL_RDESC_STAT_CRCERR) 718117388Swpaul 719215018Syongari#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 720117388Swpaul (rl_vlandata valid)*/ 721215018Syongari#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 722180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 723180176Syongari#define RL_RDESC_IPV6 0x80000000 724180176Syongari#define RL_RDESC_IPV4 0x40000000 725117388Swpaul 726215018Syongari#define RL_PROTOID_NONIP 0x00000000 727215018Syongari#define RL_PROTOID_TCPIP 0x00010000 728215018Syongari#define RL_PROTOID_UDPIP 0x00020000 729215018Syongari#define RL_PROTOID_IP 0x00030000 730215018Syongari#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 731117388Swpaul RL_PROTOID_TCPIP) 732215018Syongari#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 733117388Swpaul RL_PROTOID_UDPIP) 734117388Swpaul 735117388Swpaul/* 736117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 737117388Swpaul */ 738117388Swpaulstruct rl_stats { 739214844Syongari uint64_t rl_tx_pkts; 740214844Syongari uint64_t rl_rx_pkts; 741214844Syongari uint64_t rl_tx_errs; 742214844Syongari uint32_t rl_rx_errs; 743131605Sbms uint16_t rl_missed_pkts; 744131605Sbms uint16_t rl_rx_framealign_errs; 745131605Sbms uint32_t rl_tx_onecoll; 746131605Sbms uint32_t rl_tx_multicolls; 747214844Syongari uint64_t rl_rx_ucasts; 748214844Syongari uint64_t rl_rx_bcasts; 749131605Sbms uint32_t rl_rx_mcasts; 750131605Sbms uint16_t rl_tx_aborts; 751131605Sbms uint16_t rl_rx_underruns; 752117388Swpaul}; 753117388Swpaul 754135467Sjmg/* 755135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 756135467Sjmg * 757175337Syongari * 8139C+ 758175337Syongari * Number of descriptors supported : up to 64 759175337Syongari * Descriptor alignment : 256 bytes 760175337Syongari * Tx buffer : At least 4 bytes in length. 761175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 762215019Syongari * 763175337Syongari * 8169 764175337Syongari * Number of descriptors supported : up to 1024 765175337Syongari * Descriptor alignment : 256 bytes 766175337Syongari * Tx buffer : At least 4 bytes in length. 767175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 768135467Sjmg */ 769164460Syongari#ifndef __NO_STRICT_ALIGNMENT 770215018Syongari#define RE_FIXUP_RX 1 771135896Sjmg#endif 772135896Sjmg 773215018Syongari#define RL_8169_TX_DESC_CNT 256 774215018Syongari#define RL_8169_RX_DESC_CNT 256 775215018Syongari#define RL_8139_TX_DESC_CNT 64 776215018Syongari#define RL_8139_RX_DESC_CNT 64 777215018Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 778215018Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 779217499Syongari#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 780175337Syongari#define RL_NTXSEGS 32 781159962Swpaul 782215018Syongari#define RL_RING_ALIGN 256 783215018Syongari#define RL_DUMP_ALIGN 64 784215018Syongari#define RL_IFQ_MAXLEN 512 785215018Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 786215018Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 787215018Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 788215018Syongari#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 789215018Syongari#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 790215018Syongari#define RL_PKTSZ(x) ((x)/* >> 3*/) 791135896Sjmg#ifdef RE_FIXUP_RX 792215018Syongari#define RE_ETHER_ALIGN sizeof(uint64_t) 793215018Syongari#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 794135896Sjmg#else 795215018Syongari#define RE_ETHER_ALIGN 0 796215018Syongari#define RE_RX_DESC_BUFLEN MCLBYTES 797135896Sjmg#endif 798117388Swpaul 799188474Syongari#define RL_MSI_MESSAGES 1 800171560Syongari 801215018Syongari#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 802215018Syongari#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 803118712Swpaul 804181270Syongari/* 805181270Syongari * The number of bits reserved for MSS in RealTek controllers is 806181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 807181270Syongari * as upper stack should not generate TCP segments with MSS greater 808181270Syongari * than the limit. 809181270Syongari */ 810181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 811181270Syongari 812135896Sjmg/* see comment in dev/re/if_re.c */ 813215018Syongari#define RL_JUMBO_FRAMELEN 7440 814217499Syongari#define RL_JUMBO_MTU \ 815217499Syongari (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 816217499Syongari#define RL_JUMBO_MTU_6K \ 817217499Syongari ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 818217499Syongari#define RL_JUMBO_MTU_9K \ 819217499Syongari ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 820217499Syongari#define RL_MTU \ 821176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 822119868Swpaul 823175337Syongaristruct rl_txdesc { 824175337Syongari struct mbuf *tx_m; 825175337Syongari bus_dmamap_t tx_dmamap; 826175337Syongari}; 827117388Swpaul 828175337Syongaristruct rl_rxdesc { 829175337Syongari struct mbuf *rx_m; 830175337Syongari bus_dmamap_t rx_dmamap; 831175337Syongari bus_size_t rx_size; 832117388Swpaul}; 833117388Swpaul 834117388Swpaulstruct rl_list_data { 835175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 836175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 837217499Syongari struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 838175337Syongari int rl_tx_desc_cnt; 839175337Syongari int rl_rx_desc_cnt; 840117388Swpaul int rl_tx_prodidx; 841117388Swpaul int rl_rx_prodidx; 842117388Swpaul int rl_tx_considx; 843117388Swpaul int rl_tx_free; 844175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 845175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 846217499Syongari bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 847175337Syongari bus_dmamap_t rl_rx_sparemap; 848217499Syongari bus_dmamap_t rl_jrx_sparemap; 849117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 850117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 851117388Swpaul struct rl_stats *rl_stats; 852118712Swpaul bus_addr_t rl_stats_addr; 853117388Swpaul bus_dma_tag_t rl_rx_list_tag; 854117388Swpaul bus_dmamap_t rl_rx_list_map; 855117388Swpaul struct rl_desc *rl_rx_list; 856118712Swpaul bus_addr_t rl_rx_list_addr; 857117388Swpaul bus_dma_tag_t rl_tx_list_tag; 858117388Swpaul bus_dmamap_t rl_tx_list_map; 859117388Swpaul struct rl_desc *rl_tx_list; 860118712Swpaul bus_addr_t rl_tx_list_addr; 861117388Swpaul}; 862117388Swpaul 863184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 864184515Simp 86540516Swpaulstruct rl_softc { 866147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 86741569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 86841569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 869159962Swpaul device_t rl_dev; 87050703Swpaul struct resource *rl_res; 871180169Syongari int rl_res_id; 872180169Syongari int rl_res_type; 873217857Syongari struct resource *rl_res_pba; 874171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 875171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 87650703Swpaul device_t rl_miibus; 87781713Swpaul bus_dma_tag_t rl_parent_tag; 878131605Sbms uint8_t rl_type; 879226995Smarius const struct rl_hwrev *rl_hwrev; 88067931Swpaul int rl_eecmd_read; 881159962Swpaul int rl_eewidth; 882227593Syongari int rl_expcap; 88352426Swpaul int rl_txthresh; 884232145Syongari bus_size_t rl_cfg0; 885232145Syongari bus_size_t rl_cfg1; 886232145Syongari bus_size_t rl_cfg2; 887232145Syongari bus_size_t rl_cfg3; 888232145Syongari bus_size_t rl_cfg4; 889232145Syongari bus_size_t rl_cfg5; 89040516Swpaul struct rl_chain_data rl_cdata; 891117388Swpaul struct rl_list_data rl_ldata; 892150720Sjhb struct callout rl_stat_callout; 893164811Sru int rl_watchdog_timer; 89467087Swpaul struct mtx rl_mtx; 895119868Swpaul struct mbuf *rl_head; 896119868Swpaul struct mbuf *rl_tail; 897131605Sbms uint32_t rl_rxlenmask; 898119868Swpaul int rl_testmode; 899168828Syongari int rl_if_flags; 900184559Simp int rl_twister_enable; 901184515Simp enum rl_twist rl_twister; 902184515Simp int rl_twist_row; 903184515Simp int rl_twist_col; 90486822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 90594883Sluigi#ifdef DEVICE_POLLING 90694883Sluigi int rxcycles; 90794883Sluigi#endif 908159962Swpaul 909159962Swpaul struct task rl_inttask; 910159962Swpaul 911159962Swpaul int rl_txstart; 912217902Syongari int rl_int_rx_act; 913217902Syongari int rl_int_rx_mod; 914180171Syongari uint32_t rl_flags; 915227914Syongari#define RL_FLAG_MSI 0x00000001 916227914Syongari#define RL_FLAG_AUTOPAD 0x00000002 917227914Syongari#define RL_FLAG_PHYWAKE_PM 0x00000004 918227914Syongari#define RL_FLAG_PHYWAKE 0x00000008 919227914Syongari#define RL_FLAG_JUMBOV2 0x00000010 920227914Syongari#define RL_FLAG_PAR 0x00000020 921227914Syongari#define RL_FLAG_DESCV2 0x00000040 922227914Syongari#define RL_FLAG_MACSTAT 0x00000080 923227914Syongari#define RL_FLAG_FASTETHER 0x00000100 924227914Syongari#define RL_FLAG_CMDSTOP 0x00000200 925227914Syongari#define RL_FLAG_MACRESET 0x00000400 926227914Syongari#define RL_FLAG_MSIX 0x00000800 927227914Syongari#define RL_FLAG_WOLRXENB 0x00001000 928227914Syongari#define RL_FLAG_MACSLEEP 0x00002000 929227914Syongari#define RL_FLAG_WAIT_TXPOLL 0x00004000 930227914Syongari#define RL_FLAG_CMDSTOP_WAIT_TXQ 0x00008000 931227916Syongari#define RL_FLAG_WOL_MANLINK 0x00010000 932227914Syongari#define RL_FLAG_PCIE 0x40000000 933227914Syongari#define RL_FLAG_LINK 0x80000000 93440516Swpaul}; 93540516Swpaul 93672200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 93772200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 938122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 93967087Swpaul 94040516Swpaul/* 94140516Swpaul * register space access macros 94240516Swpaul */ 943215018Syongari#define CSR_WRITE_STREAM_4(sc, reg, val) \ 944119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 945215018Syongari#define CSR_WRITE_4(sc, reg, val) \ 94641569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 947215018Syongari#define CSR_WRITE_2(sc, reg, val) \ 94841569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 949215018Syongari#define CSR_WRITE_1(sc, reg, val) \ 95041569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 95140516Swpaul 952215018Syongari#define CSR_READ_4(sc, reg) \ 95341569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 954215018Syongari#define CSR_READ_2(sc, reg) \ 95541569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 956215018Syongari#define CSR_READ_1(sc, reg) \ 95741569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 95840516Swpaul 959226995Smarius#define CSR_BARRIER(sc, reg, length, flags) \ 960226995Smarius bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 961226995Smarius 962215018Syongari#define CSR_SETBIT_1(sc, offset, val) \ 963159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 964159962Swpaul 965215018Syongari#define CSR_CLRBIT_1(sc, offset, val) \ 966159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 967159962Swpaul 968215018Syongari#define CSR_SETBIT_2(sc, offset, val) \ 969159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 970159962Swpaul 971215018Syongari#define CSR_CLRBIT_2(sc, offset, val) \ 972159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 973159962Swpaul 974215018Syongari#define CSR_SETBIT_4(sc, offset, val) \ 975159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 976159962Swpaul 977215018Syongari#define CSR_CLRBIT_4(sc, offset, val) \ 978159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 979159962Swpaul 980215018Syongari#define RL_TIMEOUT 1000 981215018Syongari#define RL_PHY_TIMEOUT 2000 98240516Swpaul 98340516Swpaul/* 98440516Swpaul * General constants that are fun to know. 98540516Swpaul * 98640516Swpaul * RealTek PCI vendor ID 98740516Swpaul */ 98840516Swpaul#define RT_VENDORID 0x10EC 98940516Swpaul 99040516Swpaul/* 99140516Swpaul * RealTek chip device IDs. 99240516Swpaul */ 993215018Syongari#define RT_DEVICEID_8139D 0x8039 99440516Swpaul#define RT_DEVICEID_8129 0x8129 995215018Syongari#define RT_DEVICEID_8101E 0x8136 99667771Swpaul#define RT_DEVICEID_8138 0x8138 99740516Swpaul#define RT_DEVICEID_8139 0x8139 998215018Syongari#define RT_DEVICEID_8169SC 0x8167 999215018Syongari#define RT_DEVICEID_8168 0x8168 1000215018Syongari#define RT_DEVICEID_8169 0x8169 1001215018Syongari#define RT_DEVICEID_8100 0x8100 100240516Swpaul 1003215018Syongari#define RT_REVID_8139CPLUS 0x20 1004117388Swpaul 100540516Swpaul/* 100644238Swpaul * Accton PCI vendor ID 100744238Swpaul */ 1008215018Syongari#define ACCTON_VENDORID 0x1113 100944238Swpaul 101044238Swpaul/* 101141243Swpaul * Accton MPX 5030/5038 device ID. 101241243Swpaul */ 1013215018Syongari#define ACCTON_DEVICEID_5030 0x1211 101441243Swpaul 101541243Swpaul/* 101694400Swpaul * Nortel PCI vendor ID 101794400Swpaul */ 1018215018Syongari#define NORTEL_VENDORID 0x126C 101994400Swpaul 102094400Swpaul/* 102144238Swpaul * Delta Electronics Vendor ID. 102244238Swpaul */ 1023215018Syongari#define DELTA_VENDORID 0x1500 102444238Swpaul 102544238Swpaul/* 102644238Swpaul * Delta device IDs. 102744238Swpaul */ 1028215018Syongari#define DELTA_DEVICEID_8139 0x1360 102944238Swpaul 103044238Swpaul/* 103144238Swpaul * Addtron vendor ID. 103244238Swpaul */ 1033215018Syongari#define ADDTRON_VENDORID 0x4033 103444238Swpaul 103544238Swpaul/* 103644238Swpaul * Addtron device IDs. 103744238Swpaul */ 1038215018Syongari#define ADDTRON_DEVICEID_8139 0x1360 103944238Swpaul 104044238Swpaul/* 104172813Swpaul * D-Link vendor ID. 104272813Swpaul */ 1043215018Syongari#define DLINK_VENDORID 0x1186 104472813Swpaul 104572813Swpaul/* 104672813Swpaul * D-Link DFE-530TX+ device ID 104772813Swpaul */ 1048215018Syongari#define DLINK_DEVICEID_530TXPLUS 0x1300 104972813Swpaul 105072813Swpaul/* 1051148722Stobez * D-Link DFE-5280T device ID 1052148722Stobez */ 1053215018Syongari#define DLINK_DEVICEID_528T 0x4300 1054224506Syongari#define DLINK_DEVICEID_530T_REVC 0x4302 1055148722Stobez 1056148722Stobez/* 105796112Sjhb * D-Link DFE-690TXD device ID 105896112Sjhb */ 1059215018Syongari#define DLINK_DEVICEID_690TXD 0x1340 106096112Sjhb 106196112Sjhb/* 1062103020Siwasaki * Corega K.K vendor ID 1063103020Siwasaki */ 1064215018Syongari#define COREGA_VENDORID 0x1259 1065103020Siwasaki 1066103020Siwasaki/* 1067109095Ssanpei * Corega FEther CB-TXD device ID 1068103020Siwasaki */ 1069215018Syongari#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1070103020Siwasaki 1071103020Siwasaki/* 1072109095Ssanpei * Corega FEtherII CB-TXD device ID 1073109095Ssanpei */ 1074215018Syongari#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1075109095Ssanpei 1076111381Sdan/* 1077134433Ssanpei * Corega CG-LAPCIGT device ID 1078134433Ssanpei */ 1079215018Syongari#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1080134433Ssanpei 1081134433Ssanpei/* 1082151341Sjhb * Linksys vendor ID 1083151341Sjhb */ 1084215018Syongari#define LINKSYS_VENDORID 0x1737 1085151341Sjhb 1086151341Sjhb/* 1087151341Sjhb * Linksys EG1032 device ID 1088151341Sjhb */ 1089215018Syongari#define LINKSYS_DEVICEID_EG1032 0x1032 1090151341Sjhb 1091151341Sjhb/* 1092151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1093151341Sjhb */ 1094215018Syongari#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1095151341Sjhb 1096151341Sjhb/* 1097111381Sdan * Peppercon vendor ID 1098111381Sdan */ 1099215018Syongari#define PEPPERCON_VENDORID 0x1743 1100109095Ssanpei 1101111381Sdan/* 1102111381Sdan * Peppercon ROL-F device ID 1103111381Sdan */ 1104215018Syongari#define PEPPERCON_DEVICEID_ROLF 0x8139 1105109095Ssanpei 1106109095Ssanpei/* 1107112379Ssanpei * Planex Communications, Inc. vendor ID 1108112379Ssanpei */ 1109215018Syongari#define PLANEX_VENDORID 0x14ea 1110112379Ssanpei 1111112379Ssanpei/* 1112173948Sremko * Planex FNW-3603-TX device ID 1113173948Sremko */ 1114215018Syongari#define PLANEX_DEVICEID_FNW3603TX 0xab06 1115173948Sremko 1116173948Sremko/* 1117112379Ssanpei * Planex FNW-3800-TX device ID 1118112379Ssanpei */ 1119215018Syongari#define PLANEX_DEVICEID_FNW3800TX 0xab07 1120112379Ssanpei 1121112379Ssanpei/* 1122117388Swpaul * LevelOne vendor ID 1123117388Swpaul */ 1124215018Syongari#define LEVEL1_VENDORID 0x018A 1125117388Swpaul 1126117388Swpaul/* 1127117388Swpaul * LevelOne FPC-0106TX devide ID 1128117388Swpaul */ 1129215018Syongari#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1130117388Swpaul 1131117388Swpaul/* 1132117388Swpaul * Compaq vendor ID 1133117388Swpaul */ 1134215018Syongari#define CP_VENDORID 0x021B 1135117388Swpaul 1136117388Swpaul/* 1137117388Swpaul * Edimax vendor ID 1138117388Swpaul */ 1139215018Syongari#define EDIMAX_VENDORID 0x13D1 1140117388Swpaul 1141117388Swpaul/* 1142117388Swpaul * Edimax EP-4103DL cardbus device ID 1143117388Swpaul */ 1144215018Syongari#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1145117388Swpaul 1146160883Swpaul/* US Robotics vendor ID */ 1147160883Swpaul 1148215018Syongari#define USR_VENDORID 0x16EC 1149160883Swpaul 1150160883Swpaul/* US Robotics 997902 device ID */ 1151160883Swpaul 1152215018Syongari#define USR_DEVICEID_997902 0x0116 1153