if_rlreg.h revision 227590
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 227590 2011-11-16 22:05:38Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39215018Syongari#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40215018Syongari#define RL_IDR2 0x0002 41215018Syongari#define RL_IDR3 0x0003 42215018Syongari#define RL_IDR4 0x0004 43215018Syongari#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 45215018Syongari#define RL_MAR0 0x0008 /* Multicast hash table */ 46215018Syongari#define RL_MAR1 0x0009 47215018Syongari#define RL_MAR2 0x000A 48215018Syongari#define RL_MAR3 0x000B 49215018Syongari#define RL_MAR4 0x000C 50215018Syongari#define RL_MAR5 0x000D 51215018Syongari#define RL_MAR6 0x000E 52215018Syongari#define RL_MAR7 0x000F 5340516Swpaul 54215018Syongari#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55215018Syongari#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56215018Syongari#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57215018Syongari#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 59215018Syongari#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60215018Syongari#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61215018Syongari#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62215018Syongari#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 64215018Syongari#define RL_RXADDR 0x0030 /* RX ring start address */ 65215018Syongari#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66215018Syongari#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67215018Syongari#define RL_COMMAND 0x0037 /* command register */ 68215018Syongari#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69215018Syongari#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70215018Syongari#define RL_IMR 0x003C /* interrupt mask register */ 71215018Syongari#define RL_ISR 0x003E /* interrupt status register */ 72215018Syongari#define RL_TXCFG 0x0040 /* transmit config */ 73215018Syongari#define RL_RXCFG 0x0044 /* receive config */ 74215018Syongari#define RL_TIMERCNT 0x0048 /* timer count register */ 75215018Syongari#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76215018Syongari#define RL_EECMD 0x0050 /* EEPROM command register */ 77215018Syongari#define RL_CFG0 0x0051 /* config register #0 */ 78215018Syongari#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 84215018Syongari#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 86215018Syongari#define RL_MII 0x005A /* 8129 chip only */ 87215018Syongari#define RL_HALTCLK 0x005B 88215018Syongari#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89215018Syongari#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 91215018Syongari#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 94215018Syongari#define RL_BMCR 0x0062 /* PHY basic mode control */ 95215018Syongari#define RL_BMSR 0x0064 /* PHY basic mode status */ 96215018Syongari#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97215018Syongari#define RL_LPAR 0x0068 /* PHY link partner ability */ 98215018Syongari#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 100215018Syongari#define RL_DISCCNT 0x006C /* disconnect counter */ 101215018Syongari#define RL_FALSECAR 0x006E /* false carrier counter */ 102215018Syongari#define RL_NWAYTST 0x0070 /* NWAY test register */ 103215018Syongari#define RL_RX_ER 0x0072 /* RX_ER counter */ 104215018Syongari#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111215018Syongari#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112215018Syongari#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113215018Syongari#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114215018Syongari#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115215018Syongari#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116215018Syongari#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117215018Syongari#define RL_CFG2 0x0053 118215018Syongari#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119215018Syongari#define RL_TXSTART 0x00D9 /* 8 bits */ 120215018Syongari#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121215018Syongari#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122215018Syongari#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123215018Syongari#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128215018Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 129215018Syongari#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130215018Syongari#define RL_PHYAR 0x0060 131215018Syongari#define RL_TBICSR 0x0064 132215018Syongari#define RL_TBI_ANAR 0x0068 133215018Syongari#define RL_TBI_LPAR 0x006A 134215018Syongari#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135215018Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136215018Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137215018Syongari#define RL_PMCH 0x006F /* 8 bits */ 138215018Syongari#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139215018Syongari#define RL_INTRMOD 0x00E2 /* 16 bits */ 140117388Swpaul 141117388Swpaul/* 14240516Swpaul * TX config register bits 14340516Swpaul */ 144215018Syongari#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145215018Syongari#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146215018Syongari#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147215018Syongari#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148215018Syongari#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149215018Syongari#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150215018Syongari#define RL_TXCFG_HWREV 0x7CC00000 15140516Swpaul 152215018Syongari#define RL_LOOPTEST_OFF 0x00000000 153215018Syongari#define RL_LOOPTEST_ON 0x00020000 154215018Syongari#define RL_LOOPTEST_ON_CPLUS 0x00060000 155119868Swpaul 156159962Swpaul/* Known revision codes. */ 157117388Swpaul 158215018Syongari#define RL_HWREV_8169 0x00000000 159215018Syongari#define RL_HWREV_8169S 0x00800000 160215018Syongari#define RL_HWREV_8110S 0x04000000 161215018Syongari#define RL_HWREV_8169_8110SB 0x10000000 162215018Syongari#define RL_HWREV_8169_8110SC 0x18000000 163215018Syongari#define RL_HWREV_8401E 0x24000000 164215018Syongari#define RL_HWREV_8102EL 0x24800000 165215018Syongari#define RL_HWREV_8102EL_SPIN1 0x24C00000 166215018Syongari#define RL_HWREV_8168D 0x28000000 167215018Syongari#define RL_HWREV_8168DP 0x28800000 168217498Syongari#define RL_HWREV_8168E 0x2C000000 169215018Syongari#define RL_HWREV_8168E_VL 0x2C800000 170215018Syongari#define RL_HWREV_8168B_SPIN1 0x30000000 171215018Syongari#define RL_HWREV_8100E 0x30800000 172215018Syongari#define RL_HWREV_8101E 0x34000000 173215018Syongari#define RL_HWREV_8102E 0x34800000 174215018Syongari#define RL_HWREV_8103E 0x34C00000 175215018Syongari#define RL_HWREV_8168B_SPIN2 0x38000000 176215018Syongari#define RL_HWREV_8168B_SPIN3 0x38400000 177215018Syongari#define RL_HWREV_8168C 0x3C000000 178215018Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 179215018Syongari#define RL_HWREV_8168CP 0x3C800000 180215018Syongari#define RL_HWREV_8105E 0x40800000 181215018Syongari#define RL_HWREV_8402 0x44000000 182215018Syongari#define RL_HWREV_8411 0x48800000 183215018Syongari#define RL_HWREV_8139 0x60000000 184215018Syongari#define RL_HWREV_8139A 0x70000000 185215018Syongari#define RL_HWREV_8139AG 0x70800000 186215018Syongari#define RL_HWREV_8139B 0x78000000 187215018Syongari#define RL_HWREV_8130 0x7C000000 188215018Syongari#define RL_HWREV_8139C 0x74000000 189215018Syongari#define RL_HWREV_8139D 0x74400000 190215018Syongari#define RL_HWREV_8139CPLUS 0x74800000 191159962Swpaul#define RL_HWREV_8101 0x74C00000 192215018Syongari#define RL_HWREV_8100 0x78800000 193215018Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 194215018Syongari#define RL_HWREV_8169_8110SCE 0x98000000 195215018Syongari 196215018Syongari#define RL_TXDMA_16BYTES 0x00000000 197215018Syongari#define RL_TXDMA_32BYTES 0x00000100 198215018Syongari#define RL_TXDMA_64BYTES 0x00000200 199215018Syongari#define RL_TXDMA_128BYTES 0x00000300 20045633Swpaul#define RL_TXDMA_256BYTES 0x00000400 20140516Swpaul#define RL_TXDMA_512BYTES 0x00000500 20240516Swpaul#define RL_TXDMA_1024BYTES 0x00000600 20340516Swpaul#define RL_TXDMA_2048BYTES 0x00000700 204215018Syongari 205215018Syongari/* 206215018Syongari * Transmit descriptor status register bits. 207215018Syongari */ 208215018Syongari#define RL_TXSTAT_LENMASK 0x00001FFF 209215018Syongari#define RL_TXSTAT_OWN 0x00002000 210215018Syongari#define RL_TXSTAT_TX_UNDERRUN 0x00004000 211215018Syongari#define RL_TXSTAT_TX_OK 0x00008000 212215018Syongari#define RL_TXSTAT_EARLY_THRESH 0x003F0000 213215018Syongari#define RL_TXSTAT_COLLCNT 0x0F000000 21440516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 21540516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 21640516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 21740516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 218215018Syongari 219215018Syongari/* 220215018Syongari * Interrupt status register bits. 221215018Syongari */ 222215018Syongari#define RL_ISR_RX_OK 0x0001 223215018Syongari#define RL_ISR_RX_ERR 0x0002 224215018Syongari#define RL_ISR_TX_OK 0x0004 225215018Syongari#define RL_ISR_TX_ERR 0x0008 226215018Syongari#define RL_ISR_RX_OVERRUN 0x0010 227215018Syongari#define RL_ISR_PKT_UNDERRUN 0x0020 228215018Syongari#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 229215018Syongari#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 230215018Syongari#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 231215018Syongari#define RL_ISR_SWI 0x0100 /* C+ only */ 23240516Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 233215018Syongari#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 23440516Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 23540516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 23640516Swpaul 23740516Swpaul#define RL_INTRS \ 238159962Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 239215018Syongari RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 240119868Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 241117388Swpaul 242117388Swpaul#ifdef RE_TX_MODERATION 243159962Swpaul#define RL_INTRS_CPLUS \ 244215018Syongari (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 245159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 246159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 247159962Swpaul#else 248159962Swpaul#define RL_INTRS_CPLUS \ 249117388Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 25040516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 25140516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 25240516Swpaul#endif 253215018Syongari 254215018Syongari/* 255215018Syongari * Media status register. (8139 only) 256215018Syongari */ 257215018Syongari#define RL_MEDIASTAT_RXPAUSE 0x01 258215018Syongari#define RL_MEDIASTAT_TXPAUSE 0x02 25940516Swpaul#define RL_MEDIASTAT_LINK 0x04 26040516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 26140516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 26240516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 263215018Syongari 264215018Syongari/* 265215018Syongari * Receive config register. 266215018Syongari */ 267215018Syongari#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 268215018Syongari#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 269215018Syongari#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 270215018Syongari#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 271215018Syongari#define RL_RXCFG_RX_RUNT 0x00000010 272215018Syongari#define RL_RXCFG_RX_ERRPKT 0x00000020 273215018Syongari#define RL_RXCFG_WRAP 0x00000080 27440516Swpaul#define RL_RXCFG_MAXDMA 0x00000700 275215018Syongari#define RL_RXCFG_BUFSZ 0x00001800 276215018Syongari#define RL_RXCFG_FIFOTHRESH 0x0000E000 277215018Syongari#define RL_RXCFG_EARLYTHRESH 0x07000000 278215018Syongari 279215018Syongari#define RL_RXDMA_16BYTES 0x00000000 280215018Syongari#define RL_RXDMA_32BYTES 0x00000100 281215018Syongari#define RL_RXDMA_64BYTES 0x00000200 282215018Syongari#define RL_RXDMA_128BYTES 0x00000300 28345633Swpaul#define RL_RXDMA_256BYTES 0x00000400 284215018Syongari#define RL_RXDMA_512BYTES 0x00000500 285215018Syongari#define RL_RXDMA_1024BYTES 0x00000600 286215018Syongari#define RL_RXDMA_UNLIMITED 0x00000700 287215018Syongari 28840516Swpaul#define RL_RXBUF_8 0x00000000 289215018Syongari#define RL_RXBUF_16 0x00000800 290215018Syongari#define RL_RXBUF_32 0x00001000 291215018Syongari#define RL_RXBUF_64 0x00001800 292215018Syongari 293215018Syongari#define RL_RXFIFO_16BYTES 0x00000000 294215018Syongari#define RL_RXFIFO_32BYTES 0x00002000 295215018Syongari#define RL_RXFIFO_64BYTES 0x00004000 296215018Syongari#define RL_RXFIFO_128BYTES 0x00006000 29745633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 29840516Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 29940516Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 30040516Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 30140516Swpaul 302215018Syongari/* 303215018Syongari * Bits in RX status header (included with RX'ed packet 304215018Syongari * in ring buffer). 305215018Syongari */ 306215018Syongari#define RL_RXSTAT_RXOK 0x00000001 307215018Syongari#define RL_RXSTAT_ALIGNERR 0x00000002 308215018Syongari#define RL_RXSTAT_CRCERR 0x00000004 309215018Syongari#define RL_RXSTAT_GIANT 0x00000008 310215018Syongari#define RL_RXSTAT_RUNT 0x00000010 311215018Syongari#define RL_RXSTAT_BADSYM 0x00000020 31240516Swpaul#define RL_RXSTAT_BROAD 0x00002000 313215018Syongari#define RL_RXSTAT_INDIV 0x00004000 31440516Swpaul#define RL_RXSTAT_MULTI 0x00008000 31540516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 31640516Swpaul 317215018Syongari#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 318215018Syongari/* 319215018Syongari * Command register. 320215018Syongari */ 321215018Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 32240516Swpaul#define RL_CMD_TX_ENB 0x0004 32340516Swpaul#define RL_CMD_RX_ENB 0x0008 324184515Simp#define RL_CMD_RESET 0x0010 325184515Simp#define RL_CMD_STOPREQ 0x0080 326184515Simp 327215018Syongari/* 328215018Syongari * Twister register values. These are completely undocumented and derived 329215018Syongari * from public sources. 330215018Syongari */ 331215018Syongari#define RL_CSCFG_LINK_OK 0x0400 332215018Syongari#define RL_CSCFG_CHANGE 0x0800 333215018Syongari#define RL_CSCFG_STATUS 0xf000 334215018Syongari#define RL_CSCFG_ROW3 0x7000 335184515Simp#define RL_CSCFG_ROW2 0x3000 336215018Syongari#define RL_CSCFG_ROW1 0x1000 337215018Syongari#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 338184515Simp#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 339215018Syongari 340215018Syongari#define RL_NWAYTST_RESET 0 341215018Syongari#define RL_NWAYTST_CBL_TEST 0x20 342215018Syongari 343215018Syongari#define RL_PARA78 0x78 344184515Simp#define RL_PARA78_DEF 0x78fa8388 34540516Swpaul#define RL_PARA7C 0x7C 34640516Swpaul#define RL_PARA7C_DEF 0xcb38de43 347215018Syongari#define RL_PARA7C_RETUNE 0xfb38de03 348215018Syongari/* 349215018Syongari * EEPROM control register 350215018Syongari */ 351215018Syongari#define RL_EE_DATAOUT 0x01 /* Data out */ 35240516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 353215018Syongari#define RL_EE_CLK 0x04 /* clock */ 354215018Syongari#define RL_EE_SEL 0x08 /* chip select */ 355215018Syongari#define RL_EE_MODE (0x40|0x80) 356215018Syongari 35740516Swpaul#define RL_EEMODE_OFF 0x00 35840516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 359215018Syongari#define RL_EEMODE_PROGRAM 0x80 360215018Syongari#define RL_EEMODE_WRITECFG (0x80|0x40) 361159962Swpaul 362215018Syongari/* 9346 EEPROM commands */ 363215018Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 364215018Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 365215018Syongari 366215018Syongari#define RL_9346_WRITE 0x5 367215018Syongari#define RL_9346_READ 0x6 368215018Syongari#define RL_9346_ERASE 0x7 369159962Swpaul#define RL_9346_EWEN 0x4 370215018Syongari#define RL_9346_EWEN_ADDR 0x30 371215018Syongari#define RL_9456_EWDS 0x4 372215018Syongari#define RL_9346_EWDS_ADDR 0x00 373215018Syongari 37440516Swpaul#define RL_EECMD_WRITE 0x140 375215018Syongari#define RL_EECMD_READ_6BIT 0x180 376215018Syongari#define RL_EECMD_READ_8BIT 0x600 377215018Syongari#define RL_EECMD_ERASE 0x1c0 37840516Swpaul 379215018Syongari#define RL_EE_ID 0x00 38040516Swpaul#define RL_EE_PCI_VID 0x01 38140516Swpaul#define RL_EE_PCI_DID 0x02 38240516Swpaul/* Location of station address inside EEPROM */ 38340516Swpaul#define RL_EE_EADDR 0x07 384215018Syongari 385215018Syongari/* 386215018Syongari * MII register (8129 only) 387215018Syongari */ 38840516Swpaul#define RL_MII_CLK 0x01 38940516Swpaul#define RL_MII_DATAIN 0x02 39040516Swpaul#define RL_MII_DATAOUT 0x04 39140516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 392215018Syongari 393215018Syongari/* 394215018Syongari * Config 0 register 395215018Syongari */ 396215018Syongari#define RL_CFG0_ROM0 0x01 397215018Syongari#define RL_CFG0_ROM1 0x02 398215018Syongari#define RL_CFG0_ROM2 0x04 399215018Syongari#define RL_CFG0_PL0 0x08 40040516Swpaul#define RL_CFG0_PL1 0x10 40140516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 40240516Swpaul#define RL_CFG0_PCS 0x40 40340516Swpaul#define RL_CFG0_SCR 0x80 404215018Syongari 405215019Syongari/* 406215018Syongari * Config 1 register 407215018Syongari */ 408215018Syongari#define RL_CFG1_PWRDWN 0x01 409215018Syongari#define RL_CFG1_PME 0x01 410215018Syongari#define RL_CFG1_SLEEP 0x02 411176754Syongari#define RL_CFG1_VPDEN 0x02 412215018Syongari#define RL_CFG1_IOMAP 0x04 413215018Syongari#define RL_CFG1_MEMMAP 0x08 414215018Syongari#define RL_CFG1_RSVD 0x10 415215018Syongari#define RL_CFG1_LWACT 0x10 41640516Swpaul#define RL_CFG1_DRVLOAD 0x20 41740516Swpaul#define RL_CFG1_LED0 0x40 418176754Syongari#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 419176754Syongari#define RL_CFG1_LED1 0x80 420176754Syongari 421176754Syongari/* 422176754Syongari * Config 2 register 423176754Syongari */ 424177522Syongari#define RL_CFG2_PCI33MHZ 0x00 425176754Syongari#define RL_CFG2_PCI66MHZ 0x01 426176754Syongari#define RL_CFG2_PCI64BIT 0x08 427176754Syongari#define RL_CFG2_AUXPWR 0x10 428176754Syongari#define RL_CFG2_MSI 0x20 429176754Syongari 430176754Syongari/* 431176754Syongari * Config 3 register 432176754Syongari */ 433176754Syongari#define RL_CFG3_GRANTSEL 0x80 434176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 435176754Syongari#define RL_CFG3_WOL_LINK 0x10 436176754Syongari#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 437176754Syongari#define RL_CFG3_FAST_B2B 0x01 438176754Syongari 439176754Syongari/* 440176754Syongari * Config 4 register 441176754Syongari */ 442176754Syongari#define RL_CFG4_LWPTN 0x04 443176754Syongari#define RL_CFG4_LWPME 0x10 444176754Syongari#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 445176754Syongari 446176754Syongari/* 447176754Syongari * Config 5 register 448176754Syongari */ 449176754Syongari#define RL_CFG5_WOL_BCAST 0x40 450117388Swpaul#define RL_CFG5_WOL_MCAST 0x20 451117388Swpaul#define RL_CFG5_WOL_UCAST 0x10 452117388Swpaul#define RL_CFG5_WOL_LANWAKE 0x02 453117388Swpaul#define RL_CFG5_PME_STS 0x01 454117388Swpaul 455215018Syongari/* 456117388Swpaul * 8139C+ register definitions 457117388Swpaul */ 458117388Swpaul 459215018Syongari/* RL_DUMPSTATS_LO register */ 460215018Syongari 461215018Syongari#define RL_DUMPSTATS_START 0x00000008 462117388Swpaul 463120043Swpaul/* Transmit start register */ 464120043Swpaul 465120043Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 466215018Syongari#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 467215018Syongari#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 468215018Syongari 469120043Swpaul/* 470215018Syongari * Config 2 register, 8139C+/8169/8169S/8110S only 471215018Syongari */ 472215019Syongari#define RL_CFG2_BUSFREQ 0x07 473215018Syongari#define RL_CFG2_BUSWIDTH 0x08 474215018Syongari#define RL_CFG2_AUXPWRSTS 0x10 475120043Swpaul 476117388Swpaul#define RL_BUSFREQ_33MHZ 0x00 477117388Swpaul#define RL_BUSFREQ_66MHZ 0x01 478215018Syongari 479215018Syongari#define RL_BUSWIDTH_32BITS 0x00 480215018Syongari#define RL_BUSWIDTH_64BITS 0x08 481215018Syongari 482215018Syongari/* C+ mode command register */ 483215018Syongari 484180176Syongari#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 485180176Syongari#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 486180176Syongari#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 487180176Syongari#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 488180176Syongari#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 489180176Syongari#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 490180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 491180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 492180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 493117388Swpaul#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 494117388Swpaul#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 495117388Swpaul#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 496215019Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 497117388Swpaul#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 498117388Swpaul#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 499117388Swpaul 500117388Swpaul/* C+ early transmit threshold */ 501117388Swpaul 502215018Syongari#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 503215018Syongari 504215018Syongari/* Timer interrupt register */ 505117388Swpaul#define RL_TIMERINT_8169_VAL 0x00001FFF 506117388Swpaul#define RL_TIMER_MIN 0 507117388Swpaul#define RL_TIMER_MAX 65 /* 65.528us */ 508117388Swpaul#define RL_TIMER_DEFAULT RL_TIMER_MAX 509215018Syongari#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 510215018Syongari#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 511215018Syongari 512215018Syongari/* 513215018Syongari * Gigabit PHY access register (8169 only) 514215018Syongari */ 515215018Syongari 516215018Syongari#define RL_PHYAR_PHYDATA 0x0000FFFF 517117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 518117388Swpaul#define RL_PHYAR_BUSY 0x80000000 51940516Swpaul 52040516Swpaul/* 52140516Swpaul * Gigabit media status (8169 only) 52240516Swpaul */ 52340516Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 52440516Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 52540516Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 52640516Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 52740516Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 52840516Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 52940516Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 53040516Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 53140516Swpaul 53240516Swpaul/* 533215018Syongari * The RealTek doesn't use a fragment-based descriptor mechanism. 534215018Syongari * Instead, there are only four register sets, each or which represents 535215018Syongari * one 'descriptor.' Basically, each TX descriptor is just a contiguous 536215018Syongari * packet buffer (32-bit aligned!) and we place the buffer addresses in 537184240Syongari * the registers so the chip knows where they are. 538184240Syongari * 539184240Syongari * We can sort of kludge together the same kind of buffer management 540184240Syongari * used in previous drivers, but we have to do buffer copies almost all 541215019Syongari * the time, so it doesn't really buy us much. 542215018Syongari * 543215018Syongari * For reception, there's just one large buffer where the chip stores 544215018Syongari * all received packets. 545215018Syongari */ 546215018Syongari 54740516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 548215018Syongari#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 549215018Syongari#define RL_TX_LIST_CNT 4 55040516Swpaul#define RL_MIN_FRAMELEN 60 551215018Syongari#define RL_TX_8139_BUF_ALIGN 4 55248028Swpaul#define RL_RX_8139_BUF_ALIGN 8 553177771Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 554177771Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 555177771Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 556177771Syongari#define RL_TXTHRESH(x) ((x) << 11) 557177771Syongari#define RL_TX_THRESH_INIT 96 558177771Syongari#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 55940516Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 560131605Sbms#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 561131605Sbms 562131605Sbms#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 56340516Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 56445633Swpaul 56581713Swpaul#define RL_ETHER_ALIGN 2 566184240Syongari 567184240Syongari/* 568184240Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 569184240Syongari */ 570131605Sbms#define RL_IP4CSUMTX_MINLEN 28 571131605Sbms#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 57240516Swpaul 57340516Swpaulstruct rl_chain_data { 574215018Syongari uint16_t cur_rx; 575215018Syongari uint8_t *rl_rx_buf; 576215018Syongari uint8_t *rl_rx_buf_ptr; 577215018Syongari 578215018Syongari struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 579215018Syongari bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 580215018Syongari bus_dma_tag_t rl_tx_tag; 581215018Syongari bus_dma_tag_t rl_rx_tag; 582215018Syongari bus_dmamap_t rl_rx_dmamap; 58345633Swpaul bus_addr_t rl_rx_buf_paddr; 58440516Swpaul uint8_t last_tx; 585131605Sbms uint8_t cur_tx; 586131605Sbms}; 587117388Swpaul 58840516Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 58940516Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 59040516Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 591117388Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 592131605Sbms#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 593117388Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 594117388Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 595117388Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 596117388Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 59740516Swpaul 598131605Sbmsstruct rl_type { 599131605Sbms uint16_t rl_vid; 600131605Sbms uint16_t rl_did; 601131605Sbms int rl_basetype; 602131605Sbms const char *rl_name; 603131605Sbms}; 60440516Swpaul 60540516Swpaulstruct rl_hwrev { 60640516Swpaul uint32_t rl_rev; 60740516Swpaul int rl_type; 60840516Swpaul const char *rl_desc; 609215018Syongari int rl_max_mtu; 610215018Syongari}; 611215018Syongari 612215018Syongari#define RL_8129 1 61340516Swpaul#define RL_8139 2 614215018Syongari#define RL_8139CPLUS 3 615215018Syongari#define RL_8169 4 616215018Syongari 617215018Syongari#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 61840516Swpaul (x)->rl_type == RL_8169) 619215018Syongari 620117388Swpaul/* 621117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 622117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 623117388Swpaul * must be allocated in contiguous blocks that are aligned on a 624117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 625117388Swpaul */ 626117388Swpaul 627117388Swpaul/* 628117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 629117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 630117388Swpaul * the checksum offload bits are disabled. The structure layout is 631117388Swpaul * the same for RX and TX descriptors 632117388Swpaul */ 633117388Swpaul 634117388Swpaulstruct rl_desc { 635117388Swpaul uint32_t rl_cmdstat; 636117388Swpaul uint32_t rl_vlanctl; 637131605Sbms uint32_t rl_bufaddr_lo; 638131605Sbms uint32_t rl_bufaddr_hi; 639131605Sbms}; 640131605Sbms 641117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 642117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 643215018Syongari#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 644215018Syongari#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 645215018Syongari#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 646215018Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 647215018Syongari#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 648215018Syongari#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 649215018Syongari#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 650215018Syongari#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 651215018Syongari#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 652215018Syongari 653215018Syongari#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 654117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 655215018Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 656215018Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 657180176Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 658180176Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 659215019Syongari#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 660215019Syongari#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 661217246Syongari 662217246Syongari/* 663117388Swpaul * Error bits are valid only on the last descriptor of a frame 664117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 665117388Swpaul */ 666117388Swpaul 667117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 668117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 669215018Syongari#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 670215018Syongari#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 671215018Syongari#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 672215018Syongari#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 673215018Syongari#define RL_TDESC_STAT_OWN 0x80000000 674215018Syongari 675215018Syongari/* 676117388Swpaul * RX descriptor cmd/vlan definitions 677117388Swpaul */ 678117388Swpaul 679117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 680117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 681215018Syongari#define RL_RDESC_CMD_BUFLEN 0x00001FFF 682215018Syongari 683215018Syongari#define RL_RDESC_STAT_OWN 0x80000000 684117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 685215018Syongari#define RL_RDESC_STAT_SOF 0x20000000 686215018Syongari#define RL_RDESC_STAT_EOF 0x10000000 687215018Syongari#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 688215018Syongari#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 689215018Syongari#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 690215018Syongari#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 691215018Syongari#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 692215018Syongari#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 693215018Syongari#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 694215018Syongari#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 695215018Syongari#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 696215018Syongari#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 697215018Syongari#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 698215018Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 699215018Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 700180176Syongari#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 701180176Syongari#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 702215018Syongari#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 703215018Syongari#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 704215018Syongari#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 705215018Syongari#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 706215018Syongari RL_RDESC_STAT_CRCERR) 707215018Syongari 708135896Sjmg#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 709117388Swpaul (rl_vlandata valid)*/ 710215018Syongari#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 711117388Swpaul/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 712215018Syongari#define RL_RDESC_IPV6 0x80000000 713180176Syongari#define RL_RDESC_IPV4 0x40000000 714180176Syongari 715180176Syongari#define RL_PROTOID_NONIP 0x00000000 716117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 717215018Syongari#define RL_PROTOID_UDPIP 0x00020000 718215018Syongari#define RL_PROTOID_IP 0x00030000 719215018Syongari#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 720215018Syongari RL_PROTOID_TCPIP) 721215018Syongari#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 722117388Swpaul RL_PROTOID_UDPIP) 723215018Syongari 724117388Swpaul/* 725117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 726117388Swpaul */ 727117388Swpaulstruct rl_stats { 728117388Swpaul uint64_t rl_tx_pkts; 729117388Swpaul uint64_t rl_rx_pkts; 730214844Syongari uint64_t rl_tx_errs; 731214844Syongari uint32_t rl_rx_errs; 732214844Syongari uint16_t rl_missed_pkts; 733214844Syongari uint16_t rl_rx_framealign_errs; 734131605Sbms uint32_t rl_tx_onecoll; 735131605Sbms uint32_t rl_tx_multicolls; 736131605Sbms uint64_t rl_rx_ucasts; 737131605Sbms uint64_t rl_rx_bcasts; 738214844Syongari uint32_t rl_rx_mcasts; 739214844Syongari uint16_t rl_tx_aborts; 740131605Sbms uint16_t rl_rx_underruns; 741131605Sbms}; 742131605Sbms 743117388Swpaul/* 744117388Swpaul * Rx/Tx descriptor parameters (8139C+ and 8169 only) 745135467Sjmg * 746135467Sjmg * 8139C+ 747135467Sjmg * Number of descriptors supported : up to 64 748175337Syongari * Descriptor alignment : 256 bytes 749175337Syongari * Tx buffer : At least 4 bytes in length. 750175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 751175337Syongari * 752175337Syongari * 8169 753215019Syongari * Number of descriptors supported : up to 1024 754175337Syongari * Descriptor alignment : 256 bytes 755175337Syongari * Tx buffer : At least 4 bytes in length. 756175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 757175337Syongari */ 758175337Syongari#ifndef __NO_STRICT_ALIGNMENT 759135467Sjmg#define RE_FIXUP_RX 1 760164460Syongari#endif 761215018Syongari 762135896Sjmg#define RL_8169_TX_DESC_CNT 256 763135896Sjmg#define RL_8169_RX_DESC_CNT 256 764215018Syongari#define RL_8139_TX_DESC_CNT 64 765215018Syongari#define RL_8139_RX_DESC_CNT 64 766215018Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 767215018Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 768215018Syongari#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 769215018Syongari#define RL_NTXSEGS 32 770175337Syongari 771159962Swpaul#define RL_RING_ALIGN 256 772215018Syongari#define RL_DUMP_ALIGN 64 773215018Syongari#define RL_IFQ_MAXLEN 512 774215018Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 775215018Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 776215018Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 777215018Syongari#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 778215018Syongari#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 779215018Syongari#define RL_PKTSZ(x) ((x)/* >> 3*/) 780215018Syongari#ifdef RE_FIXUP_RX 781135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 782215018Syongari#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 783215018Syongari#else 784135896Sjmg#define RE_ETHER_ALIGN 0 785215018Syongari#define RE_RX_DESC_BUFLEN MCLBYTES 786215018Syongari#endif 787135896Sjmg 788117388Swpaul#define RL_MSI_MESSAGES 1 789188474Syongari 790171560Syongari#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 791215018Syongari#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 792215018Syongari 793118712Swpaul/* 794181270Syongari * The number of bits reserved for MSS in RealTek controllers is 795181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 796181270Syongari * as upper stack should not generate TCP segments with MSS greater 797181270Syongari * than the limit. 798181270Syongari */ 799181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 800181270Syongari 801181270Syongari/* see comment in dev/re/if_re.c */ 802135896Sjmg#define RL_JUMBO_FRAMELEN 7440 803215018Syongari#define RL_JUMBO_MTU \ 804215018Syongari (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 805176756Syongari#define RL_JUMBO_MTU_6K \ 806176756Syongari ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 807119868Swpaul#define RL_JUMBO_MTU_9K \ 808175337Syongari ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 809175337Syongari#define RL_MTU \ 810175337Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 811175337Syongari 812117388Swpaulstruct rl_txdesc { 813175337Syongari struct mbuf *tx_m; 814175337Syongari bus_dmamap_t tx_dmamap; 815175337Syongari}; 816175337Syongari 817117388Swpaulstruct rl_rxdesc { 818117388Swpaul struct mbuf *rx_m; 819117388Swpaul bus_dmamap_t rx_dmamap; 820175337Syongari bus_size_t rx_size; 821175337Syongari}; 822175337Syongari 823175337Syongaristruct rl_list_data { 824117388Swpaul struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 825117388Swpaul struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 826117388Swpaul struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 827117388Swpaul int rl_tx_desc_cnt; 828175337Syongari int rl_rx_desc_cnt; 829175337Syongari int rl_tx_prodidx; 830175337Syongari int rl_rx_prodidx; 831117388Swpaul int rl_tx_considx; 832117388Swpaul int rl_tx_free; 833117388Swpaul bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 834118712Swpaul bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 835117388Swpaul bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 836117388Swpaul bus_dmamap_t rl_rx_sparemap; 837117388Swpaul bus_dmamap_t rl_jrx_sparemap; 838118712Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 839117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 840117388Swpaul struct rl_stats *rl_stats; 841117388Swpaul bus_addr_t rl_stats_addr; 842118712Swpaul bus_dma_tag_t rl_rx_list_tag; 843117388Swpaul bus_dmamap_t rl_rx_list_map; 844117388Swpaul struct rl_desc *rl_rx_list; 845184515Simp bus_addr_t rl_rx_list_addr; 846184515Simp bus_dma_tag_t rl_tx_list_tag; 84740516Swpaul bus_dmamap_t rl_tx_list_map; 848147256Sbrooks struct rl_desc *rl_tx_list; 84941569Swpaul bus_addr_t rl_tx_list_addr; 85041569Swpaul}; 851159962Swpaul 85250703Swpaulenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 853180169Syongari 854180169Syongaristruct rl_softc { 855171560Syongari struct ifnet *rl_ifp; /* interface info */ 856171560Syongari bus_space_handle_t rl_bhandle; /* bus space handle */ 85750703Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 85881713Swpaul device_t rl_dev; 859131605Sbms struct resource *rl_res; 86067931Swpaul int rl_res_id; 861159962Swpaul int rl_res_type; 862131605Sbms struct resource *rl_res_pba; 86352426Swpaul struct resource *rl_irq[RL_MSI_MESSAGES]; 86440516Swpaul void *rl_intrhand[RL_MSI_MESSAGES]; 865117388Swpaul device_t rl_miibus; 866150720Sjhb bus_dma_tag_t rl_parent_tag; 867164811Sru uint8_t rl_type; 86867087Swpaul const struct rl_hwrev *rl_hwrev; 869119868Swpaul int rl_eecmd_read; 870119868Swpaul int rl_eewidth; 871131605Sbms int rl_txthresh; 872131605Sbms struct rl_chain_data rl_cdata; 873119868Swpaul struct rl_list_data rl_ldata; 874168828Syongari struct callout rl_stat_callout; 875184559Simp int rl_watchdog_timer; 876184515Simp struct mtx rl_mtx; 877184515Simp struct mbuf *rl_head; 878184515Simp struct mbuf *rl_tail; 87986822Siwasaki uint32_t rl_rxlenmask; 88094883Sluigi int rl_testmode; 88194883Sluigi int rl_if_flags; 88294883Sluigi int rl_twister_enable; 883159962Swpaul enum rl_twist rl_twister; 884159962Swpaul int rl_twist_row; 885159962Swpaul int rl_twist_col; 886159962Swpaul int suspended; /* 0 = normal 1 = suspended */ 887159962Swpaul#ifdef DEVICE_POLLING 888180171Syongari int rxcycles; 889180171Syongari#endif 890191301Syongari 891206433Syongari struct task rl_inttask; 892180171Syongari 893180171Syongari int rl_txstart; 894180176Syongari int rl_int_rx_act; 895180176Syongari int rl_int_rx_mod; 896180176Syongari uint32_t rl_flags; 897185753Syongari#define RL_FLAG_MSI 0x0001 898185900Syongari#define RL_FLAG_AUTOPAD 0x0002 899187483Sjkim#define RL_FLAG_PHYWAKE_PM 0x0004 900185903Syongari#define RL_FLAG_PHYWAKE 0x0008 901186210Syongari#define RL_FLAG_JUMBOV2 0x0010 902186214Syongari#define RL_FLAG_PAR 0x0020 903180171Syongari#define RL_FLAG_DESCV2 0x0040 90440516Swpaul#define RL_FLAG_MACSTAT 0x0080 90540516Swpaul#define RL_FLAG_FASTETHER 0x0100 90672200Sbmilekic#define RL_FLAG_CMDSTOP 0x0200 90772200Sbmilekic#define RL_FLAG_MACRESET 0x0400 908122689Ssam#define RL_FLAG_MSIX 0x0800 90967087Swpaul#define RL_FLAG_WOLRXENB 0x1000 91040516Swpaul#define RL_FLAG_MACSLEEP 0x2000 91140516Swpaul#define RL_FLAG_PCIE 0x4000 91240516Swpaul#define RL_FLAG_LINK 0x8000 913215018Syongari}; 914119738Stmm 915215018Syongari#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 91641569Swpaul#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 917215018Syongari#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 91841569Swpaul 919215018Syongari/* 92041569Swpaul * register space access macros 92140516Swpaul */ 922215018Syongari#define CSR_WRITE_STREAM_4(sc, reg, val) \ 92341569Swpaul bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 924215018Syongari#define CSR_WRITE_4(sc, reg, val) \ 92541569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 926215018Syongari#define CSR_WRITE_2(sc, reg, val) \ 92741569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 92840516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 929215018Syongari bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 930159962Swpaul 931159962Swpaul#define CSR_READ_4(sc, reg) \ 932215018Syongari bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 933159962Swpaul#define CSR_READ_2(sc, reg) \ 934159962Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 935215018Syongari#define CSR_READ_1(sc, reg) \ 936159962Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 937159962Swpaul 938215018Syongari#define CSR_BARRIER(sc, reg, length, flags) \ 939159962Swpaul bus_space_barrier(sc->rl_btag, sc->rl_bhandle, reg, length, flags) 940159962Swpaul 941215018Syongari#define CSR_SETBIT_1(sc, offset, val) \ 942159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 943159962Swpaul 944215018Syongari#define CSR_CLRBIT_1(sc, offset, val) \ 945159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 946159962Swpaul 947215018Syongari#define CSR_SETBIT_2(sc, offset, val) \ 948215018Syongari CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 94940516Swpaul 95040516Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 95140516Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 95240516Swpaul 95340516Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 95440516Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 95540516Swpaul 95640516Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 95740516Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 95840516Swpaul 95940516Swpaul#define RL_TIMEOUT 1000 960215018Syongari#define RL_PHY_TIMEOUT 2000 96140516Swpaul 962215018Syongari/* 96367771Swpaul * General constants that are fun to know. 96440516Swpaul * 965215018Syongari * RealTek PCI vendor ID 966215018Syongari */ 967215018Syongari#define RT_VENDORID 0x10EC 968215018Syongari 96940516Swpaul/* 970215018Syongari * RealTek chip device IDs. 971117388Swpaul */ 97240516Swpaul#define RT_DEVICEID_8139D 0x8039 97344238Swpaul#define RT_DEVICEID_8129 0x8129 97444238Swpaul#define RT_DEVICEID_8101E 0x8136 975215018Syongari#define RT_DEVICEID_8138 0x8138 97644238Swpaul#define RT_DEVICEID_8139 0x8139 97744238Swpaul#define RT_DEVICEID_8169SC 0x8167 97841243Swpaul#define RT_DEVICEID_8168 0x8168 97941243Swpaul#define RT_DEVICEID_8169 0x8169 980215018Syongari#define RT_DEVICEID_8100 0x8100 98141243Swpaul 98241243Swpaul#define RT_REVID_8139CPLUS 0x20 98394400Swpaul 98494400Swpaul/* 985215018Syongari * Accton PCI vendor ID 98694400Swpaul */ 98794400Swpaul#define ACCTON_VENDORID 0x1113 98844238Swpaul 98944238Swpaul/* 990215018Syongari * Accton MPX 5030/5038 device ID. 99144238Swpaul */ 99244238Swpaul#define ACCTON_DEVICEID_5030 0x1211 99344238Swpaul 99444238Swpaul/* 995215018Syongari * Nortel PCI vendor ID 99644238Swpaul */ 99744238Swpaul#define NORTEL_VENDORID 0x126C 99844238Swpaul 99944238Swpaul/* 1000215018Syongari * Delta Electronics Vendor ID. 100144238Swpaul */ 100244238Swpaul#define DELTA_VENDORID 0x1500 100344238Swpaul 100444238Swpaul/* 1005215018Syongari * Delta device IDs. 100644238Swpaul */ 100744238Swpaul#define DELTA_DEVICEID_8139 0x1360 100872813Swpaul 100972813Swpaul/* 1010215018Syongari * Addtron vendor ID. 101172813Swpaul */ 101272813Swpaul#define ADDTRON_VENDORID 0x4033 101372813Swpaul 101472813Swpaul/* 1015215018Syongari * Addtron device IDs. 101672813Swpaul */ 101772813Swpaul#define ADDTRON_DEVICEID_8139 0x1360 1018148722Stobez 1019148722Stobez/* 1020215018Syongari * D-Link vendor ID. 1021148722Stobez */ 1022148722Stobez#define DLINK_VENDORID 0x1186 102396112Sjhb 102496112Sjhb/* 1025215018Syongari * D-Link DFE-530TX+ device ID 102696112Sjhb */ 102796112Sjhb#define DLINK_DEVICEID_530TXPLUS 0x1300 1028103020Siwasaki 1029103020Siwasaki/* 1030215018Syongari * D-Link DFE-5280T device ID 1031103020Siwasaki */ 1032103020Siwasaki#define DLINK_DEVICEID_528T 0x4300 1033109095Ssanpei#define DLINK_DEVICEID_530T_REVC 0x4302 1034103020Siwasaki 1035215018Syongari/* 1036103020Siwasaki * D-Link DFE-690TXD device ID 1037103020Siwasaki */ 1038109095Ssanpei#define DLINK_DEVICEID_690TXD 0x1340 1039109095Ssanpei 1040215018Syongari/* 1041109095Ssanpei * Corega K.K vendor ID 1042111381Sdan */ 1043134433Ssanpei#define COREGA_VENDORID 0x1259 1044134433Ssanpei 1045215018Syongari/* 1046134433Ssanpei * Corega FEther CB-TXD device ID 1047134433Ssanpei */ 1048151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1049151341Sjhb 1050215018Syongari/* 1051151341Sjhb * Corega FEtherII CB-TXD device ID 1052151341Sjhb */ 1053151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1054151341Sjhb 1055215018Syongari/* 1056151341Sjhb * Corega CG-LAPCIGT device ID 1057151341Sjhb */ 1058151341Sjhb#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1059151341Sjhb 1060215018Syongari/* 1061151341Sjhb * Linksys vendor ID 1062151341Sjhb */ 1063111381Sdan#define LINKSYS_VENDORID 0x1737 1064111381Sdan 1065215018Syongari/* 1066109095Ssanpei * Linksys EG1032 device ID 1067111381Sdan */ 1068111381Sdan#define LINKSYS_DEVICEID_EG1032 0x1032 1069111381Sdan 1070215018Syongari/* 1071109095Ssanpei * Linksys EG1032 rev 3 sub-device ID 1072109095Ssanpei */ 1073112379Ssanpei#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1074112379Ssanpei 1075215018Syongari/* 1076112379Ssanpei * Peppercon vendor ID 1077112379Ssanpei */ 1078173948Sremko#define PEPPERCON_VENDORID 0x1743 1079173948Sremko 1080215018Syongari/* 1081173948Sremko * Peppercon ROL-F device ID 1082173948Sremko */ 1083112379Ssanpei#define PEPPERCON_DEVICEID_ROLF 0x8139 1084112379Ssanpei 1085215018Syongari/* 1086112379Ssanpei * Planex Communications, Inc. vendor ID 1087112379Ssanpei */ 1088117388Swpaul#define PLANEX_VENDORID 0x14ea 1089117388Swpaul 1090215018Syongari/* 1091117388Swpaul * Planex FNW-3603-TX device ID 1092117388Swpaul */ 1093117388Swpaul#define PLANEX_DEVICEID_FNW3603TX 0xab06 1094117388Swpaul 1095215018Syongari/* 1096117388Swpaul * Planex FNW-3800-TX device ID 1097117388Swpaul */ 1098117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 1099117388Swpaul 1100215018Syongari/* 1101117388Swpaul * LevelOne vendor ID 1102117388Swpaul */ 1103117388Swpaul#define LEVEL1_VENDORID 0x018A 1104117388Swpaul 1105215018Syongari/* 1106117388Swpaul * LevelOne FPC-0106TX devide ID 1107117388Swpaul */ 1108117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1109117388Swpaul 1110215018Syongari/* 1111117388Swpaul * Compaq vendor ID 1112160883Swpaul */ 1113160883Swpaul#define CP_VENDORID 0x021B 1114215018Syongari 1115160883Swpaul/* 1116160883Swpaul * Edimax vendor ID 1117160883Swpaul */ 1118215018Syongari#define EDIMAX_VENDORID 0x13D1 1119 1120/* 1121 * Edimax EP-4103DL cardbus device ID 1122 */ 1123#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1124 1125/* US Robotics vendor ID */ 1126 1127#define USR_VENDORID 0x16EC 1128 1129/* US Robotics 997902 device ID */ 1130 1131#define USR_DEVICEID_997902 0x0116 1132