if_rlreg.h revision 217911
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 217911 2011-01-26 21:14:20Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39215018Syongari#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40215018Syongari#define RL_IDR2 0x0002 41215018Syongari#define RL_IDR3 0x0003 42215018Syongari#define RL_IDR4 0x0004 43215018Syongari#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 45215018Syongari#define RL_MAR0 0x0008 /* Multicast hash table */ 46215018Syongari#define RL_MAR1 0x0009 47215018Syongari#define RL_MAR2 0x000A 48215018Syongari#define RL_MAR3 0x000B 49215018Syongari#define RL_MAR4 0x000C 50215018Syongari#define RL_MAR5 0x000D 51215018Syongari#define RL_MAR6 0x000E 52215018Syongari#define RL_MAR7 0x000F 5340516Swpaul 54215018Syongari#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55215018Syongari#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56215018Syongari#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57215018Syongari#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 59215018Syongari#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60215018Syongari#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61215018Syongari#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62215018Syongari#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 64215018Syongari#define RL_RXADDR 0x0030 /* RX ring start address */ 65215018Syongari#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66215018Syongari#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67215018Syongari#define RL_COMMAND 0x0037 /* command register */ 68215018Syongari#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69215018Syongari#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70215018Syongari#define RL_IMR 0x003C /* interrupt mask register */ 71215018Syongari#define RL_ISR 0x003E /* interrupt status register */ 72215018Syongari#define RL_TXCFG 0x0040 /* transmit config */ 73215018Syongari#define RL_RXCFG 0x0044 /* receive config */ 74215018Syongari#define RL_TIMERCNT 0x0048 /* timer count register */ 75215018Syongari#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76215018Syongari#define RL_EECMD 0x0050 /* EEPROM command register */ 77215018Syongari#define RL_CFG0 0x0051 /* config register #0 */ 78215018Syongari#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 84215018Syongari#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 86215018Syongari#define RL_MII 0x005A /* 8129 chip only */ 87215018Syongari#define RL_HALTCLK 0x005B 88215018Syongari#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89215018Syongari#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 91215018Syongari#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 94215018Syongari#define RL_BMCR 0x0062 /* PHY basic mode control */ 95215018Syongari#define RL_BMSR 0x0064 /* PHY basic mode status */ 96215018Syongari#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97215018Syongari#define RL_LPAR 0x0068 /* PHY link partner ability */ 98215018Syongari#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 100215018Syongari#define RL_DISCCNT 0x006C /* disconnect counter */ 101215018Syongari#define RL_FALSECAR 0x006E /* false carrier counter */ 102215018Syongari#define RL_NWAYTST 0x0070 /* NWAY test register */ 103215018Syongari#define RL_RX_ER 0x0072 /* RX_ER counter */ 104215018Syongari#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111215018Syongari#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112215018Syongari#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113215018Syongari#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114215018Syongari#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115215018Syongari#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116215018Syongari#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117215018Syongari#define RL_CFG2 0x0053 118215018Syongari#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119215018Syongari#define RL_TXSTART 0x00D9 /* 8 bits */ 120215018Syongari#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121215018Syongari#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122215018Syongari#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123215018Syongari#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128215018Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 129215018Syongari#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130215018Syongari#define RL_PHYAR 0x0060 131215018Syongari#define RL_TBICSR 0x0064 132215018Syongari#define RL_TBI_ANAR 0x0068 133215018Syongari#define RL_TBI_LPAR 0x006A 134215018Syongari#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135215018Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136215018Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137215018Syongari#define RL_PMCH 0x006F /* 8 bits */ 138215018Syongari#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139215018Syongari#define RL_INTRMOD 0x00E2 /* 16 bits */ 140117388Swpaul 141117388Swpaul/* 14240516Swpaul * TX config register bits 14340516Swpaul */ 144215018Syongari#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145215018Syongari#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146215018Syongari#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147215018Syongari#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148215018Syongari#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149215018Syongari#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150215018Syongari#define RL_TXCFG_HWREV 0x7CC00000 15140516Swpaul 152215018Syongari#define RL_LOOPTEST_OFF 0x00000000 153215018Syongari#define RL_LOOPTEST_ON 0x00020000 154215018Syongari#define RL_LOOPTEST_ON_CPLUS 0x00060000 155119868Swpaul 156159962Swpaul/* Known revision codes. */ 157117388Swpaul 158215018Syongari#define RL_HWREV_8169 0x00000000 159215018Syongari#define RL_HWREV_8169S 0x00800000 160215018Syongari#define RL_HWREV_8110S 0x04000000 161215018Syongari#define RL_HWREV_8169_8110SB 0x10000000 162215018Syongari#define RL_HWREV_8169_8110SC 0x18000000 163215018Syongari#define RL_HWREV_8102EL 0x24800000 164215018Syongari#define RL_HWREV_8102EL_SPIN1 0x24C00000 165215018Syongari#define RL_HWREV_8168D 0x28000000 166215018Syongari#define RL_HWREV_8168DP 0x28800000 167215018Syongari#define RL_HWREV_8168E 0x2C000000 168217498Syongari#define RL_HWREV_8168E_VL 0x2C800000 169217524Syongari#define RL_HWREV_8168B_SPIN1 0x30000000 170215018Syongari#define RL_HWREV_8100E 0x30800000 171215018Syongari#define RL_HWREV_8101E 0x34000000 172215018Syongari#define RL_HWREV_8102E 0x34800000 173215018Syongari#define RL_HWREV_8103E 0x34C00000 174217524Syongari#define RL_HWREV_8168B_SPIN2 0x38000000 175217524Syongari#define RL_HWREV_8168B_SPIN3 0x38400000 176215018Syongari#define RL_HWREV_8168C 0x3C000000 177215018Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 178215018Syongari#define RL_HWREV_8168CP 0x3C800000 179217911Syongari#define RL_HWREV_8105E 0x40800000 180215018Syongari#define RL_HWREV_8139 0x60000000 181215018Syongari#define RL_HWREV_8139A 0x70000000 182215018Syongari#define RL_HWREV_8139AG 0x70800000 183215018Syongari#define RL_HWREV_8139B 0x78000000 184215018Syongari#define RL_HWREV_8130 0x7C000000 185215018Syongari#define RL_HWREV_8139C 0x74000000 186215018Syongari#define RL_HWREV_8139D 0x74400000 187215018Syongari#define RL_HWREV_8139CPLUS 0x74800000 188215018Syongari#define RL_HWREV_8101 0x74C00000 189215018Syongari#define RL_HWREV_8100 0x78800000 190215018Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 191215018Syongari#define RL_HWREV_8169_8110SCE 0x98000000 192159962Swpaul 193215018Syongari#define RL_TXDMA_16BYTES 0x00000000 194215018Syongari#define RL_TXDMA_32BYTES 0x00000100 195215018Syongari#define RL_TXDMA_64BYTES 0x00000200 196215018Syongari#define RL_TXDMA_128BYTES 0x00000300 197215018Syongari#define RL_TXDMA_256BYTES 0x00000400 198215018Syongari#define RL_TXDMA_512BYTES 0x00000500 199215018Syongari#define RL_TXDMA_1024BYTES 0x00000600 200215018Syongari#define RL_TXDMA_2048BYTES 0x00000700 20145633Swpaul 20240516Swpaul/* 20340516Swpaul * Transmit descriptor status register bits. 20440516Swpaul */ 205215018Syongari#define RL_TXSTAT_LENMASK 0x00001FFF 206215018Syongari#define RL_TXSTAT_OWN 0x00002000 207215018Syongari#define RL_TXSTAT_TX_UNDERRUN 0x00004000 208215018Syongari#define RL_TXSTAT_TX_OK 0x00008000 209215018Syongari#define RL_TXSTAT_EARLY_THRESH 0x003F0000 210215018Syongari#define RL_TXSTAT_COLLCNT 0x0F000000 211215018Syongari#define RL_TXSTAT_CARR_HBEAT 0x10000000 212215018Syongari#define RL_TXSTAT_OUTOFWIN 0x20000000 213215018Syongari#define RL_TXSTAT_TXABRT 0x40000000 214215018Syongari#define RL_TXSTAT_CARRLOSS 0x80000000 21540516Swpaul 21640516Swpaul/* 21740516Swpaul * Interrupt status register bits. 21840516Swpaul */ 219215018Syongari#define RL_ISR_RX_OK 0x0001 220215018Syongari#define RL_ISR_RX_ERR 0x0002 221215018Syongari#define RL_ISR_TX_OK 0x0004 222215018Syongari#define RL_ISR_TX_ERR 0x0008 223215018Syongari#define RL_ISR_RX_OVERRUN 0x0010 224215018Syongari#define RL_ISR_PKT_UNDERRUN 0x0020 225215018Syongari#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 226215018Syongari#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 227215018Syongari#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 228215018Syongari#define RL_ISR_SWI 0x0100 /* C+ only */ 229215018Syongari#define RL_ISR_CABLE_LEN_CHGD 0x2000 230215018Syongari#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 231215018Syongari#define RL_ISR_TIMEOUT_EXPIRED 0x4000 232215018Syongari#define RL_ISR_SYSTEM_ERR 0x8000 23340516Swpaul 234215018Syongari#define RL_INTRS \ 23540516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 23640516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 23740516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 23840516Swpaul 239159962Swpaul#ifdef RE_TX_MODERATION 240215018Syongari#define RL_INTRS_CPLUS \ 241119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 242117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 243117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 244159962Swpaul#else 245215018Syongari#define RL_INTRS_CPLUS \ 246159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 247159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 248159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 249159962Swpaul#endif 250117388Swpaul 25140516Swpaul/* 25240516Swpaul * Media status register. (8139 only) 25340516Swpaul */ 254215018Syongari#define RL_MEDIASTAT_RXPAUSE 0x01 255215018Syongari#define RL_MEDIASTAT_TXPAUSE 0x02 256215018Syongari#define RL_MEDIASTAT_LINK 0x04 257215018Syongari#define RL_MEDIASTAT_SPEED10 0x08 258215018Syongari#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 259215018Syongari#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 26040516Swpaul 26140516Swpaul/* 26240516Swpaul * Receive config register. 26340516Swpaul */ 264215018Syongari#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 265215018Syongari#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 266215018Syongari#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 267215018Syongari#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 268215018Syongari#define RL_RXCFG_RX_RUNT 0x00000010 269215018Syongari#define RL_RXCFG_RX_ERRPKT 0x00000020 270215018Syongari#define RL_RXCFG_WRAP 0x00000080 271215018Syongari#define RL_RXCFG_MAXDMA 0x00000700 272215018Syongari#define RL_RXCFG_BUFSZ 0x00001800 273215018Syongari#define RL_RXCFG_FIFOTHRESH 0x0000E000 274215018Syongari#define RL_RXCFG_EARLYTHRESH 0x07000000 27540516Swpaul 276215018Syongari#define RL_RXDMA_16BYTES 0x00000000 277215018Syongari#define RL_RXDMA_32BYTES 0x00000100 278215018Syongari#define RL_RXDMA_64BYTES 0x00000200 279215018Syongari#define RL_RXDMA_128BYTES 0x00000300 280215018Syongari#define RL_RXDMA_256BYTES 0x00000400 281215018Syongari#define RL_RXDMA_512BYTES 0x00000500 282215018Syongari#define RL_RXDMA_1024BYTES 0x00000600 283215018Syongari#define RL_RXDMA_UNLIMITED 0x00000700 28445633Swpaul 285215018Syongari#define RL_RXBUF_8 0x00000000 286215018Syongari#define RL_RXBUF_16 0x00000800 287215018Syongari#define RL_RXBUF_32 0x00001000 288215018Syongari#define RL_RXBUF_64 0x00001800 28940516Swpaul 290215018Syongari#define RL_RXFIFO_16BYTES 0x00000000 291215018Syongari#define RL_RXFIFO_32BYTES 0x00002000 292215018Syongari#define RL_RXFIFO_64BYTES 0x00004000 293215018Syongari#define RL_RXFIFO_128BYTES 0x00006000 294215018Syongari#define RL_RXFIFO_256BYTES 0x00008000 295215018Syongari#define RL_RXFIFO_512BYTES 0x0000A000 296215018Syongari#define RL_RXFIFO_1024BYTES 0x0000C000 297215018Syongari#define RL_RXFIFO_NOTHRESH 0x0000E000 29845633Swpaul 29940516Swpaul/* 30040516Swpaul * Bits in RX status header (included with RX'ed packet 30140516Swpaul * in ring buffer). 30240516Swpaul */ 303215018Syongari#define RL_RXSTAT_RXOK 0x00000001 304215018Syongari#define RL_RXSTAT_ALIGNERR 0x00000002 305215018Syongari#define RL_RXSTAT_CRCERR 0x00000004 306215018Syongari#define RL_RXSTAT_GIANT 0x00000008 307215018Syongari#define RL_RXSTAT_RUNT 0x00000010 308215018Syongari#define RL_RXSTAT_BADSYM 0x00000020 309215018Syongari#define RL_RXSTAT_BROAD 0x00002000 310215018Syongari#define RL_RXSTAT_INDIV 0x00004000 311215018Syongari#define RL_RXSTAT_MULTI 0x00008000 312215018Syongari#define RL_RXSTAT_LENMASK 0xFFFF0000 31340516Swpaul 314215018Syongari#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 31540516Swpaul/* 31640516Swpaul * Command register. 31740516Swpaul */ 318215018Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 319215018Syongari#define RL_CMD_TX_ENB 0x0004 320215018Syongari#define RL_CMD_RX_ENB 0x0008 321215018Syongari#define RL_CMD_RESET 0x0010 322215018Syongari#define RL_CMD_STOPREQ 0x0080 32340516Swpaul 32440516Swpaul/* 325184515Simp * Twister register values. These are completely undocumented and derived 326184515Simp * from public sources. 327184515Simp */ 328215018Syongari#define RL_CSCFG_LINK_OK 0x0400 329215018Syongari#define RL_CSCFG_CHANGE 0x0800 330215018Syongari#define RL_CSCFG_STATUS 0xf000 331215018Syongari#define RL_CSCFG_ROW3 0x7000 332215018Syongari#define RL_CSCFG_ROW2 0x3000 333215018Syongari#define RL_CSCFG_ROW1 0x1000 334215018Syongari#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 335215018Syongari#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 336184515Simp 337215018Syongari#define RL_NWAYTST_RESET 0 338215018Syongari#define RL_NWAYTST_CBL_TEST 0x20 339184515Simp 340215018Syongari#define RL_PARA78 0x78 341215018Syongari#define RL_PARA78_DEF 0x78fa8388 342215018Syongari#define RL_PARA7C 0x7C 343215018Syongari#define RL_PARA7C_DEF 0xcb38de43 344215018Syongari#define RL_PARA7C_RETUNE 0xfb38de03 345184515Simp/* 34640516Swpaul * EEPROM control register 34740516Swpaul */ 348215018Syongari#define RL_EE_DATAOUT 0x01 /* Data out */ 349215018Syongari#define RL_EE_DATAIN 0x02 /* Data in */ 350215018Syongari#define RL_EE_CLK 0x04 /* clock */ 351215018Syongari#define RL_EE_SEL 0x08 /* chip select */ 352215018Syongari#define RL_EE_MODE (0x40|0x80) 35340516Swpaul 354215018Syongari#define RL_EEMODE_OFF 0x00 355215018Syongari#define RL_EEMODE_AUTOLOAD 0x40 356215018Syongari#define RL_EEMODE_PROGRAM 0x80 357215018Syongari#define RL_EEMODE_WRITECFG (0x80|0x40) 35840516Swpaul 35940516Swpaul/* 9346 EEPROM commands */ 360215018Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 361215018Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 362159962Swpaul 363215018Syongari#define RL_9346_WRITE 0x5 364215018Syongari#define RL_9346_READ 0x6 365215018Syongari#define RL_9346_ERASE 0x7 366215018Syongari#define RL_9346_EWEN 0x4 367215018Syongari#define RL_9346_EWEN_ADDR 0x30 368215018Syongari#define RL_9456_EWDS 0x4 369215018Syongari#define RL_9346_EWDS_ADDR 0x00 370159962Swpaul 371215018Syongari#define RL_EECMD_WRITE 0x140 372215018Syongari#define RL_EECMD_READ_6BIT 0x180 373215018Syongari#define RL_EECMD_READ_8BIT 0x600 374215018Syongari#define RL_EECMD_ERASE 0x1c0 37540516Swpaul 376215018Syongari#define RL_EE_ID 0x00 377215018Syongari#define RL_EE_PCI_VID 0x01 378215018Syongari#define RL_EE_PCI_DID 0x02 37940516Swpaul/* Location of station address inside EEPROM */ 380215018Syongari#define RL_EE_EADDR 0x07 38140516Swpaul 38240516Swpaul/* 38340516Swpaul * MII register (8129 only) 38440516Swpaul */ 385215018Syongari#define RL_MII_CLK 0x01 386215018Syongari#define RL_MII_DATAIN 0x02 387215018Syongari#define RL_MII_DATAOUT 0x04 388215018Syongari#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 38940516Swpaul 39040516Swpaul/* 39140516Swpaul * Config 0 register 39240516Swpaul */ 393215018Syongari#define RL_CFG0_ROM0 0x01 394215018Syongari#define RL_CFG0_ROM1 0x02 395215018Syongari#define RL_CFG0_ROM2 0x04 396215018Syongari#define RL_CFG0_PL0 0x08 397215018Syongari#define RL_CFG0_PL1 0x10 398215018Syongari#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 399215018Syongari#define RL_CFG0_PCS 0x40 400215018Syongari#define RL_CFG0_SCR 0x80 40140516Swpaul 40240516Swpaul/* 40340516Swpaul * Config 1 register 40440516Swpaul */ 405215018Syongari#define RL_CFG1_PWRDWN 0x01 406215019Syongari#define RL_CFG1_PME 0x01 407215018Syongari#define RL_CFG1_SLEEP 0x02 408215018Syongari#define RL_CFG1_VPDEN 0x02 409215018Syongari#define RL_CFG1_IOMAP 0x04 410215018Syongari#define RL_CFG1_MEMMAP 0x08 411215018Syongari#define RL_CFG1_RSVD 0x10 412176754Syongari#define RL_CFG1_LWACT 0x10 413215018Syongari#define RL_CFG1_DRVLOAD 0x20 414215018Syongari#define RL_CFG1_LED0 0x40 415215018Syongari#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 416215018Syongari#define RL_CFG1_LED1 0x80 41740516Swpaul 41840516Swpaul/* 419176754Syongari * Config 2 register 420176754Syongari */ 421176754Syongari#define RL_CFG2_PCI33MHZ 0x00 422176754Syongari#define RL_CFG2_PCI66MHZ 0x01 423176754Syongari#define RL_CFG2_PCI64BIT 0x08 424176754Syongari#define RL_CFG2_AUXPWR 0x10 425177522Syongari#define RL_CFG2_MSI 0x20 426176754Syongari 427176754Syongari/* 428176754Syongari * Config 3 register 429176754Syongari */ 430176754Syongari#define RL_CFG3_GRANTSEL 0x80 431176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 432176754Syongari#define RL_CFG3_WOL_LINK 0x10 433217499Syongari#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 434176754Syongari#define RL_CFG3_FAST_B2B 0x01 435176754Syongari 436176754Syongari/* 437176754Syongari * Config 4 register 438176754Syongari */ 439176754Syongari#define RL_CFG4_LWPTN 0x04 440176754Syongari#define RL_CFG4_LWPME 0x10 441217499Syongari#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 442176754Syongari 443176754Syongari/* 444176754Syongari * Config 5 register 445176754Syongari */ 446176754Syongari#define RL_CFG5_WOL_BCAST 0x40 447176754Syongari#define RL_CFG5_WOL_MCAST 0x20 448176754Syongari#define RL_CFG5_WOL_UCAST 0x10 449176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 450176754Syongari#define RL_CFG5_PME_STS 0x01 451176754Syongari 452176754Syongari/* 453117388Swpaul * 8139C+ register definitions 454117388Swpaul */ 455117388Swpaul 456117388Swpaul/* RL_DUMPSTATS_LO register */ 457117388Swpaul 458215018Syongari#define RL_DUMPSTATS_START 0x00000008 459117388Swpaul 460117388Swpaul/* Transmit start register */ 461117388Swpaul 462215018Syongari#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 463215018Syongari#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 464215018Syongari#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 465117388Swpaul 466120043Swpaul/* 467120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 468120043Swpaul */ 469215018Syongari#define RL_CFG2_BUSFREQ 0x07 470215018Syongari#define RL_CFG2_BUSWIDTH 0x08 471215018Syongari#define RL_CFG2_AUXPWRSTS 0x10 472120043Swpaul 473215018Syongari#define RL_BUSFREQ_33MHZ 0x00 474215018Syongari#define RL_BUSFREQ_66MHZ 0x01 475215019Syongari 476215018Syongari#define RL_BUSWIDTH_32BITS 0x00 477215018Syongari#define RL_BUSWIDTH_64BITS 0x08 478120043Swpaul 479117388Swpaul/* C+ mode command register */ 480117388Swpaul 481215018Syongari#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 482215018Syongari#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 483215018Syongari#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 484215018Syongari#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 485215018Syongari#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 486215018Syongari#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 487180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 488180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 489180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 490180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 491180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 492180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 493180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 494180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 495180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 496117388Swpaul 497117388Swpaul/* C+ early transmit threshold */ 498117388Swpaul 499215019Syongari#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 500117388Swpaul 501217902Syongari/* Timer interrupt register */ 502217902Syongari#define RL_TIMERINT_8169_VAL 0x00001FFF 503217902Syongari#define RL_TIMER_MIN 0 504217902Syongari#define RL_TIMER_MAX 65 /* 65.528us */ 505217902Syongari#define RL_TIMER_DEFAULT RL_TIMER_MAX 506217902Syongari#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 507217902Syongari#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 508217902Syongari 509117388Swpaul/* 510117388Swpaul * Gigabit PHY access register (8169 only) 511117388Swpaul */ 512117388Swpaul 513215018Syongari#define RL_PHYAR_PHYDATA 0x0000FFFF 514215018Syongari#define RL_PHYAR_PHYREG 0x001F0000 515215018Syongari#define RL_PHYAR_BUSY 0x80000000 516117388Swpaul 517117388Swpaul/* 518117388Swpaul * Gigabit media status (8169 only) 519117388Swpaul */ 520215018Syongari#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 521215018Syongari#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 522215018Syongari#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 523215018Syongari#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 524215018Syongari#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 525215018Syongari#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 526215018Syongari#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 527215018Syongari#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 528117388Swpaul 529117388Swpaul/* 53040516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 53140516Swpaul * Instead, there are only four register sets, each or which represents 53240516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 53340516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 53440516Swpaul * the registers so the chip knows where they are. 53540516Swpaul * 53640516Swpaul * We can sort of kludge together the same kind of buffer management 53740516Swpaul * used in previous drivers, but we have to do buffer copies almost all 53840516Swpaul * the time, so it doesn't really buy us much. 53940516Swpaul * 54040516Swpaul * For reception, there's just one large buffer where the chip stores 54140516Swpaul * all received packets. 54240516Swpaul */ 54340516Swpaul 544215018Syongari#define RL_RX_BUF_SZ RL_RXBUF_64 545215018Syongari#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 546215018Syongari#define RL_TX_LIST_CNT 4 547215018Syongari#define RL_MIN_FRAMELEN 60 548184240Syongari#define RL_TX_8139_BUF_ALIGN 4 549184240Syongari#define RL_RX_8139_BUF_ALIGN 8 550184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 551184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 552215019Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 553215018Syongari#define RL_TXTHRESH(x) ((x) << 11) 554215018Syongari#define RL_TX_THRESH_INIT 96 555215018Syongari#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 556215018Syongari#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 557215018Syongari#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 55840516Swpaul 559215018Syongari#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 560215018Syongari#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 56140516Swpaul 562215018Syongari#define RL_ETHER_ALIGN 2 56348028Swpaul 564177771Syongari/* 565177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 566177771Syongari */ 567177771Syongari#define RL_IP4CSUMTX_MINLEN 28 568177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 569177771Syongari 57040516Swpaulstruct rl_chain_data { 571131605Sbms uint16_t cur_rx; 572131605Sbms uint8_t *rl_rx_buf; 573131605Sbms uint8_t *rl_rx_buf_ptr; 57440516Swpaul 57545633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 57681713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 577184240Syongari bus_dma_tag_t rl_tx_tag; 578184240Syongari bus_dma_tag_t rl_rx_tag; 579184240Syongari bus_dmamap_t rl_rx_dmamap; 580184240Syongari bus_addr_t rl_rx_buf_paddr; 581131605Sbms uint8_t last_tx; 582131605Sbms uint8_t cur_tx; 58340516Swpaul}; 58440516Swpaul 585215018Syongari#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 586215018Syongari#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 587215018Syongari#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 588215018Syongari#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 589215018Syongari#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 590215018Syongari#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 591215018Syongari#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 592215018Syongari#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 593215018Syongari#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 59445633Swpaul 59540516Swpaulstruct rl_type { 596131605Sbms uint16_t rl_vid; 597131605Sbms uint16_t rl_did; 598117388Swpaul int rl_basetype; 59940516Swpaul char *rl_name; 60040516Swpaul}; 60140516Swpaul 602117388Swpaulstruct rl_hwrev { 603131605Sbms uint32_t rl_rev; 604117388Swpaul int rl_type; 605117388Swpaul char *rl_desc; 606217499Syongari int rl_max_mtu; 607117388Swpaul}; 608117388Swpaul 60940516Swpaulstruct rl_mii_frame { 610131605Sbms uint8_t mii_stdelim; 611131605Sbms uint8_t mii_opcode; 612131605Sbms uint8_t mii_phyaddr; 613131605Sbms uint8_t mii_regaddr; 614131605Sbms uint8_t mii_turnaround; 615131605Sbms uint16_t mii_data; 61640516Swpaul}; 61740516Swpaul 61840516Swpaul/* 61940516Swpaul * MII constants 62040516Swpaul */ 621215018Syongari#define RL_MII_STARTDELIM 0x01 622215018Syongari#define RL_MII_READOP 0x02 623215018Syongari#define RL_MII_WRITEOP 0x01 624215018Syongari#define RL_MII_TURNAROUND 0x02 62540516Swpaul 626215018Syongari#define RL_8129 1 627215018Syongari#define RL_8139 2 628215018Syongari#define RL_8139CPLUS 3 629215018Syongari#define RL_8169 4 63040516Swpaul 631215018Syongari#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 632117388Swpaul (x)->rl_type == RL_8169) 633117388Swpaul 634117388Swpaul/* 635117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 636117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 637117388Swpaul * must be allocated in contiguous blocks that are aligned on a 638117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 639117388Swpaul */ 640117388Swpaul 641117388Swpaul/* 642117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 643117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 644117388Swpaul * the checksum offload bits are disabled. The structure layout is 645117388Swpaul * the same for RX and TX descriptors 646117388Swpaul */ 647117388Swpaul 648117388Swpaulstruct rl_desc { 649131605Sbms uint32_t rl_cmdstat; 650131605Sbms uint32_t rl_vlanctl; 651131605Sbms uint32_t rl_bufaddr_lo; 652131605Sbms uint32_t rl_bufaddr_hi; 653117388Swpaul}; 654117388Swpaul 655215018Syongari#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 656215018Syongari#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 657215018Syongari#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 658215018Syongari#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 659215018Syongari#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 660215018Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 661215018Syongari#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 662215018Syongari#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 663215018Syongari#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 664215018Syongari#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 665215018Syongari#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 666117388Swpaul 667215018Syongari#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 668215018Syongari#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 669180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 670180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 671215019Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 672215019Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 673217246Syongari#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 674217246Syongari#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 675117388Swpaul 676117388Swpaul/* 677117388Swpaul * Error bits are valid only on the last descriptor of a frame 678117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 679117388Swpaul */ 680117388Swpaul 681215018Syongari#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 682215018Syongari#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 683215018Syongari#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 684215018Syongari#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 685215018Syongari#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 686215018Syongari#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 687215018Syongari#define RL_TDESC_STAT_OWN 0x80000000 688117388Swpaul 689117388Swpaul/* 690117388Swpaul * RX descriptor cmd/vlan definitions 691117388Swpaul */ 692117388Swpaul 693215018Syongari#define RL_RDESC_CMD_EOR 0x40000000 694215018Syongari#define RL_RDESC_CMD_OWN 0x80000000 695215018Syongari#define RL_RDESC_CMD_BUFLEN 0x00001FFF 696117388Swpaul 697215018Syongari#define RL_RDESC_STAT_OWN 0x80000000 698215018Syongari#define RL_RDESC_STAT_EOR 0x40000000 699215018Syongari#define RL_RDESC_STAT_SOF 0x20000000 700215018Syongari#define RL_RDESC_STAT_EOF 0x10000000 701215018Syongari#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 702215018Syongari#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 703215018Syongari#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 704215018Syongari#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 705215018Syongari#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 706215018Syongari#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 707215018Syongari#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 708215018Syongari#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 709215018Syongari#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 710215018Syongari#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 711215018Syongari#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 712180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 713180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 714215018Syongari#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 715215018Syongari#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 716215018Syongari#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 717215018Syongari#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 718215018Syongari#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 719215018Syongari#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 720135896Sjmg RL_RDESC_STAT_CRCERR) 721117388Swpaul 722215018Syongari#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 723117388Swpaul (rl_vlandata valid)*/ 724215018Syongari#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 725180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 726180176Syongari#define RL_RDESC_IPV6 0x80000000 727180176Syongari#define RL_RDESC_IPV4 0x40000000 728117388Swpaul 729215018Syongari#define RL_PROTOID_NONIP 0x00000000 730215018Syongari#define RL_PROTOID_TCPIP 0x00010000 731215018Syongari#define RL_PROTOID_UDPIP 0x00020000 732215018Syongari#define RL_PROTOID_IP 0x00030000 733215018Syongari#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 734117388Swpaul RL_PROTOID_TCPIP) 735215018Syongari#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 736117388Swpaul RL_PROTOID_UDPIP) 737117388Swpaul 738117388Swpaul/* 739117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 740117388Swpaul */ 741117388Swpaulstruct rl_stats { 742214844Syongari uint64_t rl_tx_pkts; 743214844Syongari uint64_t rl_rx_pkts; 744214844Syongari uint64_t rl_tx_errs; 745214844Syongari uint32_t rl_rx_errs; 746131605Sbms uint16_t rl_missed_pkts; 747131605Sbms uint16_t rl_rx_framealign_errs; 748131605Sbms uint32_t rl_tx_onecoll; 749131605Sbms uint32_t rl_tx_multicolls; 750214844Syongari uint64_t rl_rx_ucasts; 751214844Syongari uint64_t rl_rx_bcasts; 752131605Sbms uint32_t rl_rx_mcasts; 753131605Sbms uint16_t rl_tx_aborts; 754131605Sbms uint16_t rl_rx_underruns; 755117388Swpaul}; 756117388Swpaul 757135467Sjmg/* 758135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 759135467Sjmg * 760175337Syongari * 8139C+ 761175337Syongari * Number of descriptors supported : up to 64 762175337Syongari * Descriptor alignment : 256 bytes 763175337Syongari * Tx buffer : At least 4 bytes in length. 764175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 765215019Syongari * 766175337Syongari * 8169 767175337Syongari * Number of descriptors supported : up to 1024 768175337Syongari * Descriptor alignment : 256 bytes 769175337Syongari * Tx buffer : At least 4 bytes in length. 770175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 771135467Sjmg */ 772164460Syongari#ifndef __NO_STRICT_ALIGNMENT 773215018Syongari#define RE_FIXUP_RX 1 774135896Sjmg#endif 775135896Sjmg 776215018Syongari#define RL_8169_TX_DESC_CNT 256 777215018Syongari#define RL_8169_RX_DESC_CNT 256 778215018Syongari#define RL_8139_TX_DESC_CNT 64 779215018Syongari#define RL_8139_RX_DESC_CNT 64 780215018Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 781215018Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 782217499Syongari#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 783175337Syongari#define RL_NTXSEGS 32 784159962Swpaul 785215018Syongari#define RL_RING_ALIGN 256 786215018Syongari#define RL_DUMP_ALIGN 64 787215018Syongari#define RL_IFQ_MAXLEN 512 788215018Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 789215018Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 790215018Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 791215018Syongari#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 792215018Syongari#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 793215018Syongari#define RL_PKTSZ(x) ((x)/* >> 3*/) 794135896Sjmg#ifdef RE_FIXUP_RX 795215018Syongari#define RE_ETHER_ALIGN sizeof(uint64_t) 796215018Syongari#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 797135896Sjmg#else 798215018Syongari#define RE_ETHER_ALIGN 0 799215018Syongari#define RE_RX_DESC_BUFLEN MCLBYTES 800135896Sjmg#endif 801117388Swpaul 802188474Syongari#define RL_MSI_MESSAGES 1 803171560Syongari 804215018Syongari#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 805215018Syongari#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 806118712Swpaul 807181270Syongari/* 808181270Syongari * The number of bits reserved for MSS in RealTek controllers is 809181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 810181270Syongari * as upper stack should not generate TCP segments with MSS greater 811181270Syongari * than the limit. 812181270Syongari */ 813181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 814181270Syongari 815135896Sjmg/* see comment in dev/re/if_re.c */ 816215018Syongari#define RL_JUMBO_FRAMELEN 7440 817217499Syongari#define RL_JUMBO_MTU \ 818217499Syongari (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 819217499Syongari#define RL_JUMBO_MTU_6K \ 820217499Syongari ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 821217499Syongari#define RL_JUMBO_MTU_9K \ 822217499Syongari ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 823217499Syongari#define RL_MTU \ 824176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 825119868Swpaul 826175337Syongaristruct rl_txdesc { 827175337Syongari struct mbuf *tx_m; 828175337Syongari bus_dmamap_t tx_dmamap; 829175337Syongari}; 830117388Swpaul 831175337Syongaristruct rl_rxdesc { 832175337Syongari struct mbuf *rx_m; 833175337Syongari bus_dmamap_t rx_dmamap; 834175337Syongari bus_size_t rx_size; 835117388Swpaul}; 836117388Swpaul 837117388Swpaulstruct rl_list_data { 838175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 839175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 840217499Syongari struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 841175337Syongari int rl_tx_desc_cnt; 842175337Syongari int rl_rx_desc_cnt; 843117388Swpaul int rl_tx_prodidx; 844117388Swpaul int rl_rx_prodidx; 845117388Swpaul int rl_tx_considx; 846117388Swpaul int rl_tx_free; 847175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 848175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 849217499Syongari bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 850175337Syongari bus_dmamap_t rl_rx_sparemap; 851217499Syongari bus_dmamap_t rl_jrx_sparemap; 852117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 853117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 854117388Swpaul struct rl_stats *rl_stats; 855118712Swpaul bus_addr_t rl_stats_addr; 856117388Swpaul bus_dma_tag_t rl_rx_list_tag; 857117388Swpaul bus_dmamap_t rl_rx_list_map; 858117388Swpaul struct rl_desc *rl_rx_list; 859118712Swpaul bus_addr_t rl_rx_list_addr; 860117388Swpaul bus_dma_tag_t rl_tx_list_tag; 861117388Swpaul bus_dmamap_t rl_tx_list_map; 862117388Swpaul struct rl_desc *rl_tx_list; 863118712Swpaul bus_addr_t rl_tx_list_addr; 864117388Swpaul}; 865117388Swpaul 866184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 867184515Simp 86840516Swpaulstruct rl_softc { 869147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 87041569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 87141569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 872159962Swpaul device_t rl_dev; 87350703Swpaul struct resource *rl_res; 874180169Syongari int rl_res_id; 875180169Syongari int rl_res_type; 876217857Syongari struct resource *rl_res_pba; 877171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 878171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 87950703Swpaul device_t rl_miibus; 88081713Swpaul bus_dma_tag_t rl_parent_tag; 881131605Sbms uint8_t rl_type; 882217499Syongari struct rl_hwrev *rl_hwrev; 88367931Swpaul int rl_eecmd_read; 884159962Swpaul int rl_eewidth; 88552426Swpaul int rl_txthresh; 88640516Swpaul struct rl_chain_data rl_cdata; 887117388Swpaul struct rl_list_data rl_ldata; 888150720Sjhb struct callout rl_stat_callout; 889164811Sru int rl_watchdog_timer; 89067087Swpaul struct mtx rl_mtx; 891119868Swpaul struct mbuf *rl_head; 892119868Swpaul struct mbuf *rl_tail; 893131605Sbms uint32_t rl_rxlenmask; 894119868Swpaul int rl_testmode; 895168828Syongari int rl_if_flags; 896184559Simp int rl_twister_enable; 897184515Simp enum rl_twist rl_twister; 898184515Simp int rl_twist_row; 899184515Simp int rl_twist_col; 90086822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 90194883Sluigi#ifdef DEVICE_POLLING 90294883Sluigi int rxcycles; 90394883Sluigi#endif 904159962Swpaul 905159962Swpaul struct task rl_inttask; 906159962Swpaul 907159962Swpaul int rl_txstart; 908217902Syongari int rl_int_rx_act; 909217902Syongari int rl_int_rx_mod; 910180171Syongari uint32_t rl_flags; 911180171Syongari#define RL_FLAG_MSI 0x0001 912191301Syongari#define RL_FLAG_AUTOPAD 0x0002 913206433Syongari#define RL_FLAG_PHYWAKE_PM 0x0004 914180171Syongari#define RL_FLAG_PHYWAKE 0x0008 915217499Syongari#define RL_FLAG_JUMBOV2 0x0010 916180176Syongari#define RL_FLAG_PAR 0x0020 917180176Syongari#define RL_FLAG_DESCV2 0x0040 918180176Syongari#define RL_FLAG_MACSTAT 0x0080 919185753Syongari#define RL_FLAG_FASTETHER 0x0100 920185900Syongari#define RL_FLAG_CMDSTOP 0x0200 921187483Sjkim#define RL_FLAG_MACRESET 0x0400 922217857Syongari#define RL_FLAG_MSIX 0x0800 923185903Syongari#define RL_FLAG_WOLRXENB 0x1000 924186210Syongari#define RL_FLAG_MACSLEEP 0x2000 925186214Syongari#define RL_FLAG_PCIE 0x4000 926180171Syongari#define RL_FLAG_LINK 0x8000 92740516Swpaul}; 92840516Swpaul 92972200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 93072200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 931122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 93267087Swpaul 93340516Swpaul/* 93440516Swpaul * register space access macros 93540516Swpaul */ 936215018Syongari#define CSR_WRITE_STREAM_4(sc, reg, val) \ 937119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 938215018Syongari#define CSR_WRITE_4(sc, reg, val) \ 93941569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 940215018Syongari#define CSR_WRITE_2(sc, reg, val) \ 94141569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 942215018Syongari#define CSR_WRITE_1(sc, reg, val) \ 94341569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 94440516Swpaul 945215018Syongari#define CSR_READ_4(sc, reg) \ 94641569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 947215018Syongari#define CSR_READ_2(sc, reg) \ 94841569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 949215018Syongari#define CSR_READ_1(sc, reg) \ 95041569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 95140516Swpaul 952215018Syongari#define CSR_SETBIT_1(sc, offset, val) \ 953159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 954159962Swpaul 955215018Syongari#define CSR_CLRBIT_1(sc, offset, val) \ 956159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 957159962Swpaul 958215018Syongari#define CSR_SETBIT_2(sc, offset, val) \ 959159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 960159962Swpaul 961215018Syongari#define CSR_CLRBIT_2(sc, offset, val) \ 962159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 963159962Swpaul 964215018Syongari#define CSR_SETBIT_4(sc, offset, val) \ 965159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 966159962Swpaul 967215018Syongari#define CSR_CLRBIT_4(sc, offset, val) \ 968159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 969159962Swpaul 970215018Syongari#define RL_TIMEOUT 1000 971215018Syongari#define RL_PHY_TIMEOUT 2000 97240516Swpaul 97340516Swpaul/* 97440516Swpaul * General constants that are fun to know. 97540516Swpaul * 97640516Swpaul * RealTek PCI vendor ID 97740516Swpaul */ 97840516Swpaul#define RT_VENDORID 0x10EC 97940516Swpaul 98040516Swpaul/* 98140516Swpaul * RealTek chip device IDs. 98240516Swpaul */ 983215018Syongari#define RT_DEVICEID_8139D 0x8039 98440516Swpaul#define RT_DEVICEID_8129 0x8129 985215018Syongari#define RT_DEVICEID_8101E 0x8136 98667771Swpaul#define RT_DEVICEID_8138 0x8138 98740516Swpaul#define RT_DEVICEID_8139 0x8139 988215018Syongari#define RT_DEVICEID_8169SC 0x8167 989215018Syongari#define RT_DEVICEID_8168 0x8168 990215018Syongari#define RT_DEVICEID_8169 0x8169 991215018Syongari#define RT_DEVICEID_8100 0x8100 99240516Swpaul 993215018Syongari#define RT_REVID_8139CPLUS 0x20 994117388Swpaul 99540516Swpaul/* 99644238Swpaul * Accton PCI vendor ID 99744238Swpaul */ 998215018Syongari#define ACCTON_VENDORID 0x1113 99944238Swpaul 100044238Swpaul/* 100141243Swpaul * Accton MPX 5030/5038 device ID. 100241243Swpaul */ 1003215018Syongari#define ACCTON_DEVICEID_5030 0x1211 100441243Swpaul 100541243Swpaul/* 100694400Swpaul * Nortel PCI vendor ID 100794400Swpaul */ 1008215018Syongari#define NORTEL_VENDORID 0x126C 100994400Swpaul 101094400Swpaul/* 101144238Swpaul * Delta Electronics Vendor ID. 101244238Swpaul */ 1013215018Syongari#define DELTA_VENDORID 0x1500 101444238Swpaul 101544238Swpaul/* 101644238Swpaul * Delta device IDs. 101744238Swpaul */ 1018215018Syongari#define DELTA_DEVICEID_8139 0x1360 101944238Swpaul 102044238Swpaul/* 102144238Swpaul * Addtron vendor ID. 102244238Swpaul */ 1023215018Syongari#define ADDTRON_VENDORID 0x4033 102444238Swpaul 102544238Swpaul/* 102644238Swpaul * Addtron device IDs. 102744238Swpaul */ 1028215018Syongari#define ADDTRON_DEVICEID_8139 0x1360 102944238Swpaul 103044238Swpaul/* 103172813Swpaul * D-Link vendor ID. 103272813Swpaul */ 1033215018Syongari#define DLINK_VENDORID 0x1186 103472813Swpaul 103572813Swpaul/* 103672813Swpaul * D-Link DFE-530TX+ device ID 103772813Swpaul */ 1038215018Syongari#define DLINK_DEVICEID_530TXPLUS 0x1300 103972813Swpaul 104072813Swpaul/* 1041148722Stobez * D-Link DFE-5280T device ID 1042148722Stobez */ 1043215018Syongari#define DLINK_DEVICEID_528T 0x4300 1044148722Stobez 1045148722Stobez/* 104696112Sjhb * D-Link DFE-690TXD device ID 104796112Sjhb */ 1048215018Syongari#define DLINK_DEVICEID_690TXD 0x1340 104996112Sjhb 105096112Sjhb/* 1051103020Siwasaki * Corega K.K vendor ID 1052103020Siwasaki */ 1053215018Syongari#define COREGA_VENDORID 0x1259 1054103020Siwasaki 1055103020Siwasaki/* 1056109095Ssanpei * Corega FEther CB-TXD device ID 1057103020Siwasaki */ 1058215018Syongari#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1059103020Siwasaki 1060103020Siwasaki/* 1061109095Ssanpei * Corega FEtherII CB-TXD device ID 1062109095Ssanpei */ 1063215018Syongari#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1064109095Ssanpei 1065111381Sdan/* 1066134433Ssanpei * Corega CG-LAPCIGT device ID 1067134433Ssanpei */ 1068215018Syongari#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1069134433Ssanpei 1070134433Ssanpei/* 1071151341Sjhb * Linksys vendor ID 1072151341Sjhb */ 1073215018Syongari#define LINKSYS_VENDORID 0x1737 1074151341Sjhb 1075151341Sjhb/* 1076151341Sjhb * Linksys EG1032 device ID 1077151341Sjhb */ 1078215018Syongari#define LINKSYS_DEVICEID_EG1032 0x1032 1079151341Sjhb 1080151341Sjhb/* 1081151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1082151341Sjhb */ 1083215018Syongari#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1084151341Sjhb 1085151341Sjhb/* 1086111381Sdan * Peppercon vendor ID 1087111381Sdan */ 1088215018Syongari#define PEPPERCON_VENDORID 0x1743 1089109095Ssanpei 1090111381Sdan/* 1091111381Sdan * Peppercon ROL-F device ID 1092111381Sdan */ 1093215018Syongari#define PEPPERCON_DEVICEID_ROLF 0x8139 1094109095Ssanpei 1095109095Ssanpei/* 1096112379Ssanpei * Planex Communications, Inc. vendor ID 1097112379Ssanpei */ 1098215018Syongari#define PLANEX_VENDORID 0x14ea 1099112379Ssanpei 1100112379Ssanpei/* 1101173948Sremko * Planex FNW-3603-TX device ID 1102173948Sremko */ 1103215018Syongari#define PLANEX_DEVICEID_FNW3603TX 0xab06 1104173948Sremko 1105173948Sremko/* 1106112379Ssanpei * Planex FNW-3800-TX device ID 1107112379Ssanpei */ 1108215018Syongari#define PLANEX_DEVICEID_FNW3800TX 0xab07 1109112379Ssanpei 1110112379Ssanpei/* 1111117388Swpaul * LevelOne vendor ID 1112117388Swpaul */ 1113215018Syongari#define LEVEL1_VENDORID 0x018A 1114117388Swpaul 1115117388Swpaul/* 1116117388Swpaul * LevelOne FPC-0106TX devide ID 1117117388Swpaul */ 1118215018Syongari#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1119117388Swpaul 1120117388Swpaul/* 1121117388Swpaul * Compaq vendor ID 1122117388Swpaul */ 1123215018Syongari#define CP_VENDORID 0x021B 1124117388Swpaul 1125117388Swpaul/* 1126117388Swpaul * Edimax vendor ID 1127117388Swpaul */ 1128215018Syongari#define EDIMAX_VENDORID 0x13D1 1129117388Swpaul 1130117388Swpaul/* 1131117388Swpaul * Edimax EP-4103DL cardbus device ID 1132117388Swpaul */ 1133215018Syongari#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1134117388Swpaul 1135160883Swpaul/* US Robotics vendor ID */ 1136160883Swpaul 1137215018Syongari#define USR_VENDORID 0x16EC 1138160883Swpaul 1139160883Swpaul/* US Robotics 997902 device ID */ 1140160883Swpaul 1141215018Syongari#define USR_DEVICEID_997902 0x0116 1142