if_rlreg.h revision 217902
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 217902 2011-01-26 20:25:40Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39215018Syongari#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40215018Syongari#define RL_IDR2 0x0002 41215018Syongari#define RL_IDR3 0x0003 42215018Syongari#define RL_IDR4 0x0004 43215018Syongari#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 45215018Syongari#define RL_MAR0 0x0008 /* Multicast hash table */ 46215018Syongari#define RL_MAR1 0x0009 47215018Syongari#define RL_MAR2 0x000A 48215018Syongari#define RL_MAR3 0x000B 49215018Syongari#define RL_MAR4 0x000C 50215018Syongari#define RL_MAR5 0x000D 51215018Syongari#define RL_MAR6 0x000E 52215018Syongari#define RL_MAR7 0x000F 5340516Swpaul 54215018Syongari#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55215018Syongari#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56215018Syongari#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57215018Syongari#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 59215018Syongari#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60215018Syongari#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61215018Syongari#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62215018Syongari#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 64215018Syongari#define RL_RXADDR 0x0030 /* RX ring start address */ 65215018Syongari#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66215018Syongari#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67215018Syongari#define RL_COMMAND 0x0037 /* command register */ 68215018Syongari#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69215018Syongari#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70215018Syongari#define RL_IMR 0x003C /* interrupt mask register */ 71215018Syongari#define RL_ISR 0x003E /* interrupt status register */ 72215018Syongari#define RL_TXCFG 0x0040 /* transmit config */ 73215018Syongari#define RL_RXCFG 0x0044 /* receive config */ 74215018Syongari#define RL_TIMERCNT 0x0048 /* timer count register */ 75215018Syongari#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76215018Syongari#define RL_EECMD 0x0050 /* EEPROM command register */ 77215018Syongari#define RL_CFG0 0x0051 /* config register #0 */ 78215018Syongari#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 84215018Syongari#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 86215018Syongari#define RL_MII 0x005A /* 8129 chip only */ 87215018Syongari#define RL_HALTCLK 0x005B 88215018Syongari#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89215018Syongari#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 91215018Syongari#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 94215018Syongari#define RL_BMCR 0x0062 /* PHY basic mode control */ 95215018Syongari#define RL_BMSR 0x0064 /* PHY basic mode status */ 96215018Syongari#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97215018Syongari#define RL_LPAR 0x0068 /* PHY link partner ability */ 98215018Syongari#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 100215018Syongari#define RL_DISCCNT 0x006C /* disconnect counter */ 101215018Syongari#define RL_FALSECAR 0x006E /* false carrier counter */ 102215018Syongari#define RL_NWAYTST 0x0070 /* NWAY test register */ 103215018Syongari#define RL_RX_ER 0x0072 /* RX_ER counter */ 104215018Syongari#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111215018Syongari#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112215018Syongari#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113215018Syongari#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114215018Syongari#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115215018Syongari#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116215018Syongari#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117215018Syongari#define RL_CFG2 0x0053 118215018Syongari#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119215018Syongari#define RL_TXSTART 0x00D9 /* 8 bits */ 120215018Syongari#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121215018Syongari#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122215018Syongari#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123215018Syongari#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128215018Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 129215018Syongari#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130215018Syongari#define RL_PHYAR 0x0060 131215018Syongari#define RL_TBICSR 0x0064 132215018Syongari#define RL_TBI_ANAR 0x0068 133215018Syongari#define RL_TBI_LPAR 0x006A 134215018Syongari#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135215018Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136215018Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137215018Syongari#define RL_PMCH 0x006F /* 8 bits */ 138215018Syongari#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139215018Syongari#define RL_INTRMOD 0x00E2 /* 16 bits */ 140117388Swpaul 141117388Swpaul/* 14240516Swpaul * TX config register bits 14340516Swpaul */ 144215018Syongari#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145215018Syongari#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146215018Syongari#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147215018Syongari#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148215018Syongari#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149215018Syongari#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150215018Syongari#define RL_TXCFG_HWREV 0x7CC00000 15140516Swpaul 152215018Syongari#define RL_LOOPTEST_OFF 0x00000000 153215018Syongari#define RL_LOOPTEST_ON 0x00020000 154215018Syongari#define RL_LOOPTEST_ON_CPLUS 0x00060000 155119868Swpaul 156159962Swpaul/* Known revision codes. */ 157117388Swpaul 158215018Syongari#define RL_HWREV_8169 0x00000000 159215018Syongari#define RL_HWREV_8169S 0x00800000 160215018Syongari#define RL_HWREV_8110S 0x04000000 161215018Syongari#define RL_HWREV_8169_8110SB 0x10000000 162215018Syongari#define RL_HWREV_8169_8110SC 0x18000000 163215018Syongari#define RL_HWREV_8102EL 0x24800000 164215018Syongari#define RL_HWREV_8102EL_SPIN1 0x24C00000 165215018Syongari#define RL_HWREV_8168D 0x28000000 166215018Syongari#define RL_HWREV_8168DP 0x28800000 167215018Syongari#define RL_HWREV_8168E 0x2C000000 168217498Syongari#define RL_HWREV_8168E_VL 0x2C800000 169217524Syongari#define RL_HWREV_8168B_SPIN1 0x30000000 170215018Syongari#define RL_HWREV_8100E 0x30800000 171215018Syongari#define RL_HWREV_8101E 0x34000000 172215018Syongari#define RL_HWREV_8102E 0x34800000 173215018Syongari#define RL_HWREV_8103E 0x34C00000 174217524Syongari#define RL_HWREV_8168B_SPIN2 0x38000000 175217524Syongari#define RL_HWREV_8168B_SPIN3 0x38400000 176215018Syongari#define RL_HWREV_8168C 0x3C000000 177215018Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 178215018Syongari#define RL_HWREV_8168CP 0x3C800000 179215018Syongari#define RL_HWREV_8139 0x60000000 180215018Syongari#define RL_HWREV_8139A 0x70000000 181215018Syongari#define RL_HWREV_8139AG 0x70800000 182215018Syongari#define RL_HWREV_8139B 0x78000000 183215018Syongari#define RL_HWREV_8130 0x7C000000 184215018Syongari#define RL_HWREV_8139C 0x74000000 185215018Syongari#define RL_HWREV_8139D 0x74400000 186215018Syongari#define RL_HWREV_8139CPLUS 0x74800000 187215018Syongari#define RL_HWREV_8101 0x74C00000 188215018Syongari#define RL_HWREV_8100 0x78800000 189215018Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 190215018Syongari#define RL_HWREV_8169_8110SCE 0x98000000 191159962Swpaul 192215018Syongari#define RL_TXDMA_16BYTES 0x00000000 193215018Syongari#define RL_TXDMA_32BYTES 0x00000100 194215018Syongari#define RL_TXDMA_64BYTES 0x00000200 195215018Syongari#define RL_TXDMA_128BYTES 0x00000300 196215018Syongari#define RL_TXDMA_256BYTES 0x00000400 197215018Syongari#define RL_TXDMA_512BYTES 0x00000500 198215018Syongari#define RL_TXDMA_1024BYTES 0x00000600 199215018Syongari#define RL_TXDMA_2048BYTES 0x00000700 20045633Swpaul 20140516Swpaul/* 20240516Swpaul * Transmit descriptor status register bits. 20340516Swpaul */ 204215018Syongari#define RL_TXSTAT_LENMASK 0x00001FFF 205215018Syongari#define RL_TXSTAT_OWN 0x00002000 206215018Syongari#define RL_TXSTAT_TX_UNDERRUN 0x00004000 207215018Syongari#define RL_TXSTAT_TX_OK 0x00008000 208215018Syongari#define RL_TXSTAT_EARLY_THRESH 0x003F0000 209215018Syongari#define RL_TXSTAT_COLLCNT 0x0F000000 210215018Syongari#define RL_TXSTAT_CARR_HBEAT 0x10000000 211215018Syongari#define RL_TXSTAT_OUTOFWIN 0x20000000 212215018Syongari#define RL_TXSTAT_TXABRT 0x40000000 213215018Syongari#define RL_TXSTAT_CARRLOSS 0x80000000 21440516Swpaul 21540516Swpaul/* 21640516Swpaul * Interrupt status register bits. 21740516Swpaul */ 218215018Syongari#define RL_ISR_RX_OK 0x0001 219215018Syongari#define RL_ISR_RX_ERR 0x0002 220215018Syongari#define RL_ISR_TX_OK 0x0004 221215018Syongari#define RL_ISR_TX_ERR 0x0008 222215018Syongari#define RL_ISR_RX_OVERRUN 0x0010 223215018Syongari#define RL_ISR_PKT_UNDERRUN 0x0020 224215018Syongari#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 225215018Syongari#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 226215018Syongari#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 227215018Syongari#define RL_ISR_SWI 0x0100 /* C+ only */ 228215018Syongari#define RL_ISR_CABLE_LEN_CHGD 0x2000 229215018Syongari#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 230215018Syongari#define RL_ISR_TIMEOUT_EXPIRED 0x4000 231215018Syongari#define RL_ISR_SYSTEM_ERR 0x8000 23240516Swpaul 233215018Syongari#define RL_INTRS \ 23440516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 23540516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 23640516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 23740516Swpaul 238159962Swpaul#ifdef RE_TX_MODERATION 239215018Syongari#define RL_INTRS_CPLUS \ 240119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 241117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 242117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 243159962Swpaul#else 244215018Syongari#define RL_INTRS_CPLUS \ 245159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 246159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 247159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 248159962Swpaul#endif 249117388Swpaul 25040516Swpaul/* 25140516Swpaul * Media status register. (8139 only) 25240516Swpaul */ 253215018Syongari#define RL_MEDIASTAT_RXPAUSE 0x01 254215018Syongari#define RL_MEDIASTAT_TXPAUSE 0x02 255215018Syongari#define RL_MEDIASTAT_LINK 0x04 256215018Syongari#define RL_MEDIASTAT_SPEED10 0x08 257215018Syongari#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 258215018Syongari#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 25940516Swpaul 26040516Swpaul/* 26140516Swpaul * Receive config register. 26240516Swpaul */ 263215018Syongari#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 264215018Syongari#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 265215018Syongari#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 266215018Syongari#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 267215018Syongari#define RL_RXCFG_RX_RUNT 0x00000010 268215018Syongari#define RL_RXCFG_RX_ERRPKT 0x00000020 269215018Syongari#define RL_RXCFG_WRAP 0x00000080 270215018Syongari#define RL_RXCFG_MAXDMA 0x00000700 271215018Syongari#define RL_RXCFG_BUFSZ 0x00001800 272215018Syongari#define RL_RXCFG_FIFOTHRESH 0x0000E000 273215018Syongari#define RL_RXCFG_EARLYTHRESH 0x07000000 27440516Swpaul 275215018Syongari#define RL_RXDMA_16BYTES 0x00000000 276215018Syongari#define RL_RXDMA_32BYTES 0x00000100 277215018Syongari#define RL_RXDMA_64BYTES 0x00000200 278215018Syongari#define RL_RXDMA_128BYTES 0x00000300 279215018Syongari#define RL_RXDMA_256BYTES 0x00000400 280215018Syongari#define RL_RXDMA_512BYTES 0x00000500 281215018Syongari#define RL_RXDMA_1024BYTES 0x00000600 282215018Syongari#define RL_RXDMA_UNLIMITED 0x00000700 28345633Swpaul 284215018Syongari#define RL_RXBUF_8 0x00000000 285215018Syongari#define RL_RXBUF_16 0x00000800 286215018Syongari#define RL_RXBUF_32 0x00001000 287215018Syongari#define RL_RXBUF_64 0x00001800 28840516Swpaul 289215018Syongari#define RL_RXFIFO_16BYTES 0x00000000 290215018Syongari#define RL_RXFIFO_32BYTES 0x00002000 291215018Syongari#define RL_RXFIFO_64BYTES 0x00004000 292215018Syongari#define RL_RXFIFO_128BYTES 0x00006000 293215018Syongari#define RL_RXFIFO_256BYTES 0x00008000 294215018Syongari#define RL_RXFIFO_512BYTES 0x0000A000 295215018Syongari#define RL_RXFIFO_1024BYTES 0x0000C000 296215018Syongari#define RL_RXFIFO_NOTHRESH 0x0000E000 29745633Swpaul 29840516Swpaul/* 29940516Swpaul * Bits in RX status header (included with RX'ed packet 30040516Swpaul * in ring buffer). 30140516Swpaul */ 302215018Syongari#define RL_RXSTAT_RXOK 0x00000001 303215018Syongari#define RL_RXSTAT_ALIGNERR 0x00000002 304215018Syongari#define RL_RXSTAT_CRCERR 0x00000004 305215018Syongari#define RL_RXSTAT_GIANT 0x00000008 306215018Syongari#define RL_RXSTAT_RUNT 0x00000010 307215018Syongari#define RL_RXSTAT_BADSYM 0x00000020 308215018Syongari#define RL_RXSTAT_BROAD 0x00002000 309215018Syongari#define RL_RXSTAT_INDIV 0x00004000 310215018Syongari#define RL_RXSTAT_MULTI 0x00008000 311215018Syongari#define RL_RXSTAT_LENMASK 0xFFFF0000 31240516Swpaul 313215018Syongari#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 31440516Swpaul/* 31540516Swpaul * Command register. 31640516Swpaul */ 317215018Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 318215018Syongari#define RL_CMD_TX_ENB 0x0004 319215018Syongari#define RL_CMD_RX_ENB 0x0008 320215018Syongari#define RL_CMD_RESET 0x0010 321215018Syongari#define RL_CMD_STOPREQ 0x0080 32240516Swpaul 32340516Swpaul/* 324184515Simp * Twister register values. These are completely undocumented and derived 325184515Simp * from public sources. 326184515Simp */ 327215018Syongari#define RL_CSCFG_LINK_OK 0x0400 328215018Syongari#define RL_CSCFG_CHANGE 0x0800 329215018Syongari#define RL_CSCFG_STATUS 0xf000 330215018Syongari#define RL_CSCFG_ROW3 0x7000 331215018Syongari#define RL_CSCFG_ROW2 0x3000 332215018Syongari#define RL_CSCFG_ROW1 0x1000 333215018Syongari#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 334215018Syongari#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 335184515Simp 336215018Syongari#define RL_NWAYTST_RESET 0 337215018Syongari#define RL_NWAYTST_CBL_TEST 0x20 338184515Simp 339215018Syongari#define RL_PARA78 0x78 340215018Syongari#define RL_PARA78_DEF 0x78fa8388 341215018Syongari#define RL_PARA7C 0x7C 342215018Syongari#define RL_PARA7C_DEF 0xcb38de43 343215018Syongari#define RL_PARA7C_RETUNE 0xfb38de03 344184515Simp/* 34540516Swpaul * EEPROM control register 34640516Swpaul */ 347215018Syongari#define RL_EE_DATAOUT 0x01 /* Data out */ 348215018Syongari#define RL_EE_DATAIN 0x02 /* Data in */ 349215018Syongari#define RL_EE_CLK 0x04 /* clock */ 350215018Syongari#define RL_EE_SEL 0x08 /* chip select */ 351215018Syongari#define RL_EE_MODE (0x40|0x80) 35240516Swpaul 353215018Syongari#define RL_EEMODE_OFF 0x00 354215018Syongari#define RL_EEMODE_AUTOLOAD 0x40 355215018Syongari#define RL_EEMODE_PROGRAM 0x80 356215018Syongari#define RL_EEMODE_WRITECFG (0x80|0x40) 35740516Swpaul 35840516Swpaul/* 9346 EEPROM commands */ 359215018Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 360215018Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 361159962Swpaul 362215018Syongari#define RL_9346_WRITE 0x5 363215018Syongari#define RL_9346_READ 0x6 364215018Syongari#define RL_9346_ERASE 0x7 365215018Syongari#define RL_9346_EWEN 0x4 366215018Syongari#define RL_9346_EWEN_ADDR 0x30 367215018Syongari#define RL_9456_EWDS 0x4 368215018Syongari#define RL_9346_EWDS_ADDR 0x00 369159962Swpaul 370215018Syongari#define RL_EECMD_WRITE 0x140 371215018Syongari#define RL_EECMD_READ_6BIT 0x180 372215018Syongari#define RL_EECMD_READ_8BIT 0x600 373215018Syongari#define RL_EECMD_ERASE 0x1c0 37440516Swpaul 375215018Syongari#define RL_EE_ID 0x00 376215018Syongari#define RL_EE_PCI_VID 0x01 377215018Syongari#define RL_EE_PCI_DID 0x02 37840516Swpaul/* Location of station address inside EEPROM */ 379215018Syongari#define RL_EE_EADDR 0x07 38040516Swpaul 38140516Swpaul/* 38240516Swpaul * MII register (8129 only) 38340516Swpaul */ 384215018Syongari#define RL_MII_CLK 0x01 385215018Syongari#define RL_MII_DATAIN 0x02 386215018Syongari#define RL_MII_DATAOUT 0x04 387215018Syongari#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 38840516Swpaul 38940516Swpaul/* 39040516Swpaul * Config 0 register 39140516Swpaul */ 392215018Syongari#define RL_CFG0_ROM0 0x01 393215018Syongari#define RL_CFG0_ROM1 0x02 394215018Syongari#define RL_CFG0_ROM2 0x04 395215018Syongari#define RL_CFG0_PL0 0x08 396215018Syongari#define RL_CFG0_PL1 0x10 397215018Syongari#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 398215018Syongari#define RL_CFG0_PCS 0x40 399215018Syongari#define RL_CFG0_SCR 0x80 40040516Swpaul 40140516Swpaul/* 40240516Swpaul * Config 1 register 40340516Swpaul */ 404215018Syongari#define RL_CFG1_PWRDWN 0x01 405215019Syongari#define RL_CFG1_PME 0x01 406215018Syongari#define RL_CFG1_SLEEP 0x02 407215018Syongari#define RL_CFG1_VPDEN 0x02 408215018Syongari#define RL_CFG1_IOMAP 0x04 409215018Syongari#define RL_CFG1_MEMMAP 0x08 410215018Syongari#define RL_CFG1_RSVD 0x10 411176754Syongari#define RL_CFG1_LWACT 0x10 412215018Syongari#define RL_CFG1_DRVLOAD 0x20 413215018Syongari#define RL_CFG1_LED0 0x40 414215018Syongari#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 415215018Syongari#define RL_CFG1_LED1 0x80 41640516Swpaul 41740516Swpaul/* 418176754Syongari * Config 2 register 419176754Syongari */ 420176754Syongari#define RL_CFG2_PCI33MHZ 0x00 421176754Syongari#define RL_CFG2_PCI66MHZ 0x01 422176754Syongari#define RL_CFG2_PCI64BIT 0x08 423176754Syongari#define RL_CFG2_AUXPWR 0x10 424177522Syongari#define RL_CFG2_MSI 0x20 425176754Syongari 426176754Syongari/* 427176754Syongari * Config 3 register 428176754Syongari */ 429176754Syongari#define RL_CFG3_GRANTSEL 0x80 430176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 431176754Syongari#define RL_CFG3_WOL_LINK 0x10 432217499Syongari#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 433176754Syongari#define RL_CFG3_FAST_B2B 0x01 434176754Syongari 435176754Syongari/* 436176754Syongari * Config 4 register 437176754Syongari */ 438176754Syongari#define RL_CFG4_LWPTN 0x04 439176754Syongari#define RL_CFG4_LWPME 0x10 440217499Syongari#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 441176754Syongari 442176754Syongari/* 443176754Syongari * Config 5 register 444176754Syongari */ 445176754Syongari#define RL_CFG5_WOL_BCAST 0x40 446176754Syongari#define RL_CFG5_WOL_MCAST 0x20 447176754Syongari#define RL_CFG5_WOL_UCAST 0x10 448176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 449176754Syongari#define RL_CFG5_PME_STS 0x01 450176754Syongari 451176754Syongari/* 452117388Swpaul * 8139C+ register definitions 453117388Swpaul */ 454117388Swpaul 455117388Swpaul/* RL_DUMPSTATS_LO register */ 456117388Swpaul 457215018Syongari#define RL_DUMPSTATS_START 0x00000008 458117388Swpaul 459117388Swpaul/* Transmit start register */ 460117388Swpaul 461215018Syongari#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 462215018Syongari#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 463215018Syongari#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 464117388Swpaul 465120043Swpaul/* 466120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 467120043Swpaul */ 468215018Syongari#define RL_CFG2_BUSFREQ 0x07 469215018Syongari#define RL_CFG2_BUSWIDTH 0x08 470215018Syongari#define RL_CFG2_AUXPWRSTS 0x10 471120043Swpaul 472215018Syongari#define RL_BUSFREQ_33MHZ 0x00 473215018Syongari#define RL_BUSFREQ_66MHZ 0x01 474215019Syongari 475215018Syongari#define RL_BUSWIDTH_32BITS 0x00 476215018Syongari#define RL_BUSWIDTH_64BITS 0x08 477120043Swpaul 478117388Swpaul/* C+ mode command register */ 479117388Swpaul 480215018Syongari#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 481215018Syongari#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 482215018Syongari#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 483215018Syongari#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 484215018Syongari#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 485215018Syongari#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 486180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 487180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 488180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 489180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 490180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 491180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 492180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 493180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 494180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 495117388Swpaul 496117388Swpaul/* C+ early transmit threshold */ 497117388Swpaul 498215019Syongari#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 499117388Swpaul 500217902Syongari/* Timer interrupt register */ 501217902Syongari#define RL_TIMERINT_8169_VAL 0x00001FFF 502217902Syongari#define RL_TIMER_MIN 0 503217902Syongari#define RL_TIMER_MAX 65 /* 65.528us */ 504217902Syongari#define RL_TIMER_DEFAULT RL_TIMER_MAX 505217902Syongari#define RL_TIMER_PCIE_CLK 125 /* 125MHZ */ 506217902Syongari#define RL_USECS(x) ((x) * RL_TIMER_PCIE_CLK) 507217902Syongari 508117388Swpaul/* 509117388Swpaul * Gigabit PHY access register (8169 only) 510117388Swpaul */ 511117388Swpaul 512215018Syongari#define RL_PHYAR_PHYDATA 0x0000FFFF 513215018Syongari#define RL_PHYAR_PHYREG 0x001F0000 514215018Syongari#define RL_PHYAR_BUSY 0x80000000 515117388Swpaul 516117388Swpaul/* 517117388Swpaul * Gigabit media status (8169 only) 518117388Swpaul */ 519215018Syongari#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 520215018Syongari#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 521215018Syongari#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 522215018Syongari#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 523215018Syongari#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 524215018Syongari#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 525215018Syongari#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 526215018Syongari#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 527117388Swpaul 528117388Swpaul/* 52940516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 53040516Swpaul * Instead, there are only four register sets, each or which represents 53140516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 53240516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 53340516Swpaul * the registers so the chip knows where they are. 53440516Swpaul * 53540516Swpaul * We can sort of kludge together the same kind of buffer management 53640516Swpaul * used in previous drivers, but we have to do buffer copies almost all 53740516Swpaul * the time, so it doesn't really buy us much. 53840516Swpaul * 53940516Swpaul * For reception, there's just one large buffer where the chip stores 54040516Swpaul * all received packets. 54140516Swpaul */ 54240516Swpaul 543215018Syongari#define RL_RX_BUF_SZ RL_RXBUF_64 544215018Syongari#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 545215018Syongari#define RL_TX_LIST_CNT 4 546215018Syongari#define RL_MIN_FRAMELEN 60 547184240Syongari#define RL_TX_8139_BUF_ALIGN 4 548184240Syongari#define RL_RX_8139_BUF_ALIGN 8 549184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 550184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 551215019Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 552215018Syongari#define RL_TXTHRESH(x) ((x) << 11) 553215018Syongari#define RL_TX_THRESH_INIT 96 554215018Syongari#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 555215018Syongari#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 556215018Syongari#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 55740516Swpaul 558215018Syongari#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 559215018Syongari#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 56040516Swpaul 561215018Syongari#define RL_ETHER_ALIGN 2 56248028Swpaul 563177771Syongari/* 564177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 565177771Syongari */ 566177771Syongari#define RL_IP4CSUMTX_MINLEN 28 567177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 568177771Syongari 56940516Swpaulstruct rl_chain_data { 570131605Sbms uint16_t cur_rx; 571131605Sbms uint8_t *rl_rx_buf; 572131605Sbms uint8_t *rl_rx_buf_ptr; 57340516Swpaul 57445633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 57581713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 576184240Syongari bus_dma_tag_t rl_tx_tag; 577184240Syongari bus_dma_tag_t rl_rx_tag; 578184240Syongari bus_dmamap_t rl_rx_dmamap; 579184240Syongari bus_addr_t rl_rx_buf_paddr; 580131605Sbms uint8_t last_tx; 581131605Sbms uint8_t cur_tx; 58240516Swpaul}; 58340516Swpaul 584215018Syongari#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 585215018Syongari#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 586215018Syongari#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 587215018Syongari#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 588215018Syongari#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 589215018Syongari#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 590215018Syongari#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 591215018Syongari#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 592215018Syongari#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 59345633Swpaul 59440516Swpaulstruct rl_type { 595131605Sbms uint16_t rl_vid; 596131605Sbms uint16_t rl_did; 597117388Swpaul int rl_basetype; 59840516Swpaul char *rl_name; 59940516Swpaul}; 60040516Swpaul 601117388Swpaulstruct rl_hwrev { 602131605Sbms uint32_t rl_rev; 603117388Swpaul int rl_type; 604117388Swpaul char *rl_desc; 605217499Syongari int rl_max_mtu; 606117388Swpaul}; 607117388Swpaul 60840516Swpaulstruct rl_mii_frame { 609131605Sbms uint8_t mii_stdelim; 610131605Sbms uint8_t mii_opcode; 611131605Sbms uint8_t mii_phyaddr; 612131605Sbms uint8_t mii_regaddr; 613131605Sbms uint8_t mii_turnaround; 614131605Sbms uint16_t mii_data; 61540516Swpaul}; 61640516Swpaul 61740516Swpaul/* 61840516Swpaul * MII constants 61940516Swpaul */ 620215018Syongari#define RL_MII_STARTDELIM 0x01 621215018Syongari#define RL_MII_READOP 0x02 622215018Syongari#define RL_MII_WRITEOP 0x01 623215018Syongari#define RL_MII_TURNAROUND 0x02 62440516Swpaul 625215018Syongari#define RL_8129 1 626215018Syongari#define RL_8139 2 627215018Syongari#define RL_8139CPLUS 3 628215018Syongari#define RL_8169 4 62940516Swpaul 630215018Syongari#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 631117388Swpaul (x)->rl_type == RL_8169) 632117388Swpaul 633117388Swpaul/* 634117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 635117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 636117388Swpaul * must be allocated in contiguous blocks that are aligned on a 637117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 638117388Swpaul */ 639117388Swpaul 640117388Swpaul/* 641117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 642117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 643117388Swpaul * the checksum offload bits are disabled. The structure layout is 644117388Swpaul * the same for RX and TX descriptors 645117388Swpaul */ 646117388Swpaul 647117388Swpaulstruct rl_desc { 648131605Sbms uint32_t rl_cmdstat; 649131605Sbms uint32_t rl_vlanctl; 650131605Sbms uint32_t rl_bufaddr_lo; 651131605Sbms uint32_t rl_bufaddr_hi; 652117388Swpaul}; 653117388Swpaul 654215018Syongari#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 655215018Syongari#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 656215018Syongari#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 657215018Syongari#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 658215018Syongari#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 659215018Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 660215018Syongari#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 661215018Syongari#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 662215018Syongari#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 663215018Syongari#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 664215018Syongari#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 665117388Swpaul 666215018Syongari#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 667215018Syongari#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 668180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 669180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 670215019Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 671215019Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 672217246Syongari#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 673217246Syongari#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 674117388Swpaul 675117388Swpaul/* 676117388Swpaul * Error bits are valid only on the last descriptor of a frame 677117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 678117388Swpaul */ 679117388Swpaul 680215018Syongari#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 681215018Syongari#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 682215018Syongari#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 683215018Syongari#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 684215018Syongari#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 685215018Syongari#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 686215018Syongari#define RL_TDESC_STAT_OWN 0x80000000 687117388Swpaul 688117388Swpaul/* 689117388Swpaul * RX descriptor cmd/vlan definitions 690117388Swpaul */ 691117388Swpaul 692215018Syongari#define RL_RDESC_CMD_EOR 0x40000000 693215018Syongari#define RL_RDESC_CMD_OWN 0x80000000 694215018Syongari#define RL_RDESC_CMD_BUFLEN 0x00001FFF 695117388Swpaul 696215018Syongari#define RL_RDESC_STAT_OWN 0x80000000 697215018Syongari#define RL_RDESC_STAT_EOR 0x40000000 698215018Syongari#define RL_RDESC_STAT_SOF 0x20000000 699215018Syongari#define RL_RDESC_STAT_EOF 0x10000000 700215018Syongari#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 701215018Syongari#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 702215018Syongari#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 703215018Syongari#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 704215018Syongari#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 705215018Syongari#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 706215018Syongari#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 707215018Syongari#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 708215018Syongari#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 709215018Syongari#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 710215018Syongari#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 711180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 712180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 713215018Syongari#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 714215018Syongari#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 715215018Syongari#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 716215018Syongari#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 717215018Syongari#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 718215018Syongari#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 719135896Sjmg RL_RDESC_STAT_CRCERR) 720117388Swpaul 721215018Syongari#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 722117388Swpaul (rl_vlandata valid)*/ 723215018Syongari#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 724180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 725180176Syongari#define RL_RDESC_IPV6 0x80000000 726180176Syongari#define RL_RDESC_IPV4 0x40000000 727117388Swpaul 728215018Syongari#define RL_PROTOID_NONIP 0x00000000 729215018Syongari#define RL_PROTOID_TCPIP 0x00010000 730215018Syongari#define RL_PROTOID_UDPIP 0x00020000 731215018Syongari#define RL_PROTOID_IP 0x00030000 732215018Syongari#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 733117388Swpaul RL_PROTOID_TCPIP) 734215018Syongari#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 735117388Swpaul RL_PROTOID_UDPIP) 736117388Swpaul 737117388Swpaul/* 738117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 739117388Swpaul */ 740117388Swpaulstruct rl_stats { 741214844Syongari uint64_t rl_tx_pkts; 742214844Syongari uint64_t rl_rx_pkts; 743214844Syongari uint64_t rl_tx_errs; 744214844Syongari uint32_t rl_rx_errs; 745131605Sbms uint16_t rl_missed_pkts; 746131605Sbms uint16_t rl_rx_framealign_errs; 747131605Sbms uint32_t rl_tx_onecoll; 748131605Sbms uint32_t rl_tx_multicolls; 749214844Syongari uint64_t rl_rx_ucasts; 750214844Syongari uint64_t rl_rx_bcasts; 751131605Sbms uint32_t rl_rx_mcasts; 752131605Sbms uint16_t rl_tx_aborts; 753131605Sbms uint16_t rl_rx_underruns; 754117388Swpaul}; 755117388Swpaul 756135467Sjmg/* 757135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 758135467Sjmg * 759175337Syongari * 8139C+ 760175337Syongari * Number of descriptors supported : up to 64 761175337Syongari * Descriptor alignment : 256 bytes 762175337Syongari * Tx buffer : At least 4 bytes in length. 763175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 764215019Syongari * 765175337Syongari * 8169 766175337Syongari * Number of descriptors supported : up to 1024 767175337Syongari * Descriptor alignment : 256 bytes 768175337Syongari * Tx buffer : At least 4 bytes in length. 769175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 770135467Sjmg */ 771164460Syongari#ifndef __NO_STRICT_ALIGNMENT 772215018Syongari#define RE_FIXUP_RX 1 773135896Sjmg#endif 774135896Sjmg 775215018Syongari#define RL_8169_TX_DESC_CNT 256 776215018Syongari#define RL_8169_RX_DESC_CNT 256 777215018Syongari#define RL_8139_TX_DESC_CNT 64 778215018Syongari#define RL_8139_RX_DESC_CNT 64 779215018Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 780215018Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 781217499Syongari#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 782175337Syongari#define RL_NTXSEGS 32 783159962Swpaul 784215018Syongari#define RL_RING_ALIGN 256 785215018Syongari#define RL_DUMP_ALIGN 64 786215018Syongari#define RL_IFQ_MAXLEN 512 787215018Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 788215018Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 789215018Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 790215018Syongari#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 791215018Syongari#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 792215018Syongari#define RL_PKTSZ(x) ((x)/* >> 3*/) 793135896Sjmg#ifdef RE_FIXUP_RX 794215018Syongari#define RE_ETHER_ALIGN sizeof(uint64_t) 795215018Syongari#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 796135896Sjmg#else 797215018Syongari#define RE_ETHER_ALIGN 0 798215018Syongari#define RE_RX_DESC_BUFLEN MCLBYTES 799135896Sjmg#endif 800117388Swpaul 801188474Syongari#define RL_MSI_MESSAGES 1 802171560Syongari 803215018Syongari#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 804215018Syongari#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 805118712Swpaul 806181270Syongari/* 807181270Syongari * The number of bits reserved for MSS in RealTek controllers is 808181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 809181270Syongari * as upper stack should not generate TCP segments with MSS greater 810181270Syongari * than the limit. 811181270Syongari */ 812181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 813181270Syongari 814135896Sjmg/* see comment in dev/re/if_re.c */ 815215018Syongari#define RL_JUMBO_FRAMELEN 7440 816217499Syongari#define RL_JUMBO_MTU \ 817217499Syongari (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 818217499Syongari#define RL_JUMBO_MTU_6K \ 819217499Syongari ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 820217499Syongari#define RL_JUMBO_MTU_9K \ 821217499Syongari ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 822217499Syongari#define RL_MTU \ 823176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 824119868Swpaul 825175337Syongaristruct rl_txdesc { 826175337Syongari struct mbuf *tx_m; 827175337Syongari bus_dmamap_t tx_dmamap; 828175337Syongari}; 829117388Swpaul 830175337Syongaristruct rl_rxdesc { 831175337Syongari struct mbuf *rx_m; 832175337Syongari bus_dmamap_t rx_dmamap; 833175337Syongari bus_size_t rx_size; 834117388Swpaul}; 835117388Swpaul 836117388Swpaulstruct rl_list_data { 837175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 838175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 839217499Syongari struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 840175337Syongari int rl_tx_desc_cnt; 841175337Syongari int rl_rx_desc_cnt; 842117388Swpaul int rl_tx_prodidx; 843117388Swpaul int rl_rx_prodidx; 844117388Swpaul int rl_tx_considx; 845117388Swpaul int rl_tx_free; 846175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 847175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 848217499Syongari bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 849175337Syongari bus_dmamap_t rl_rx_sparemap; 850217499Syongari bus_dmamap_t rl_jrx_sparemap; 851117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 852117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 853117388Swpaul struct rl_stats *rl_stats; 854118712Swpaul bus_addr_t rl_stats_addr; 855117388Swpaul bus_dma_tag_t rl_rx_list_tag; 856117388Swpaul bus_dmamap_t rl_rx_list_map; 857117388Swpaul struct rl_desc *rl_rx_list; 858118712Swpaul bus_addr_t rl_rx_list_addr; 859117388Swpaul bus_dma_tag_t rl_tx_list_tag; 860117388Swpaul bus_dmamap_t rl_tx_list_map; 861117388Swpaul struct rl_desc *rl_tx_list; 862118712Swpaul bus_addr_t rl_tx_list_addr; 863117388Swpaul}; 864117388Swpaul 865184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 866184515Simp 86740516Swpaulstruct rl_softc { 868147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 86941569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 87041569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 871159962Swpaul device_t rl_dev; 87250703Swpaul struct resource *rl_res; 873180169Syongari int rl_res_id; 874180169Syongari int rl_res_type; 875217857Syongari struct resource *rl_res_pba; 876171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 877171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 87850703Swpaul device_t rl_miibus; 87981713Swpaul bus_dma_tag_t rl_parent_tag; 880131605Sbms uint8_t rl_type; 881217499Syongari struct rl_hwrev *rl_hwrev; 88267931Swpaul int rl_eecmd_read; 883159962Swpaul int rl_eewidth; 88452426Swpaul int rl_txthresh; 88540516Swpaul struct rl_chain_data rl_cdata; 886117388Swpaul struct rl_list_data rl_ldata; 887150720Sjhb struct callout rl_stat_callout; 888164811Sru int rl_watchdog_timer; 88967087Swpaul struct mtx rl_mtx; 890119868Swpaul struct mbuf *rl_head; 891119868Swpaul struct mbuf *rl_tail; 892131605Sbms uint32_t rl_rxlenmask; 893119868Swpaul int rl_testmode; 894168828Syongari int rl_if_flags; 895184559Simp int rl_twister_enable; 896184515Simp enum rl_twist rl_twister; 897184515Simp int rl_twist_row; 898184515Simp int rl_twist_col; 89986822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 90094883Sluigi#ifdef DEVICE_POLLING 90194883Sluigi int rxcycles; 90294883Sluigi#endif 903159962Swpaul 904159962Swpaul struct task rl_inttask; 905159962Swpaul 906159962Swpaul int rl_txstart; 907217902Syongari int rl_int_rx_act; 908217902Syongari int rl_int_rx_mod; 909180171Syongari uint32_t rl_flags; 910180171Syongari#define RL_FLAG_MSI 0x0001 911191301Syongari#define RL_FLAG_AUTOPAD 0x0002 912206433Syongari#define RL_FLAG_PHYWAKE_PM 0x0004 913180171Syongari#define RL_FLAG_PHYWAKE 0x0008 914217499Syongari#define RL_FLAG_JUMBOV2 0x0010 915180176Syongari#define RL_FLAG_PAR 0x0020 916180176Syongari#define RL_FLAG_DESCV2 0x0040 917180176Syongari#define RL_FLAG_MACSTAT 0x0080 918185753Syongari#define RL_FLAG_FASTETHER 0x0100 919185900Syongari#define RL_FLAG_CMDSTOP 0x0200 920187483Sjkim#define RL_FLAG_MACRESET 0x0400 921217857Syongari#define RL_FLAG_MSIX 0x0800 922185903Syongari#define RL_FLAG_WOLRXENB 0x1000 923186210Syongari#define RL_FLAG_MACSLEEP 0x2000 924186214Syongari#define RL_FLAG_PCIE 0x4000 925180171Syongari#define RL_FLAG_LINK 0x8000 92640516Swpaul}; 92740516Swpaul 92872200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 92972200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 930122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 93167087Swpaul 93240516Swpaul/* 93340516Swpaul * register space access macros 93440516Swpaul */ 935215018Syongari#define CSR_WRITE_STREAM_4(sc, reg, val) \ 936119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 937215018Syongari#define CSR_WRITE_4(sc, reg, val) \ 93841569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 939215018Syongari#define CSR_WRITE_2(sc, reg, val) \ 94041569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 941215018Syongari#define CSR_WRITE_1(sc, reg, val) \ 94241569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 94340516Swpaul 944215018Syongari#define CSR_READ_4(sc, reg) \ 94541569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 946215018Syongari#define CSR_READ_2(sc, reg) \ 94741569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 948215018Syongari#define CSR_READ_1(sc, reg) \ 94941569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 95040516Swpaul 951215018Syongari#define CSR_SETBIT_1(sc, offset, val) \ 952159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 953159962Swpaul 954215018Syongari#define CSR_CLRBIT_1(sc, offset, val) \ 955159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 956159962Swpaul 957215018Syongari#define CSR_SETBIT_2(sc, offset, val) \ 958159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 959159962Swpaul 960215018Syongari#define CSR_CLRBIT_2(sc, offset, val) \ 961159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 962159962Swpaul 963215018Syongari#define CSR_SETBIT_4(sc, offset, val) \ 964159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 965159962Swpaul 966215018Syongari#define CSR_CLRBIT_4(sc, offset, val) \ 967159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 968159962Swpaul 969215018Syongari#define RL_TIMEOUT 1000 970215018Syongari#define RL_PHY_TIMEOUT 2000 97140516Swpaul 97240516Swpaul/* 97340516Swpaul * General constants that are fun to know. 97440516Swpaul * 97540516Swpaul * RealTek PCI vendor ID 97640516Swpaul */ 97740516Swpaul#define RT_VENDORID 0x10EC 97840516Swpaul 97940516Swpaul/* 98040516Swpaul * RealTek chip device IDs. 98140516Swpaul */ 982215018Syongari#define RT_DEVICEID_8139D 0x8039 98340516Swpaul#define RT_DEVICEID_8129 0x8129 984215018Syongari#define RT_DEVICEID_8101E 0x8136 98567771Swpaul#define RT_DEVICEID_8138 0x8138 98640516Swpaul#define RT_DEVICEID_8139 0x8139 987215018Syongari#define RT_DEVICEID_8169SC 0x8167 988215018Syongari#define RT_DEVICEID_8168 0x8168 989215018Syongari#define RT_DEVICEID_8169 0x8169 990215018Syongari#define RT_DEVICEID_8100 0x8100 99140516Swpaul 992215018Syongari#define RT_REVID_8139CPLUS 0x20 993117388Swpaul 99440516Swpaul/* 99544238Swpaul * Accton PCI vendor ID 99644238Swpaul */ 997215018Syongari#define ACCTON_VENDORID 0x1113 99844238Swpaul 99944238Swpaul/* 100041243Swpaul * Accton MPX 5030/5038 device ID. 100141243Swpaul */ 1002215018Syongari#define ACCTON_DEVICEID_5030 0x1211 100341243Swpaul 100441243Swpaul/* 100594400Swpaul * Nortel PCI vendor ID 100694400Swpaul */ 1007215018Syongari#define NORTEL_VENDORID 0x126C 100894400Swpaul 100994400Swpaul/* 101044238Swpaul * Delta Electronics Vendor ID. 101144238Swpaul */ 1012215018Syongari#define DELTA_VENDORID 0x1500 101344238Swpaul 101444238Swpaul/* 101544238Swpaul * Delta device IDs. 101644238Swpaul */ 1017215018Syongari#define DELTA_DEVICEID_8139 0x1360 101844238Swpaul 101944238Swpaul/* 102044238Swpaul * Addtron vendor ID. 102144238Swpaul */ 1022215018Syongari#define ADDTRON_VENDORID 0x4033 102344238Swpaul 102444238Swpaul/* 102544238Swpaul * Addtron device IDs. 102644238Swpaul */ 1027215018Syongari#define ADDTRON_DEVICEID_8139 0x1360 102844238Swpaul 102944238Swpaul/* 103072813Swpaul * D-Link vendor ID. 103172813Swpaul */ 1032215018Syongari#define DLINK_VENDORID 0x1186 103372813Swpaul 103472813Swpaul/* 103572813Swpaul * D-Link DFE-530TX+ device ID 103672813Swpaul */ 1037215018Syongari#define DLINK_DEVICEID_530TXPLUS 0x1300 103872813Swpaul 103972813Swpaul/* 1040148722Stobez * D-Link DFE-5280T device ID 1041148722Stobez */ 1042215018Syongari#define DLINK_DEVICEID_528T 0x4300 1043148722Stobez 1044148722Stobez/* 104596112Sjhb * D-Link DFE-690TXD device ID 104696112Sjhb */ 1047215018Syongari#define DLINK_DEVICEID_690TXD 0x1340 104896112Sjhb 104996112Sjhb/* 1050103020Siwasaki * Corega K.K vendor ID 1051103020Siwasaki */ 1052215018Syongari#define COREGA_VENDORID 0x1259 1053103020Siwasaki 1054103020Siwasaki/* 1055109095Ssanpei * Corega FEther CB-TXD device ID 1056103020Siwasaki */ 1057215018Syongari#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1058103020Siwasaki 1059103020Siwasaki/* 1060109095Ssanpei * Corega FEtherII CB-TXD device ID 1061109095Ssanpei */ 1062215018Syongari#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1063109095Ssanpei 1064111381Sdan/* 1065134433Ssanpei * Corega CG-LAPCIGT device ID 1066134433Ssanpei */ 1067215018Syongari#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1068134433Ssanpei 1069134433Ssanpei/* 1070151341Sjhb * Linksys vendor ID 1071151341Sjhb */ 1072215018Syongari#define LINKSYS_VENDORID 0x1737 1073151341Sjhb 1074151341Sjhb/* 1075151341Sjhb * Linksys EG1032 device ID 1076151341Sjhb */ 1077215018Syongari#define LINKSYS_DEVICEID_EG1032 0x1032 1078151341Sjhb 1079151341Sjhb/* 1080151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1081151341Sjhb */ 1082215018Syongari#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1083151341Sjhb 1084151341Sjhb/* 1085111381Sdan * Peppercon vendor ID 1086111381Sdan */ 1087215018Syongari#define PEPPERCON_VENDORID 0x1743 1088109095Ssanpei 1089111381Sdan/* 1090111381Sdan * Peppercon ROL-F device ID 1091111381Sdan */ 1092215018Syongari#define PEPPERCON_DEVICEID_ROLF 0x8139 1093109095Ssanpei 1094109095Ssanpei/* 1095112379Ssanpei * Planex Communications, Inc. vendor ID 1096112379Ssanpei */ 1097215018Syongari#define PLANEX_VENDORID 0x14ea 1098112379Ssanpei 1099112379Ssanpei/* 1100173948Sremko * Planex FNW-3603-TX device ID 1101173948Sremko */ 1102215018Syongari#define PLANEX_DEVICEID_FNW3603TX 0xab06 1103173948Sremko 1104173948Sremko/* 1105112379Ssanpei * Planex FNW-3800-TX device ID 1106112379Ssanpei */ 1107215018Syongari#define PLANEX_DEVICEID_FNW3800TX 0xab07 1108112379Ssanpei 1109112379Ssanpei/* 1110117388Swpaul * LevelOne vendor ID 1111117388Swpaul */ 1112215018Syongari#define LEVEL1_VENDORID 0x018A 1113117388Swpaul 1114117388Swpaul/* 1115117388Swpaul * LevelOne FPC-0106TX devide ID 1116117388Swpaul */ 1117215018Syongari#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1118117388Swpaul 1119117388Swpaul/* 1120117388Swpaul * Compaq vendor ID 1121117388Swpaul */ 1122215018Syongari#define CP_VENDORID 0x021B 1123117388Swpaul 1124117388Swpaul/* 1125117388Swpaul * Edimax vendor ID 1126117388Swpaul */ 1127215018Syongari#define EDIMAX_VENDORID 0x13D1 1128117388Swpaul 1129117388Swpaul/* 1130117388Swpaul * Edimax EP-4103DL cardbus device ID 1131117388Swpaul */ 1132215018Syongari#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1133117388Swpaul 1134160883Swpaul/* US Robotics vendor ID */ 1135160883Swpaul 1136215018Syongari#define USR_VENDORID 0x16EC 1137160883Swpaul 1138160883Swpaul/* US Robotics 997902 device ID */ 1139160883Swpaul 1140215018Syongari#define USR_DEVICEID_997902 0x0116 1141