if_rlreg.h revision 217499
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 217499 2011-01-17 03:24:33Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39215018Syongari#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40215018Syongari#define RL_IDR2 0x0002 41215018Syongari#define RL_IDR3 0x0003 42215018Syongari#define RL_IDR4 0x0004 43215018Syongari#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 45215018Syongari#define RL_MAR0 0x0008 /* Multicast hash table */ 46215018Syongari#define RL_MAR1 0x0009 47215018Syongari#define RL_MAR2 0x000A 48215018Syongari#define RL_MAR3 0x000B 49215018Syongari#define RL_MAR4 0x000C 50215018Syongari#define RL_MAR5 0x000D 51215018Syongari#define RL_MAR6 0x000E 52215018Syongari#define RL_MAR7 0x000F 5340516Swpaul 54215018Syongari#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 55215018Syongari#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 56215018Syongari#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 57215018Syongari#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 59215018Syongari#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 60215018Syongari#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 61215018Syongari#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 62215018Syongari#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 64215018Syongari#define RL_RXADDR 0x0030 /* RX ring start address */ 65215018Syongari#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 66215018Syongari#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 67215018Syongari#define RL_COMMAND 0x0037 /* command register */ 68215018Syongari#define RL_CURRXADDR 0x0038 /* current address of packet read */ 69215018Syongari#define RL_CURRXBUF 0x003A /* current RX buffer address */ 70215018Syongari#define RL_IMR 0x003C /* interrupt mask register */ 71215018Syongari#define RL_ISR 0x003E /* interrupt status register */ 72215018Syongari#define RL_TXCFG 0x0040 /* transmit config */ 73215018Syongari#define RL_RXCFG 0x0044 /* receive config */ 74215018Syongari#define RL_TIMERCNT 0x0048 /* timer count register */ 75215018Syongari#define RL_MISSEDPKT 0x004C /* missed packet counter */ 76215018Syongari#define RL_EECMD 0x0050 /* EEPROM command register */ 77215018Syongari#define RL_CFG0 0x0051 /* config register #0 */ 78215018Syongari#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 84215018Syongari#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 86215018Syongari#define RL_MII 0x005A /* 8129 chip only */ 87215018Syongari#define RL_HALTCLK 0x005B 88215018Syongari#define RL_MULTIINTR 0x005C /* multiple interrupt */ 89215018Syongari#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 91215018Syongari#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 94215018Syongari#define RL_BMCR 0x0062 /* PHY basic mode control */ 95215018Syongari#define RL_BMSR 0x0064 /* PHY basic mode status */ 96215018Syongari#define RL_ANAR 0x0066 /* PHY autoneg advert */ 97215018Syongari#define RL_LPAR 0x0068 /* PHY link partner ability */ 98215018Syongari#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 100215018Syongari#define RL_DISCCNT 0x006C /* disconnect counter */ 101215018Syongari#define RL_FALSECAR 0x006E /* false carrier counter */ 102215018Syongari#define RL_NWAYTST 0x0070 /* NWAY test register */ 103215018Syongari#define RL_RX_ER 0x0072 /* RX_ER counter */ 104215018Syongari#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111215018Syongari#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112215018Syongari#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113215018Syongari#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114215018Syongari#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115215018Syongari#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116215018Syongari#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117215018Syongari#define RL_CFG2 0x0053 118215018Syongari#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119215018Syongari#define RL_TXSTART 0x00D9 /* 8 bits */ 120215018Syongari#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121215018Syongari#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122215018Syongari#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123215018Syongari#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128215018Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 129215018Syongari#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130215018Syongari#define RL_PHYAR 0x0060 131215018Syongari#define RL_TBICSR 0x0064 132215018Syongari#define RL_TBI_ANAR 0x0068 133215018Syongari#define RL_TBI_LPAR 0x006A 134215018Syongari#define RL_GMEDIASTAT 0x006C /* 8 bits */ 135215018Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 136215018Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 137215018Syongari#define RL_PMCH 0x006F /* 8 bits */ 138215018Syongari#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 139215018Syongari#define RL_INTRMOD 0x00E2 /* 16 bits */ 140117388Swpaul 141117388Swpaul/* 14240516Swpaul * TX config register bits 14340516Swpaul */ 144215018Syongari#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145215018Syongari#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146215018Syongari#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147215018Syongari#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148215018Syongari#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149215018Syongari#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150215018Syongari#define RL_TXCFG_HWREV 0x7CC00000 15140516Swpaul 152215018Syongari#define RL_LOOPTEST_OFF 0x00000000 153215018Syongari#define RL_LOOPTEST_ON 0x00020000 154215018Syongari#define RL_LOOPTEST_ON_CPLUS 0x00060000 155119868Swpaul 156159962Swpaul/* Known revision codes. */ 157117388Swpaul 158215018Syongari#define RL_HWREV_8169 0x00000000 159215018Syongari#define RL_HWREV_8169S 0x00800000 160215018Syongari#define RL_HWREV_8110S 0x04000000 161215018Syongari#define RL_HWREV_8169_8110SB 0x10000000 162215018Syongari#define RL_HWREV_8169_8110SC 0x18000000 163215018Syongari#define RL_HWREV_8102EL 0x24800000 164215018Syongari#define RL_HWREV_8102EL_SPIN1 0x24C00000 165215018Syongari#define RL_HWREV_8168D 0x28000000 166215018Syongari#define RL_HWREV_8168DP 0x28800000 167215018Syongari#define RL_HWREV_8168E 0x2C000000 168217498Syongari#define RL_HWREV_8168E_VL 0x2C800000 169215018Syongari#define RL_HWREV_8168_SPIN1 0x30000000 170215018Syongari#define RL_HWREV_8100E 0x30800000 171215018Syongari#define RL_HWREV_8101E 0x34000000 172215018Syongari#define RL_HWREV_8102E 0x34800000 173215018Syongari#define RL_HWREV_8103E 0x34C00000 174215018Syongari#define RL_HWREV_8168_SPIN2 0x38000000 175215018Syongari#define RL_HWREV_8168_SPIN3 0x38400000 176215018Syongari#define RL_HWREV_8168C 0x3C000000 177215018Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 178215018Syongari#define RL_HWREV_8168CP 0x3C800000 179215018Syongari#define RL_HWREV_8139 0x60000000 180215018Syongari#define RL_HWREV_8139A 0x70000000 181215018Syongari#define RL_HWREV_8139AG 0x70800000 182215018Syongari#define RL_HWREV_8139B 0x78000000 183215018Syongari#define RL_HWREV_8130 0x7C000000 184215018Syongari#define RL_HWREV_8139C 0x74000000 185215018Syongari#define RL_HWREV_8139D 0x74400000 186215018Syongari#define RL_HWREV_8139CPLUS 0x74800000 187215018Syongari#define RL_HWREV_8101 0x74C00000 188215018Syongari#define RL_HWREV_8100 0x78800000 189215018Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 190215018Syongari#define RL_HWREV_8169_8110SCE 0x98000000 191159962Swpaul 192215018Syongari#define RL_TXDMA_16BYTES 0x00000000 193215018Syongari#define RL_TXDMA_32BYTES 0x00000100 194215018Syongari#define RL_TXDMA_64BYTES 0x00000200 195215018Syongari#define RL_TXDMA_128BYTES 0x00000300 196215018Syongari#define RL_TXDMA_256BYTES 0x00000400 197215018Syongari#define RL_TXDMA_512BYTES 0x00000500 198215018Syongari#define RL_TXDMA_1024BYTES 0x00000600 199215018Syongari#define RL_TXDMA_2048BYTES 0x00000700 20045633Swpaul 20140516Swpaul/* 20240516Swpaul * Transmit descriptor status register bits. 20340516Swpaul */ 204215018Syongari#define RL_TXSTAT_LENMASK 0x00001FFF 205215018Syongari#define RL_TXSTAT_OWN 0x00002000 206215018Syongari#define RL_TXSTAT_TX_UNDERRUN 0x00004000 207215018Syongari#define RL_TXSTAT_TX_OK 0x00008000 208215018Syongari#define RL_TXSTAT_EARLY_THRESH 0x003F0000 209215018Syongari#define RL_TXSTAT_COLLCNT 0x0F000000 210215018Syongari#define RL_TXSTAT_CARR_HBEAT 0x10000000 211215018Syongari#define RL_TXSTAT_OUTOFWIN 0x20000000 212215018Syongari#define RL_TXSTAT_TXABRT 0x40000000 213215018Syongari#define RL_TXSTAT_CARRLOSS 0x80000000 21440516Swpaul 21540516Swpaul/* 21640516Swpaul * Interrupt status register bits. 21740516Swpaul */ 218215018Syongari#define RL_ISR_RX_OK 0x0001 219215018Syongari#define RL_ISR_RX_ERR 0x0002 220215018Syongari#define RL_ISR_TX_OK 0x0004 221215018Syongari#define RL_ISR_TX_ERR 0x0008 222215018Syongari#define RL_ISR_RX_OVERRUN 0x0010 223215018Syongari#define RL_ISR_PKT_UNDERRUN 0x0020 224215018Syongari#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 225215018Syongari#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 226215018Syongari#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 227215018Syongari#define RL_ISR_SWI 0x0100 /* C+ only */ 228215018Syongari#define RL_ISR_CABLE_LEN_CHGD 0x2000 229215018Syongari#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 230215018Syongari#define RL_ISR_TIMEOUT_EXPIRED 0x4000 231215018Syongari#define RL_ISR_SYSTEM_ERR 0x8000 23240516Swpaul 233215018Syongari#define RL_INTRS \ 23440516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 23540516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 23640516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 23740516Swpaul 238159962Swpaul#ifdef RE_TX_MODERATION 239215018Syongari#define RL_INTRS_CPLUS \ 240119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 241117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 242117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 243159962Swpaul#else 244215018Syongari#define RL_INTRS_CPLUS \ 245159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 246159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 247159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 248159962Swpaul#endif 249117388Swpaul 25040516Swpaul/* 25140516Swpaul * Media status register. (8139 only) 25240516Swpaul */ 253215018Syongari#define RL_MEDIASTAT_RXPAUSE 0x01 254215018Syongari#define RL_MEDIASTAT_TXPAUSE 0x02 255215018Syongari#define RL_MEDIASTAT_LINK 0x04 256215018Syongari#define RL_MEDIASTAT_SPEED10 0x08 257215018Syongari#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 258215018Syongari#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 25940516Swpaul 26040516Swpaul/* 26140516Swpaul * Receive config register. 26240516Swpaul */ 263215018Syongari#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 264215018Syongari#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 265215018Syongari#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 266215018Syongari#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 267215018Syongari#define RL_RXCFG_RX_RUNT 0x00000010 268215018Syongari#define RL_RXCFG_RX_ERRPKT 0x00000020 269215018Syongari#define RL_RXCFG_WRAP 0x00000080 270215018Syongari#define RL_RXCFG_MAXDMA 0x00000700 271215018Syongari#define RL_RXCFG_BUFSZ 0x00001800 272215018Syongari#define RL_RXCFG_FIFOTHRESH 0x0000E000 273215018Syongari#define RL_RXCFG_EARLYTHRESH 0x07000000 27440516Swpaul 275215018Syongari#define RL_RXDMA_16BYTES 0x00000000 276215018Syongari#define RL_RXDMA_32BYTES 0x00000100 277215018Syongari#define RL_RXDMA_64BYTES 0x00000200 278215018Syongari#define RL_RXDMA_128BYTES 0x00000300 279215018Syongari#define RL_RXDMA_256BYTES 0x00000400 280215018Syongari#define RL_RXDMA_512BYTES 0x00000500 281215018Syongari#define RL_RXDMA_1024BYTES 0x00000600 282215018Syongari#define RL_RXDMA_UNLIMITED 0x00000700 28345633Swpaul 284215018Syongari#define RL_RXBUF_8 0x00000000 285215018Syongari#define RL_RXBUF_16 0x00000800 286215018Syongari#define RL_RXBUF_32 0x00001000 287215018Syongari#define RL_RXBUF_64 0x00001800 28840516Swpaul 289215018Syongari#define RL_RXFIFO_16BYTES 0x00000000 290215018Syongari#define RL_RXFIFO_32BYTES 0x00002000 291215018Syongari#define RL_RXFIFO_64BYTES 0x00004000 292215018Syongari#define RL_RXFIFO_128BYTES 0x00006000 293215018Syongari#define RL_RXFIFO_256BYTES 0x00008000 294215018Syongari#define RL_RXFIFO_512BYTES 0x0000A000 295215018Syongari#define RL_RXFIFO_1024BYTES 0x0000C000 296215018Syongari#define RL_RXFIFO_NOTHRESH 0x0000E000 29745633Swpaul 29840516Swpaul/* 29940516Swpaul * Bits in RX status header (included with RX'ed packet 30040516Swpaul * in ring buffer). 30140516Swpaul */ 302215018Syongari#define RL_RXSTAT_RXOK 0x00000001 303215018Syongari#define RL_RXSTAT_ALIGNERR 0x00000002 304215018Syongari#define RL_RXSTAT_CRCERR 0x00000004 305215018Syongari#define RL_RXSTAT_GIANT 0x00000008 306215018Syongari#define RL_RXSTAT_RUNT 0x00000010 307215018Syongari#define RL_RXSTAT_BADSYM 0x00000020 308215018Syongari#define RL_RXSTAT_BROAD 0x00002000 309215018Syongari#define RL_RXSTAT_INDIV 0x00004000 310215018Syongari#define RL_RXSTAT_MULTI 0x00008000 311215018Syongari#define RL_RXSTAT_LENMASK 0xFFFF0000 31240516Swpaul 313215018Syongari#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 31440516Swpaul/* 31540516Swpaul * Command register. 31640516Swpaul */ 317215018Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 318215018Syongari#define RL_CMD_TX_ENB 0x0004 319215018Syongari#define RL_CMD_RX_ENB 0x0008 320215018Syongari#define RL_CMD_RESET 0x0010 321215018Syongari#define RL_CMD_STOPREQ 0x0080 32240516Swpaul 32340516Swpaul/* 324184515Simp * Twister register values. These are completely undocumented and derived 325184515Simp * from public sources. 326184515Simp */ 327215018Syongari#define RL_CSCFG_LINK_OK 0x0400 328215018Syongari#define RL_CSCFG_CHANGE 0x0800 329215018Syongari#define RL_CSCFG_STATUS 0xf000 330215018Syongari#define RL_CSCFG_ROW3 0x7000 331215018Syongari#define RL_CSCFG_ROW2 0x3000 332215018Syongari#define RL_CSCFG_ROW1 0x1000 333215018Syongari#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 334215018Syongari#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 335184515Simp 336215018Syongari#define RL_NWAYTST_RESET 0 337215018Syongari#define RL_NWAYTST_CBL_TEST 0x20 338184515Simp 339215018Syongari#define RL_PARA78 0x78 340215018Syongari#define RL_PARA78_DEF 0x78fa8388 341215018Syongari#define RL_PARA7C 0x7C 342215018Syongari#define RL_PARA7C_DEF 0xcb38de43 343215018Syongari#define RL_PARA7C_RETUNE 0xfb38de03 344184515Simp/* 34540516Swpaul * EEPROM control register 34640516Swpaul */ 347215018Syongari#define RL_EE_DATAOUT 0x01 /* Data out */ 348215018Syongari#define RL_EE_DATAIN 0x02 /* Data in */ 349215018Syongari#define RL_EE_CLK 0x04 /* clock */ 350215018Syongari#define RL_EE_SEL 0x08 /* chip select */ 351215018Syongari#define RL_EE_MODE (0x40|0x80) 35240516Swpaul 353215018Syongari#define RL_EEMODE_OFF 0x00 354215018Syongari#define RL_EEMODE_AUTOLOAD 0x40 355215018Syongari#define RL_EEMODE_PROGRAM 0x80 356215018Syongari#define RL_EEMODE_WRITECFG (0x80|0x40) 35740516Swpaul 35840516Swpaul/* 9346 EEPROM commands */ 359215018Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 360215018Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 361159962Swpaul 362215018Syongari#define RL_9346_WRITE 0x5 363215018Syongari#define RL_9346_READ 0x6 364215018Syongari#define RL_9346_ERASE 0x7 365215018Syongari#define RL_9346_EWEN 0x4 366215018Syongari#define RL_9346_EWEN_ADDR 0x30 367215018Syongari#define RL_9456_EWDS 0x4 368215018Syongari#define RL_9346_EWDS_ADDR 0x00 369159962Swpaul 370215018Syongari#define RL_EECMD_WRITE 0x140 371215018Syongari#define RL_EECMD_READ_6BIT 0x180 372215018Syongari#define RL_EECMD_READ_8BIT 0x600 373215018Syongari#define RL_EECMD_ERASE 0x1c0 37440516Swpaul 375215018Syongari#define RL_EE_ID 0x00 376215018Syongari#define RL_EE_PCI_VID 0x01 377215018Syongari#define RL_EE_PCI_DID 0x02 37840516Swpaul/* Location of station address inside EEPROM */ 379215018Syongari#define RL_EE_EADDR 0x07 38040516Swpaul 38140516Swpaul/* 38240516Swpaul * MII register (8129 only) 38340516Swpaul */ 384215018Syongari#define RL_MII_CLK 0x01 385215018Syongari#define RL_MII_DATAIN 0x02 386215018Syongari#define RL_MII_DATAOUT 0x04 387215018Syongari#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 38840516Swpaul 38940516Swpaul/* 39040516Swpaul * Config 0 register 39140516Swpaul */ 392215018Syongari#define RL_CFG0_ROM0 0x01 393215018Syongari#define RL_CFG0_ROM1 0x02 394215018Syongari#define RL_CFG0_ROM2 0x04 395215018Syongari#define RL_CFG0_PL0 0x08 396215018Syongari#define RL_CFG0_PL1 0x10 397215018Syongari#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 398215018Syongari#define RL_CFG0_PCS 0x40 399215018Syongari#define RL_CFG0_SCR 0x80 40040516Swpaul 40140516Swpaul/* 40240516Swpaul * Config 1 register 40340516Swpaul */ 404215018Syongari#define RL_CFG1_PWRDWN 0x01 405215019Syongari#define RL_CFG1_PME 0x01 406215018Syongari#define RL_CFG1_SLEEP 0x02 407215018Syongari#define RL_CFG1_VPDEN 0x02 408215018Syongari#define RL_CFG1_IOMAP 0x04 409215018Syongari#define RL_CFG1_MEMMAP 0x08 410215018Syongari#define RL_CFG1_RSVD 0x10 411176754Syongari#define RL_CFG1_LWACT 0x10 412215018Syongari#define RL_CFG1_DRVLOAD 0x20 413215018Syongari#define RL_CFG1_LED0 0x40 414215018Syongari#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 415215018Syongari#define RL_CFG1_LED1 0x80 41640516Swpaul 41740516Swpaul/* 418176754Syongari * Config 2 register 419176754Syongari */ 420176754Syongari#define RL_CFG2_PCI33MHZ 0x00 421176754Syongari#define RL_CFG2_PCI66MHZ 0x01 422176754Syongari#define RL_CFG2_PCI64BIT 0x08 423176754Syongari#define RL_CFG2_AUXPWR 0x10 424177522Syongari#define RL_CFG2_MSI 0x20 425176754Syongari 426176754Syongari/* 427176754Syongari * Config 3 register 428176754Syongari */ 429176754Syongari#define RL_CFG3_GRANTSEL 0x80 430176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 431176754Syongari#define RL_CFG3_WOL_LINK 0x10 432217499Syongari#define RL_CFG3_JUMBO_EN0 0x04 /* RTL8168C or later. */ 433176754Syongari#define RL_CFG3_FAST_B2B 0x01 434176754Syongari 435176754Syongari/* 436176754Syongari * Config 4 register 437176754Syongari */ 438176754Syongari#define RL_CFG4_LWPTN 0x04 439176754Syongari#define RL_CFG4_LWPME 0x10 440217499Syongari#define RL_CFG4_JUMBO_EN1 0x02 /* RTL8168C or later. */ 441176754Syongari 442176754Syongari/* 443176754Syongari * Config 5 register 444176754Syongari */ 445176754Syongari#define RL_CFG5_WOL_BCAST 0x40 446176754Syongari#define RL_CFG5_WOL_MCAST 0x20 447176754Syongari#define RL_CFG5_WOL_UCAST 0x10 448176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 449176754Syongari#define RL_CFG5_PME_STS 0x01 450176754Syongari 451176754Syongari/* 452117388Swpaul * 8139C+ register definitions 453117388Swpaul */ 454117388Swpaul 455117388Swpaul/* RL_DUMPSTATS_LO register */ 456117388Swpaul 457215018Syongari#define RL_DUMPSTATS_START 0x00000008 458117388Swpaul 459117388Swpaul/* Transmit start register */ 460117388Swpaul 461215018Syongari#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 462215018Syongari#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 463215018Syongari#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 464117388Swpaul 465120043Swpaul/* 466120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 467120043Swpaul */ 468215018Syongari#define RL_CFG2_BUSFREQ 0x07 469215018Syongari#define RL_CFG2_BUSWIDTH 0x08 470215018Syongari#define RL_CFG2_AUXPWRSTS 0x10 471120043Swpaul 472215018Syongari#define RL_BUSFREQ_33MHZ 0x00 473215018Syongari#define RL_BUSFREQ_66MHZ 0x01 474215019Syongari 475215018Syongari#define RL_BUSWIDTH_32BITS 0x00 476215018Syongari#define RL_BUSWIDTH_64BITS 0x08 477120043Swpaul 478117388Swpaul/* C+ mode command register */ 479117388Swpaul 480215018Syongari#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 481215018Syongari#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 482215018Syongari#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 483215018Syongari#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 484215018Syongari#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 485215018Syongari#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 486180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 487180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 488180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 489180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 490180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 491180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 492180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 493180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 494180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 495117388Swpaul 496117388Swpaul/* C+ early transmit threshold */ 497117388Swpaul 498215019Syongari#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 499117388Swpaul 500117388Swpaul/* 501117388Swpaul * Gigabit PHY access register (8169 only) 502117388Swpaul */ 503117388Swpaul 504215018Syongari#define RL_PHYAR_PHYDATA 0x0000FFFF 505215018Syongari#define RL_PHYAR_PHYREG 0x001F0000 506215018Syongari#define RL_PHYAR_BUSY 0x80000000 507117388Swpaul 508117388Swpaul/* 509117388Swpaul * Gigabit media status (8169 only) 510117388Swpaul */ 511215018Syongari#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 512215018Syongari#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 513215018Syongari#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 514215018Syongari#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 515215018Syongari#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 516215018Syongari#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 517215018Syongari#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 518215018Syongari#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 519117388Swpaul 520117388Swpaul/* 52140516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 52240516Swpaul * Instead, there are only four register sets, each or which represents 52340516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 52440516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 52540516Swpaul * the registers so the chip knows where they are. 52640516Swpaul * 52740516Swpaul * We can sort of kludge together the same kind of buffer management 52840516Swpaul * used in previous drivers, but we have to do buffer copies almost all 52940516Swpaul * the time, so it doesn't really buy us much. 53040516Swpaul * 53140516Swpaul * For reception, there's just one large buffer where the chip stores 53240516Swpaul * all received packets. 53340516Swpaul */ 53440516Swpaul 535215018Syongari#define RL_RX_BUF_SZ RL_RXBUF_64 536215018Syongari#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 537215018Syongari#define RL_TX_LIST_CNT 4 538215018Syongari#define RL_MIN_FRAMELEN 60 539184240Syongari#define RL_TX_8139_BUF_ALIGN 4 540184240Syongari#define RL_RX_8139_BUF_ALIGN 8 541184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 542184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 543215019Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 544215018Syongari#define RL_TXTHRESH(x) ((x) << 11) 545215018Syongari#define RL_TX_THRESH_INIT 96 546215018Syongari#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 547215018Syongari#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 548215018Syongari#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 54940516Swpaul 550215018Syongari#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 551215018Syongari#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 55240516Swpaul 553215018Syongari#define RL_ETHER_ALIGN 2 55448028Swpaul 555177771Syongari/* 556177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 557177771Syongari */ 558177771Syongari#define RL_IP4CSUMTX_MINLEN 28 559177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 560177771Syongari 56140516Swpaulstruct rl_chain_data { 562131605Sbms uint16_t cur_rx; 563131605Sbms uint8_t *rl_rx_buf; 564131605Sbms uint8_t *rl_rx_buf_ptr; 56540516Swpaul 56645633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 56781713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 568184240Syongari bus_dma_tag_t rl_tx_tag; 569184240Syongari bus_dma_tag_t rl_rx_tag; 570184240Syongari bus_dmamap_t rl_rx_dmamap; 571184240Syongari bus_addr_t rl_rx_buf_paddr; 572131605Sbms uint8_t last_tx; 573131605Sbms uint8_t cur_tx; 57440516Swpaul}; 57540516Swpaul 576215018Syongari#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 577215018Syongari#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 578215018Syongari#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 579215018Syongari#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 580215018Syongari#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 581215018Syongari#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 582215018Syongari#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 583215018Syongari#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 584215018Syongari#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 58545633Swpaul 58640516Swpaulstruct rl_type { 587131605Sbms uint16_t rl_vid; 588131605Sbms uint16_t rl_did; 589117388Swpaul int rl_basetype; 59040516Swpaul char *rl_name; 59140516Swpaul}; 59240516Swpaul 593117388Swpaulstruct rl_hwrev { 594131605Sbms uint32_t rl_rev; 595117388Swpaul int rl_type; 596117388Swpaul char *rl_desc; 597217499Syongari int rl_max_mtu; 598117388Swpaul}; 599117388Swpaul 60040516Swpaulstruct rl_mii_frame { 601131605Sbms uint8_t mii_stdelim; 602131605Sbms uint8_t mii_opcode; 603131605Sbms uint8_t mii_phyaddr; 604131605Sbms uint8_t mii_regaddr; 605131605Sbms uint8_t mii_turnaround; 606131605Sbms uint16_t mii_data; 60740516Swpaul}; 60840516Swpaul 60940516Swpaul/* 61040516Swpaul * MII constants 61140516Swpaul */ 612215018Syongari#define RL_MII_STARTDELIM 0x01 613215018Syongari#define RL_MII_READOP 0x02 614215018Syongari#define RL_MII_WRITEOP 0x01 615215018Syongari#define RL_MII_TURNAROUND 0x02 61640516Swpaul 617215018Syongari#define RL_8129 1 618215018Syongari#define RL_8139 2 619215018Syongari#define RL_8139CPLUS 3 620215018Syongari#define RL_8169 4 62140516Swpaul 622215018Syongari#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 623117388Swpaul (x)->rl_type == RL_8169) 624117388Swpaul 625117388Swpaul/* 626117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 627117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 628117388Swpaul * must be allocated in contiguous blocks that are aligned on a 629117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 630117388Swpaul */ 631117388Swpaul 632117388Swpaul/* 633117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 634117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 635117388Swpaul * the checksum offload bits are disabled. The structure layout is 636117388Swpaul * the same for RX and TX descriptors 637117388Swpaul */ 638117388Swpaul 639117388Swpaulstruct rl_desc { 640131605Sbms uint32_t rl_cmdstat; 641131605Sbms uint32_t rl_vlanctl; 642131605Sbms uint32_t rl_bufaddr_lo; 643131605Sbms uint32_t rl_bufaddr_hi; 644117388Swpaul}; 645117388Swpaul 646215018Syongari#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 647215018Syongari#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 648215018Syongari#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 649215018Syongari#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 650215018Syongari#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 651215018Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 652215018Syongari#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 653215018Syongari#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 654215018Syongari#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 655215018Syongari#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 656215018Syongari#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 657117388Swpaul 658215018Syongari#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 659215018Syongari#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 660180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 661180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 662215019Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 663215019Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 664217246Syongari#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 665217246Syongari#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 666117388Swpaul 667117388Swpaul/* 668117388Swpaul * Error bits are valid only on the last descriptor of a frame 669117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 670117388Swpaul */ 671117388Swpaul 672215018Syongari#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 673215018Syongari#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 674215018Syongari#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 675215018Syongari#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 676215018Syongari#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 677215018Syongari#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 678215018Syongari#define RL_TDESC_STAT_OWN 0x80000000 679117388Swpaul 680117388Swpaul/* 681117388Swpaul * RX descriptor cmd/vlan definitions 682117388Swpaul */ 683117388Swpaul 684215018Syongari#define RL_RDESC_CMD_EOR 0x40000000 685215018Syongari#define RL_RDESC_CMD_OWN 0x80000000 686215018Syongari#define RL_RDESC_CMD_BUFLEN 0x00001FFF 687117388Swpaul 688215018Syongari#define RL_RDESC_STAT_OWN 0x80000000 689215018Syongari#define RL_RDESC_STAT_EOR 0x40000000 690215018Syongari#define RL_RDESC_STAT_SOF 0x20000000 691215018Syongari#define RL_RDESC_STAT_EOF 0x10000000 692215018Syongari#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 693215018Syongari#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 694215018Syongari#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 695215018Syongari#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 696215018Syongari#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 697215018Syongari#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 698215018Syongari#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 699215018Syongari#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 700215018Syongari#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 701215018Syongari#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 702215018Syongari#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 703180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 704180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 705215018Syongari#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 706215018Syongari#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 707215018Syongari#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 708215018Syongari#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 709215018Syongari#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 710215018Syongari#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 711135896Sjmg RL_RDESC_STAT_CRCERR) 712117388Swpaul 713215018Syongari#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 714117388Swpaul (rl_vlandata valid)*/ 715215018Syongari#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 716180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 717180176Syongari#define RL_RDESC_IPV6 0x80000000 718180176Syongari#define RL_RDESC_IPV4 0x40000000 719117388Swpaul 720215018Syongari#define RL_PROTOID_NONIP 0x00000000 721215018Syongari#define RL_PROTOID_TCPIP 0x00010000 722215018Syongari#define RL_PROTOID_UDPIP 0x00020000 723215018Syongari#define RL_PROTOID_IP 0x00030000 724215018Syongari#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 725117388Swpaul RL_PROTOID_TCPIP) 726215018Syongari#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 727117388Swpaul RL_PROTOID_UDPIP) 728117388Swpaul 729117388Swpaul/* 730117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 731117388Swpaul */ 732117388Swpaulstruct rl_stats { 733214844Syongari uint64_t rl_tx_pkts; 734214844Syongari uint64_t rl_rx_pkts; 735214844Syongari uint64_t rl_tx_errs; 736214844Syongari uint32_t rl_rx_errs; 737131605Sbms uint16_t rl_missed_pkts; 738131605Sbms uint16_t rl_rx_framealign_errs; 739131605Sbms uint32_t rl_tx_onecoll; 740131605Sbms uint32_t rl_tx_multicolls; 741214844Syongari uint64_t rl_rx_ucasts; 742214844Syongari uint64_t rl_rx_bcasts; 743131605Sbms uint32_t rl_rx_mcasts; 744131605Sbms uint16_t rl_tx_aborts; 745131605Sbms uint16_t rl_rx_underruns; 746117388Swpaul}; 747117388Swpaul 748135467Sjmg/* 749135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 750135467Sjmg * 751175337Syongari * 8139C+ 752175337Syongari * Number of descriptors supported : up to 64 753175337Syongari * Descriptor alignment : 256 bytes 754175337Syongari * Tx buffer : At least 4 bytes in length. 755175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 756215019Syongari * 757175337Syongari * 8169 758175337Syongari * Number of descriptors supported : up to 1024 759175337Syongari * Descriptor alignment : 256 bytes 760175337Syongari * Tx buffer : At least 4 bytes in length. 761175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 762135467Sjmg */ 763164460Syongari#ifndef __NO_STRICT_ALIGNMENT 764215018Syongari#define RE_FIXUP_RX 1 765135896Sjmg#endif 766135896Sjmg 767215018Syongari#define RL_8169_TX_DESC_CNT 256 768215018Syongari#define RL_8169_RX_DESC_CNT 256 769215018Syongari#define RL_8139_TX_DESC_CNT 64 770215018Syongari#define RL_8139_RX_DESC_CNT 64 771215018Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 772215018Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 773217499Syongari#define RL_RX_JUMBO_DESC_CNT RL_RX_DESC_CNT 774175337Syongari#define RL_NTXSEGS 32 775159962Swpaul 776215018Syongari#define RL_RING_ALIGN 256 777215018Syongari#define RL_DUMP_ALIGN 64 778215018Syongari#define RL_IFQ_MAXLEN 512 779215018Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 780215018Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 781215018Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 782215018Syongari#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 783215018Syongari#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 784215018Syongari#define RL_PKTSZ(x) ((x)/* >> 3*/) 785135896Sjmg#ifdef RE_FIXUP_RX 786215018Syongari#define RE_ETHER_ALIGN sizeof(uint64_t) 787215018Syongari#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 788135896Sjmg#else 789215018Syongari#define RE_ETHER_ALIGN 0 790215018Syongari#define RE_RX_DESC_BUFLEN MCLBYTES 791135896Sjmg#endif 792117388Swpaul 793188474Syongari#define RL_MSI_MESSAGES 1 794171560Syongari 795215018Syongari#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 796215018Syongari#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 797118712Swpaul 798181270Syongari/* 799181270Syongari * The number of bits reserved for MSS in RealTek controllers is 800181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 801181270Syongari * as upper stack should not generate TCP segments with MSS greater 802181270Syongari * than the limit. 803181270Syongari */ 804181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 805181270Syongari 806135896Sjmg/* see comment in dev/re/if_re.c */ 807215018Syongari#define RL_JUMBO_FRAMELEN 7440 808217499Syongari#define RL_JUMBO_MTU \ 809217499Syongari (RL_JUMBO_FRAMELEN-ETHER_VLAN_ENCAP_LEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 810217499Syongari#define RL_JUMBO_MTU_6K \ 811217499Syongari ((6 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 812217499Syongari#define RL_JUMBO_MTU_9K \ 813217499Syongari ((9 * 1024) - ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 814217499Syongari#define RL_MTU \ 815176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 816119868Swpaul 817175337Syongaristruct rl_txdesc { 818175337Syongari struct mbuf *tx_m; 819175337Syongari bus_dmamap_t tx_dmamap; 820175337Syongari}; 821117388Swpaul 822175337Syongaristruct rl_rxdesc { 823175337Syongari struct mbuf *rx_m; 824175337Syongari bus_dmamap_t rx_dmamap; 825175337Syongari bus_size_t rx_size; 826117388Swpaul}; 827117388Swpaul 828117388Swpaulstruct rl_list_data { 829175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 830175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 831217499Syongari struct rl_rxdesc rl_jrx_desc[RL_RX_JUMBO_DESC_CNT]; 832175337Syongari int rl_tx_desc_cnt; 833175337Syongari int rl_rx_desc_cnt; 834117388Swpaul int rl_tx_prodidx; 835117388Swpaul int rl_rx_prodidx; 836117388Swpaul int rl_tx_considx; 837117388Swpaul int rl_tx_free; 838175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 839175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 840217499Syongari bus_dma_tag_t rl_jrx_mtag; /* mbuf RX mapping tag */ 841175337Syongari bus_dmamap_t rl_rx_sparemap; 842217499Syongari bus_dmamap_t rl_jrx_sparemap; 843117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 844117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 845117388Swpaul struct rl_stats *rl_stats; 846118712Swpaul bus_addr_t rl_stats_addr; 847117388Swpaul bus_dma_tag_t rl_rx_list_tag; 848117388Swpaul bus_dmamap_t rl_rx_list_map; 849117388Swpaul struct rl_desc *rl_rx_list; 850118712Swpaul bus_addr_t rl_rx_list_addr; 851117388Swpaul bus_dma_tag_t rl_tx_list_tag; 852117388Swpaul bus_dmamap_t rl_tx_list_map; 853117388Swpaul struct rl_desc *rl_tx_list; 854118712Swpaul bus_addr_t rl_tx_list_addr; 855117388Swpaul}; 856117388Swpaul 857184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 858184515Simp 85940516Swpaulstruct rl_softc { 860147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 86141569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 86241569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 863159962Swpaul device_t rl_dev; 86450703Swpaul struct resource *rl_res; 865180169Syongari int rl_res_id; 866180169Syongari int rl_res_type; 867171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 868171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 86950703Swpaul device_t rl_miibus; 87081713Swpaul bus_dma_tag_t rl_parent_tag; 871131605Sbms uint8_t rl_type; 872217499Syongari struct rl_hwrev *rl_hwrev; 87367931Swpaul int rl_eecmd_read; 874159962Swpaul int rl_eewidth; 87552426Swpaul int rl_txthresh; 87640516Swpaul struct rl_chain_data rl_cdata; 877117388Swpaul struct rl_list_data rl_ldata; 878150720Sjhb struct callout rl_stat_callout; 879164811Sru int rl_watchdog_timer; 88067087Swpaul struct mtx rl_mtx; 881119868Swpaul struct mbuf *rl_head; 882119868Swpaul struct mbuf *rl_tail; 883131605Sbms uint32_t rl_rxlenmask; 884119868Swpaul int rl_testmode; 885168828Syongari int rl_if_flags; 886184559Simp int rl_twister_enable; 887184515Simp enum rl_twist rl_twister; 888184515Simp int rl_twist_row; 889184515Simp int rl_twist_col; 89086822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 89194883Sluigi#ifdef DEVICE_POLLING 89294883Sluigi int rxcycles; 89394883Sluigi#endif 894159962Swpaul 895159962Swpaul struct task rl_txtask; 896159962Swpaul struct task rl_inttask; 897159962Swpaul 898159962Swpaul int rl_txstart; 899180171Syongari uint32_t rl_flags; 900180171Syongari#define RL_FLAG_MSI 0x0001 901191301Syongari#define RL_FLAG_AUTOPAD 0x0002 902206433Syongari#define RL_FLAG_PHYWAKE_PM 0x0004 903180171Syongari#define RL_FLAG_PHYWAKE 0x0008 904217499Syongari#define RL_FLAG_JUMBOV2 0x0010 905180176Syongari#define RL_FLAG_PAR 0x0020 906180176Syongari#define RL_FLAG_DESCV2 0x0040 907180176Syongari#define RL_FLAG_MACSTAT 0x0080 908185753Syongari#define RL_FLAG_FASTETHER 0x0100 909185900Syongari#define RL_FLAG_CMDSTOP 0x0200 910187483Sjkim#define RL_FLAG_MACRESET 0x0400 911185903Syongari#define RL_FLAG_WOLRXENB 0x1000 912186210Syongari#define RL_FLAG_MACSLEEP 0x2000 913186214Syongari#define RL_FLAG_PCIE 0x4000 914180171Syongari#define RL_FLAG_LINK 0x8000 91540516Swpaul}; 91640516Swpaul 91772200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 91872200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 919122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 92067087Swpaul 92140516Swpaul/* 92240516Swpaul * register space access macros 92340516Swpaul */ 924215018Syongari#define CSR_WRITE_STREAM_4(sc, reg, val) \ 925119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 926215018Syongari#define CSR_WRITE_4(sc, reg, val) \ 92741569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 928215018Syongari#define CSR_WRITE_2(sc, reg, val) \ 92941569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 930215018Syongari#define CSR_WRITE_1(sc, reg, val) \ 93141569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 93240516Swpaul 933215018Syongari#define CSR_READ_4(sc, reg) \ 93441569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 935215018Syongari#define CSR_READ_2(sc, reg) \ 93641569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 937215018Syongari#define CSR_READ_1(sc, reg) \ 93841569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 93940516Swpaul 940215018Syongari#define CSR_SETBIT_1(sc, offset, val) \ 941159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 942159962Swpaul 943215018Syongari#define CSR_CLRBIT_1(sc, offset, val) \ 944159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 945159962Swpaul 946215018Syongari#define CSR_SETBIT_2(sc, offset, val) \ 947159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 948159962Swpaul 949215018Syongari#define CSR_CLRBIT_2(sc, offset, val) \ 950159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 951159962Swpaul 952215018Syongari#define CSR_SETBIT_4(sc, offset, val) \ 953159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 954159962Swpaul 955215018Syongari#define CSR_CLRBIT_4(sc, offset, val) \ 956159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 957159962Swpaul 958215018Syongari#define RL_TIMEOUT 1000 959215018Syongari#define RL_PHY_TIMEOUT 2000 96040516Swpaul 96140516Swpaul/* 96240516Swpaul * General constants that are fun to know. 96340516Swpaul * 96440516Swpaul * RealTek PCI vendor ID 96540516Swpaul */ 96640516Swpaul#define RT_VENDORID 0x10EC 96740516Swpaul 96840516Swpaul/* 96940516Swpaul * RealTek chip device IDs. 97040516Swpaul */ 971215018Syongari#define RT_DEVICEID_8139D 0x8039 97240516Swpaul#define RT_DEVICEID_8129 0x8129 973215018Syongari#define RT_DEVICEID_8101E 0x8136 97467771Swpaul#define RT_DEVICEID_8138 0x8138 97540516Swpaul#define RT_DEVICEID_8139 0x8139 976215018Syongari#define RT_DEVICEID_8169SC 0x8167 977215018Syongari#define RT_DEVICEID_8168 0x8168 978215018Syongari#define RT_DEVICEID_8169 0x8169 979215018Syongari#define RT_DEVICEID_8100 0x8100 98040516Swpaul 981215018Syongari#define RT_REVID_8139CPLUS 0x20 982117388Swpaul 98340516Swpaul/* 98444238Swpaul * Accton PCI vendor ID 98544238Swpaul */ 986215018Syongari#define ACCTON_VENDORID 0x1113 98744238Swpaul 98844238Swpaul/* 98941243Swpaul * Accton MPX 5030/5038 device ID. 99041243Swpaul */ 991215018Syongari#define ACCTON_DEVICEID_5030 0x1211 99241243Swpaul 99341243Swpaul/* 99494400Swpaul * Nortel PCI vendor ID 99594400Swpaul */ 996215018Syongari#define NORTEL_VENDORID 0x126C 99794400Swpaul 99894400Swpaul/* 99944238Swpaul * Delta Electronics Vendor ID. 100044238Swpaul */ 1001215018Syongari#define DELTA_VENDORID 0x1500 100244238Swpaul 100344238Swpaul/* 100444238Swpaul * Delta device IDs. 100544238Swpaul */ 1006215018Syongari#define DELTA_DEVICEID_8139 0x1360 100744238Swpaul 100844238Swpaul/* 100944238Swpaul * Addtron vendor ID. 101044238Swpaul */ 1011215018Syongari#define ADDTRON_VENDORID 0x4033 101244238Swpaul 101344238Swpaul/* 101444238Swpaul * Addtron device IDs. 101544238Swpaul */ 1016215018Syongari#define ADDTRON_DEVICEID_8139 0x1360 101744238Swpaul 101844238Swpaul/* 101972813Swpaul * D-Link vendor ID. 102072813Swpaul */ 1021215018Syongari#define DLINK_VENDORID 0x1186 102272813Swpaul 102372813Swpaul/* 102472813Swpaul * D-Link DFE-530TX+ device ID 102572813Swpaul */ 1026215018Syongari#define DLINK_DEVICEID_530TXPLUS 0x1300 102772813Swpaul 102872813Swpaul/* 1029148722Stobez * D-Link DFE-5280T device ID 1030148722Stobez */ 1031215018Syongari#define DLINK_DEVICEID_528T 0x4300 1032148722Stobez 1033148722Stobez/* 103496112Sjhb * D-Link DFE-690TXD device ID 103596112Sjhb */ 1036215018Syongari#define DLINK_DEVICEID_690TXD 0x1340 103796112Sjhb 103896112Sjhb/* 1039103020Siwasaki * Corega K.K vendor ID 1040103020Siwasaki */ 1041215018Syongari#define COREGA_VENDORID 0x1259 1042103020Siwasaki 1043103020Siwasaki/* 1044109095Ssanpei * Corega FEther CB-TXD device ID 1045103020Siwasaki */ 1046215018Syongari#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1047103020Siwasaki 1048103020Siwasaki/* 1049109095Ssanpei * Corega FEtherII CB-TXD device ID 1050109095Ssanpei */ 1051215018Syongari#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1052109095Ssanpei 1053111381Sdan/* 1054134433Ssanpei * Corega CG-LAPCIGT device ID 1055134433Ssanpei */ 1056215018Syongari#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1057134433Ssanpei 1058134433Ssanpei/* 1059151341Sjhb * Linksys vendor ID 1060151341Sjhb */ 1061215018Syongari#define LINKSYS_VENDORID 0x1737 1062151341Sjhb 1063151341Sjhb/* 1064151341Sjhb * Linksys EG1032 device ID 1065151341Sjhb */ 1066215018Syongari#define LINKSYS_DEVICEID_EG1032 0x1032 1067151341Sjhb 1068151341Sjhb/* 1069151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1070151341Sjhb */ 1071215018Syongari#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1072151341Sjhb 1073151341Sjhb/* 1074111381Sdan * Peppercon vendor ID 1075111381Sdan */ 1076215018Syongari#define PEPPERCON_VENDORID 0x1743 1077109095Ssanpei 1078111381Sdan/* 1079111381Sdan * Peppercon ROL-F device ID 1080111381Sdan */ 1081215018Syongari#define PEPPERCON_DEVICEID_ROLF 0x8139 1082109095Ssanpei 1083109095Ssanpei/* 1084112379Ssanpei * Planex Communications, Inc. vendor ID 1085112379Ssanpei */ 1086215018Syongari#define PLANEX_VENDORID 0x14ea 1087112379Ssanpei 1088112379Ssanpei/* 1089173948Sremko * Planex FNW-3603-TX device ID 1090173948Sremko */ 1091215018Syongari#define PLANEX_DEVICEID_FNW3603TX 0xab06 1092173948Sremko 1093173948Sremko/* 1094112379Ssanpei * Planex FNW-3800-TX device ID 1095112379Ssanpei */ 1096215018Syongari#define PLANEX_DEVICEID_FNW3800TX 0xab07 1097112379Ssanpei 1098112379Ssanpei/* 1099117388Swpaul * LevelOne vendor ID 1100117388Swpaul */ 1101215018Syongari#define LEVEL1_VENDORID 0x018A 1102117388Swpaul 1103117388Swpaul/* 1104117388Swpaul * LevelOne FPC-0106TX devide ID 1105117388Swpaul */ 1106215018Syongari#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1107117388Swpaul 1108117388Swpaul/* 1109117388Swpaul * Compaq vendor ID 1110117388Swpaul */ 1111215018Syongari#define CP_VENDORID 0x021B 1112117388Swpaul 1113117388Swpaul/* 1114117388Swpaul * Edimax vendor ID 1115117388Swpaul */ 1116215018Syongari#define EDIMAX_VENDORID 0x13D1 1117117388Swpaul 1118117388Swpaul/* 1119117388Swpaul * Edimax EP-4103DL cardbus device ID 1120117388Swpaul */ 1121215018Syongari#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1122117388Swpaul 1123160883Swpaul/* US Robotics vendor ID */ 1124160883Swpaul 1125215018Syongari#define USR_VENDORID 0x16EC 1126160883Swpaul 1127160883Swpaul/* US Robotics 997902 device ID */ 1128160883Swpaul 1129215018Syongari#define USR_DEVICEID_997902 0x0116 1130