if_rlreg.h revision 217246
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 217246 2011-01-10 23:28:46Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79120043Swpaul#define RL_CFG2 0x0053 /* config register #2 */ 8040516Swpaul#define RL_CFG3 0x0054 /* config register #3 */ 8140516Swpaul#define RL_CFG4 0x0055 /* config register #4 */ 8240516Swpaul#define RL_CFG5 0x0056 /* config register #5 */ 8340516Swpaul /* 0057 reserved */ 8440516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 8640516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8740516Swpaul#define RL_HALTCLK 0x005B 8840516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8940516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 9140516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 9440516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9540516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9640516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9740516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9840516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 10040516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 10140516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 102117388Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 103117388Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 104117388Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 105117388Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113120043Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117117388Swpaul#define RL_CFG2 0x0053 118117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 12040516Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 12140516Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 124118586Swpaul 125117388Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128117388Swpaul#define RL_GTXSTART 0x0038 /* 8 bits */ 129117388Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 130117388Swpaul#define RL_PHYAR 0x0060 131117388Swpaul#define RL_TBICSR 0x0064 132117388Swpaul#define RL_TBI_ANAR 0x0068 133117388Swpaul#define RL_TBI_LPAR 0x006A 13440516Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 13540516Swpaul#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 13640516Swpaul#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 13745633Swpaul#define RL_PMCH 0x006F /* 8 bits */ 13840516Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 13945633Swpaul#define RL_INTRMOD 0x00E2 /* 16 bits */ 140119868Swpaul 14145633Swpaul/* 142117388Swpaul * TX config register bits 14340516Swpaul */ 144119868Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 145119868Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 146119981Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 147119868Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 148159962Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 149117388Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 150160843Swpaul#define RL_TXCFG_HWREV 0x7CC00000 151160843Swpaul 152160843Swpaul#define RL_LOOPTEST_OFF 0x00000000 153160843Swpaul#define RL_LOOPTEST_ON 0x00020000 154160843Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 155160843Swpaul 156160843Swpaul/* Known revision codes. */ 157160843Swpaul 158160843Swpaul#define RL_HWREV_8169 0x00000000 159160843Swpaul#define RL_HWREV_8169S 0x00800000 160160843Swpaul#define RL_HWREV_8110S 0x04000000 161160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 162160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 163160843Swpaul#define RL_HWREV_8102EL 0x24800000 164160843Swpaul#define RL_HWREV_8102EL_SPIN1 0x24C00000 165160843Swpaul#define RL_HWREV_8168D 0x28000000 166160843Swpaul#define RL_HWREV_8168DP 0x28800000 167160843Swpaul#define RL_HWREV_8168E 0x2C000000 168160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 169159962Swpaul#define RL_HWREV_8100E 0x30800000 17045633Swpaul#define RL_HWREV_8101E 0x34000000 17145633Swpaul#define RL_HWREV_8102E 0x34800000 17245633Swpaul#define RL_HWREV_8103E 0x34C00000 17345633Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 17445633Swpaul#define RL_HWREV_8168_SPIN3 0x38400000 17545633Swpaul#define RL_HWREV_8168C 0x3C000000 17645633Swpaul#define RL_HWREV_8168C_SPIN2 0x3C400000 17745633Swpaul#define RL_HWREV_8168CP 0x3C800000 17845633Swpaul#define RL_HWREV_8139 0x60000000 17940516Swpaul#define RL_HWREV_8139A 0x70000000 18040516Swpaul#define RL_HWREV_8139AG 0x70800000 18140516Swpaul#define RL_HWREV_8139B 0x78000000 18240516Swpaul#define RL_HWREV_8130 0x7C000000 18340516Swpaul#define RL_HWREV_8139C 0x74000000 18440516Swpaul#define RL_HWREV_8139D 0x74400000 18540516Swpaul#define RL_HWREV_8139CPLUS 0x74800000 18640516Swpaul#define RL_HWREV_8101 0x74C00000 18740516Swpaul#define RL_HWREV_8100 0x78800000 18840516Swpaul#define RL_HWREV_8169_8110SBL 0x7CC00000 18940516Swpaul#define RL_HWREV_8169_8110SCE 0x98000000 19040516Swpaul 19140516Swpaul#define RL_TXDMA_16BYTES 0x00000000 19240516Swpaul#define RL_TXDMA_32BYTES 0x00000100 19340516Swpaul#define RL_TXDMA_64BYTES 0x00000200 19440516Swpaul#define RL_TXDMA_128BYTES 0x00000300 19540516Swpaul#define RL_TXDMA_256BYTES 0x00000400 19640516Swpaul#define RL_TXDMA_512BYTES 0x00000500 19740516Swpaul#define RL_TXDMA_1024BYTES 0x00000600 19840516Swpaul#define RL_TXDMA_2048BYTES 0x00000700 19940516Swpaul 20040516Swpaul/* 20140516Swpaul * Transmit descriptor status register bits. 202119868Swpaul */ 20340516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 204117388Swpaul#define RL_TXSTAT_OWN 0x00002000 205117388Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 206117388Swpaul#define RL_TXSTAT_TX_OK 0x00008000 20740516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 208117388Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 20940516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 21040516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 21140516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 21240516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 21340516Swpaul 21440516Swpaul/* 21540516Swpaul * Interrupt status register bits. 216159962Swpaul */ 217117388Swpaul#define RL_ISR_RX_OK 0x0001 218119868Swpaul#define RL_ISR_RX_ERR 0x0002 219117388Swpaul#define RL_ISR_TX_OK 0x0004 220117388Swpaul#define RL_ISR_TX_ERR 0x0008 221159962Swpaul#define RL_ISR_RX_OVERRUN 0x0010 222159962Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 223159962Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 224159962Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 225159962Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 226159962Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 227117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 22840516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 22940516Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 23040516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 23140516Swpaul 23240516Swpaul#define RL_INTRS \ 23340516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 23440516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 23540516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 23640516Swpaul 23740516Swpaul#ifdef RE_TX_MODERATION 23840516Swpaul#define RL_INTRS_CPLUS \ 23940516Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 24040516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 24140516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 24240516Swpaul#else 24340516Swpaul#define RL_INTRS_CPLUS \ 24440516Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 24540516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 24640516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 24740516Swpaul#endif 24845633Swpaul 24945633Swpaul/* 25045633Swpaul * Media status register. (8139 only) 25145633Swpaul */ 25240516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 25345633Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 25445633Swpaul#define RL_MEDIASTAT_LINK 0x04 25545633Swpaul#define RL_MEDIASTAT_SPEED10 0x08 25645633Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 25745633Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 25845633Swpaul 25945633Swpaul/* 26045633Swpaul * Receive config register. 26145633Swpaul */ 26240516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 26340516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 26440516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 26545633Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 26640516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 26745633Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 26845633Swpaul#define RL_RXCFG_WRAP 0x00000080 26945633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 27045633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 27145633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 27245633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 27345633Swpaul 27445633Swpaul#define RL_RXDMA_16BYTES 0x00000000 27545633Swpaul#define RL_RXDMA_32BYTES 0x00000100 27640516Swpaul#define RL_RXDMA_64BYTES 0x00000200 27740516Swpaul#define RL_RXDMA_128BYTES 0x00000300 27840516Swpaul#define RL_RXDMA_256BYTES 0x00000400 27940516Swpaul#define RL_RXDMA_512BYTES 0x00000500 28040516Swpaul#define RL_RXDMA_1024BYTES 0x00000600 28140516Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 28240516Swpaul 28340516Swpaul#define RL_RXBUF_8 0x00000000 28440516Swpaul#define RL_RXBUF_16 0x00000800 28540516Swpaul#define RL_RXBUF_32 0x00001000 28640516Swpaul#define RL_RXBUF_64 0x00001800 28740516Swpaul 28840516Swpaul#define RL_RXFIFO_16BYTES 0x00000000 28940516Swpaul#define RL_RXFIFO_32BYTES 0x00002000 29040516Swpaul#define RL_RXFIFO_64BYTES 0x00004000 29140516Swpaul#define RL_RXFIFO_128BYTES 0x00006000 29240516Swpaul#define RL_RXFIFO_256BYTES 0x00008000 29340516Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 29440516Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 29540516Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 29640516Swpaul 29740516Swpaul/* 29840516Swpaul * Bits in RX status header (included with RX'ed packet 29940516Swpaul * in ring buffer). 30040516Swpaul */ 30140516Swpaul#define RL_RXSTAT_RXOK 0x00000001 30240516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 30340516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 30440516Swpaul#define RL_RXSTAT_GIANT 0x00000008 30540516Swpaul#define RL_RXSTAT_RUNT 0x00000010 30640516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 30740516Swpaul#define RL_RXSTAT_BROAD 0x00002000 30840516Swpaul#define RL_RXSTAT_INDIV 0x00004000 30940516Swpaul#define RL_RXSTAT_MULTI 0x00008000 31040516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 31140516Swpaul 31240516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 31340516Swpaul/* 31440516Swpaul * Command register. 315171263Syongari */ 316171263Syongari#define RL_CMD_EMPTY_RXBUF 0x0001 317159962Swpaul#define RL_CMD_TX_ENB 0x0004 318159962Swpaul#define RL_CMD_RX_ENB 0x0008 319159962Swpaul#define RL_CMD_RESET 0x0010 320159962Swpaul#define RL_CMD_STOPREQ 0x0080 321159962Swpaul 322159962Swpaul/* 323159962Swpaul * Twister register values. These are completely undocumented and derived 324159962Swpaul * from public sources. 325159962Swpaul */ 32640516Swpaul#define RL_CSCFG_LINK_OK 0x0400 32767931Swpaul#define RL_CSCFG_CHANGE 0x0800 32867931Swpaul#define RL_CSCFG_STATUS 0xf000 32940516Swpaul#define RL_CSCFG_ROW3 0x7000 33040516Swpaul#define RL_CSCFG_ROW2 0x3000 33140516Swpaul#define RL_CSCFG_ROW1 0x1000 33240516Swpaul#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 33340516Swpaul#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 33440516Swpaul 33540516Swpaul#define RL_NWAYTST_RESET 0 33640516Swpaul#define RL_NWAYTST_CBL_TEST 0x20 33740516Swpaul 33840516Swpaul#define RL_PARA78 0x78 33940516Swpaul#define RL_PARA78_DEF 0x78fa8388 34040516Swpaul#define RL_PARA7C 0x7C 34140516Swpaul#define RL_PARA7C_DEF 0xcb38de43 34240516Swpaul#define RL_PARA7C_RETUNE 0xfb38de03 34340516Swpaul/* 34440516Swpaul * EEPROM control register 34540516Swpaul */ 34640516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 34740516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 34840516Swpaul#define RL_EE_CLK 0x04 /* clock */ 34940516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 35040516Swpaul#define RL_EE_MODE (0x40|0x80) 35140516Swpaul 35240516Swpaul#define RL_EEMODE_OFF 0x00 35340516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 35440516Swpaul#define RL_EEMODE_PROGRAM 0x80 35540516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 35640516Swpaul 35740516Swpaul/* 9346 EEPROM commands */ 35840516Swpaul#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 35940516Swpaul#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 36040516Swpaul 36140516Swpaul#define RL_9346_WRITE 0x5 36240516Swpaul#define RL_9346_READ 0x6 36340516Swpaul#define RL_9346_ERASE 0x7 36440516Swpaul#define RL_9346_EWEN 0x4 36540516Swpaul#define RL_9346_EWEN_ADDR 0x30 36640516Swpaul#define RL_9456_EWDS 0x4 36740516Swpaul#define RL_9346_EWDS_ADDR 0x00 36840516Swpaul 36940516Swpaul#define RL_EECMD_WRITE 0x140 37040516Swpaul#define RL_EECMD_READ_6BIT 0x180 371117388Swpaul#define RL_EECMD_READ_8BIT 0x600 372117388Swpaul#define RL_EECMD_ERASE 0x1c0 373117388Swpaul 374117388Swpaul#define RL_EE_ID 0x00 375117388Swpaul#define RL_EE_PCI_VID 0x01 376117388Swpaul#define RL_EE_PCI_DID 0x02 377117388Swpaul/* Location of station address inside EEPROM */ 378117388Swpaul#define RL_EE_EADDR 0x07 379117388Swpaul 380117388Swpaul/* 381117388Swpaul * MII register (8129 only) 382117388Swpaul */ 383117388Swpaul#define RL_MII_CLK 0x01 384120043Swpaul#define RL_MII_DATAIN 0x02 385120043Swpaul#define RL_MII_DATAOUT 0x04 386120043Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 387120043Swpaul 388120043Swpaul/* 389120043Swpaul * Config 0 register 390120043Swpaul */ 391120043Swpaul#define RL_CFG0_ROM0 0x01 392120043Swpaul#define RL_CFG0_ROM1 0x02 393120043Swpaul#define RL_CFG0_ROM2 0x04 394120043Swpaul#define RL_CFG0_PL0 0x08 395120043Swpaul#define RL_CFG0_PL1 0x10 396120043Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 397117388Swpaul#define RL_CFG0_PCS 0x40 398117388Swpaul#define RL_CFG0_SCR 0x80 399117388Swpaul 400117388Swpaul/* 401117388Swpaul * Config 1 register 402117388Swpaul */ 403117388Swpaul#define RL_CFG1_PWRDWN 0x01 404117388Swpaul#define RL_CFG1_PME 0x01 405117388Swpaul#define RL_CFG1_SLEEP 0x02 406117388Swpaul#define RL_CFG1_VPDEN 0x02 407117388Swpaul#define RL_CFG1_IOMAP 0x04 408117388Swpaul#define RL_CFG1_MEMMAP 0x08 409117388Swpaul#define RL_CFG1_RSVD 0x10 410117388Swpaul#define RL_CFG1_LWACT 0x10 411117388Swpaul#define RL_CFG1_DRVLOAD 0x20 412117388Swpaul#define RL_CFG1_LED0 0x40 413117388Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 414117388Swpaul#define RL_CFG1_LED1 0x80 415117388Swpaul 416117388Swpaul/* 417117388Swpaul * Config 2 register 418117388Swpaul */ 419117388Swpaul#define RL_CFG2_PCI33MHZ 0x00 420117388Swpaul#define RL_CFG2_PCI66MHZ 0x01 421117388Swpaul#define RL_CFG2_PCI64BIT 0x08 422117388Swpaul#define RL_CFG2_AUXPWR 0x10 423117388Swpaul#define RL_CFG2_MSI 0x20 424117388Swpaul 425119976Swpaul/* 426117388Swpaul * Config 3 register 427117388Swpaul */ 428117388Swpaul#define RL_CFG3_GRANTSEL 0x80 429117388Swpaul#define RL_CFG3_WOL_MAGIC 0x20 430117388Swpaul#define RL_CFG3_WOL_LINK 0x10 43140516Swpaul#define RL_CFG3_FAST_B2B 0x01 43240516Swpaul 43340516Swpaul/* 43440516Swpaul * Config 4 register 43540516Swpaul */ 43640516Swpaul#define RL_CFG4_LWPTN 0x04 43740516Swpaul#define RL_CFG4_LWPME 0x10 43840516Swpaul 43940516Swpaul/* 44040516Swpaul * Config 5 register 44140516Swpaul */ 44240516Swpaul#define RL_CFG5_WOL_BCAST 0x40 44340516Swpaul#define RL_CFG5_WOL_MCAST 0x20 44440516Swpaul#define RL_CFG5_WOL_UCAST 0x10 44540516Swpaul#define RL_CFG5_WOL_LANWAKE 0x02 44640516Swpaul#define RL_CFG5_PME_STS 0x01 44740516Swpaul 44840516Swpaul/* 44952426Swpaul * 8139C+ register definitions 45052426Swpaul */ 451119868Swpaul 452119868Swpaul/* RL_DUMPSTATS_LO register */ 45350703Swpaul 45440516Swpaul#define RL_DUMPSTATS_START 0x00000008 45545633Swpaul 45645633Swpaul/* Transmit start register */ 45740516Swpaul 45848028Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 45948028Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 46040516Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 461131605Sbms 462131605Sbms/* 463131605Sbms * Config 2 register, 8139C+/8169/8169S/8110S only 46481713Swpaul */ 46540516Swpaul#define RL_CFG2_BUSFREQ 0x07 46645633Swpaul#define RL_CFG2_BUSWIDTH 0x08 46781713Swpaul#define RL_CFG2_AUXPWRSTS 0x10 468131605Sbms 469131605Sbms#define RL_BUSFREQ_33MHZ 0x00 47040516Swpaul#define RL_BUSFREQ_66MHZ 0x01 47140516Swpaul 47245633Swpaul#define RL_BUSWIDTH_32BITS 0x00 47345633Swpaul#define RL_BUSWIDTH_64BITS 0x08 47445633Swpaul 47545633Swpaul/* C+ mode command register */ 47681713Swpaul 47745633Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 47845633Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 47945633Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 48081713Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 48145633Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 48240516Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 483131605Sbms#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 484131605Sbms#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 485117388Swpaul#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 48640516Swpaul#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 48740516Swpaul#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 48840516Swpaul#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 489117388Swpaul#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 490131605Sbms#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 491117388Swpaul#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 492117388Swpaul 493117388Swpaul/* C+ early transmit threshold */ 494117388Swpaul 49540516Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 496131605Sbms 497131605Sbms/* 498131605Sbms * Gigabit PHY access register (8169 only) 499131605Sbms */ 500131605Sbms 501131605Sbms#define RL_PHYAR_PHYDATA 0x0000FFFF 50240516Swpaul#define RL_PHYAR_PHYREG 0x001F0000 50340516Swpaul#define RL_PHYAR_BUSY 0x80000000 50440516Swpaul 50540516Swpaul/* 50640516Swpaul * Gigabit media status (8169 only) 50740516Swpaul */ 50840516Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 50940516Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 51040516Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 51140516Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 51240516Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 51340516Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 514117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 515117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 51640516Swpaul 517117388Swpaul/* 518117388Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 519117388Swpaul * Instead, there are only four register sets, each or which represents 520117388Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 521117388Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 522117388Swpaul * the registers so the chip knows where they are. 523117388Swpaul * 524117388Swpaul * We can sort of kludge together the same kind of buffer management 525117388Swpaul * used in previous drivers, but we have to do buffer copies almost all 526117388Swpaul * the time, so it doesn't really buy us much. 527117388Swpaul * 528117388Swpaul * For reception, there's just one large buffer where the chip stores 529117388Swpaul * all received packets. 530117388Swpaul */ 531117388Swpaul 532117388Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 533117388Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 534117388Swpaul#define RL_TX_LIST_CNT 4 535131605Sbms#define RL_MIN_FRAMELEN 60 536131605Sbms#define RL_TX_8139_BUF_ALIGN 4 537131605Sbms#define RL_RX_8139_BUF_ALIGN 8 538131605Sbms#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 539117388Swpaul#define RL_RX_8139_BUF_GUARD_SZ \ 540117388Swpaul (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 541117388Swpaul#define RL_TXTHRESH(x) ((x) << 11) 542117388Swpaul#define RL_TX_THRESH_INIT 96 543117388Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 544117388Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 545117388Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 546164463Syongari 547117388Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 548117388Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 549117388Swpaul 550117388Swpaul#define RL_ETHER_ALIGN 2 551117388Swpaul 552117388Swpaul/* 553117388Swpaul * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 554117388Swpaul */ 555117388Swpaul#define RL_IP4CSUMTX_MINLEN 28 556117388Swpaul#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 557117388Swpaul 558117388Swpaulstruct rl_chain_data { 559117388Swpaul uint16_t cur_rx; 560117388Swpaul uint8_t *rl_rx_buf; 561117388Swpaul uint8_t *rl_rx_buf_ptr; 562117388Swpaul 563117388Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 564117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 565117388Swpaul bus_dma_tag_t rl_tx_tag; 566117388Swpaul bus_dma_tag_t rl_rx_tag; 567117388Swpaul bus_dmamap_t rl_rx_dmamap; 568117388Swpaul bus_addr_t rl_rx_buf_paddr; 569117388Swpaul uint8_t last_tx; 570117388Swpaul uint8_t cur_tx; 571117388Swpaul}; 572117388Swpaul 573117388Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 574117388Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 575119981Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 576117388Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 577117388Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 578117388Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 579117388Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 580117388Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 581117388Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 582117388Swpaul 583117388Swpaulstruct rl_type { 584117388Swpaul uint16_t rl_vid; 585117388Swpaul uint16_t rl_did; 586117388Swpaul int rl_basetype; 587117388Swpaul char *rl_name; 588117388Swpaul}; 589117388Swpaul 590117388Swpaulstruct rl_hwrev { 591117388Swpaul uint32_t rl_rev; 592117388Swpaul int rl_type; 593117388Swpaul char *rl_desc; 594117388Swpaul}; 595119981Swpaul 596119981Swpaulstruct rl_mii_frame { 597135896Sjmg uint8_t mii_stdelim; 598135896Sjmg uint8_t mii_opcode; 599117388Swpaul uint8_t mii_phyaddr; 600117388Swpaul uint8_t mii_regaddr; 601117388Swpaul uint8_t mii_turnaround; 602117388Swpaul uint16_t mii_data; 603117388Swpaul}; 604117388Swpaul 605117388Swpaul/* 606117388Swpaul * MII constants 607117388Swpaul */ 608117388Swpaul#define RL_MII_STARTDELIM 0x01 609117388Swpaul#define RL_MII_READOP 0x02 610117388Swpaul#define RL_MII_WRITEOP 0x01 611117388Swpaul#define RL_MII_TURNAROUND 0x02 612117388Swpaul 613117388Swpaul#define RL_8129 1 614117388Swpaul#define RL_8139 2 615117388Swpaul#define RL_8139CPLUS 3 616117388Swpaul#define RL_8169 4 617131605Sbms 618131605Sbms#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 619131605Sbms (x)->rl_type == RL_8169) 620131605Sbms 621131605Sbms/* 622131605Sbms * The 8139C+ and 8160 gigE chips support descriptor-based TX 623131605Sbms * and RX. In fact, they even support TCP large send. Descriptors 624131605Sbms * must be allocated in contiguous blocks that are aligned on a 625131605Sbms * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 626131605Sbms */ 627131605Sbms 628131605Sbms/* 629131605Sbms * RX/TX descriptor definition. When large send mode is enabled, the 630131605Sbms * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 631131605Sbms * the checksum offload bits are disabled. The structure layout is 632131605Sbms * the same for RX and TX descriptors 633117388Swpaul */ 634117388Swpaul 635135467Sjmgstruct rl_desc { 636135467Sjmg uint32_t rl_cmdstat; 637135467Sjmg uint32_t rl_vlanctl; 638135467Sjmg uint32_t rl_bufaddr_lo; 639135896Sjmg uint32_t rl_bufaddr_hi; 640135896Sjmg}; 641135896Sjmg 642135467Sjmg#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 643164460Syongari#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 644135896Sjmg#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 645135896Sjmg#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 646135896Sjmg#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 647117388Swpaul#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 648166057Smarius#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 649135469Sjmg#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 650159962Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 651117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 652117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 653117388Swpaul 654117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 655117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 656117388Swpaul/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 657119981Swpaul#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 658119868Swpaul#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 659135896Sjmg#define RL_TDESC_CMD_IPCSUMV2 0x20000000 660135896Sjmg#define RL_TDESC_CMD_MSSVALV2 0x1FFC0000 661135896Sjmg#define RL_TDESC_CMD_MSSVALV2_SHIFT 18 662135896Sjmg 663135896Sjmg/* 664135896Sjmg * Error bits are valid only on the last descriptor of a frame 665135896Sjmg * (i.e. RL_TDESC_CMD_EOF == 1) 666117388Swpaul */ 667171560Syongari 668171560Syongari#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 669135467Sjmg#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 670135467Sjmg#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 671118712Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 672135896Sjmg#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 673135896Sjmg#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 674119868Swpaul#define RL_TDESC_STAT_OWN 0x80000000 675119868Swpaul 676117388Swpaul/* 677117388Swpaul * RX descriptor cmd/vlan definitions 678117388Swpaul */ 679117388Swpaul 680117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 681131605Sbms#define RL_RDESC_CMD_OWN 0x80000000 682117388Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 683117388Swpaul 684117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 685117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 686117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 687159962Swpaul#define RL_RDESC_STAT_EOF 0x10000000 688117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 689117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 690117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 691117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 692117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 693117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 694117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 695117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 696117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 697117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 698118712Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 699117388Swpaul#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 700117388Swpaul#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 701117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 702118712Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 703117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 704117388Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 705117388Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 706118712Swpaul#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 707117388Swpaul RL_RDESC_STAT_CRCERR) 708117388Swpaul 70940516Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 710147256Sbrooks (rl_vlandata valid)*/ 71141569Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 71241569Swpaul/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 713159962Swpaul#define RL_RDESC_IPV6 0x80000000 71450703Swpaul#define RL_RDESC_IPV4 0x40000000 715171560Syongari 716171560Syongari#define RL_PROTOID_NONIP 0x00000000 71750703Swpaul#define RL_PROTOID_TCPIP 0x00010000 71881713Swpaul#define RL_PROTOID_UDPIP 0x00020000 71981713Swpaul#define RL_PROTOID_IP 0x00030000 720131605Sbms#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 72167931Swpaul RL_PROTOID_TCPIP) 722159962Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 723131605Sbms RL_PROTOID_UDPIP) 72452426Swpaul 72540516Swpaul/* 726117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 727150720Sjhb */ 728164811Srustruct rl_stats { 72967087Swpaul uint64_t rl_tx_pkts; 730119868Swpaul uint64_t rl_rx_pkts; 731119868Swpaul uint64_t rl_tx_errs; 732131605Sbms uint32_t rl_rx_errs; 733131605Sbms uint16_t rl_missed_pkts; 734119868Swpaul uint16_t rl_rx_framealign_errs; 735168828Syongari uint32_t rl_tx_onecoll; 73686822Siwasaki uint32_t rl_tx_multicolls; 73794883Sluigi uint64_t rl_rx_ucasts; 73894883Sluigi uint64_t rl_rx_bcasts; 73994883Sluigi uint32_t rl_rx_mcasts; 740159962Swpaul uint16_t rl_tx_aborts; 741159962Swpaul uint16_t rl_rx_underruns; 742159962Swpaul}; 743159962Swpaul 744159962Swpaul/* 745159962Swpaul * Rx/Tx descriptor parameters (8139C+ and 8169 only) 746159962Swpaul * 747171560Syongari * 8139C+ 74840516Swpaul * Number of descriptors supported : up to 64 74940516Swpaul * Descriptor alignment : 256 bytes 75072200Sbmilekic * Tx buffer : At least 4 bytes in length. 75172200Sbmilekic * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 752122689Ssam * 75367087Swpaul * 8169 75440516Swpaul * Number of descriptors supported : up to 1024 75540516Swpaul * Descriptor alignment : 256 bytes 75640516Swpaul * Tx buffer : At least 4 bytes in length. 757119868Swpaul * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 758119738Stmm */ 75940516Swpaul#ifndef __NO_STRICT_ALIGNMENT 76041569Swpaul#define RE_FIXUP_RX 1 76140516Swpaul#endif 76241569Swpaul 76340516Swpaul#define RL_8169_TX_DESC_CNT 256 76441569Swpaul#define RL_8169_RX_DESC_CNT 256 76540516Swpaul#define RL_8139_TX_DESC_CNT 64 76641569Swpaul#define RL_8139_RX_DESC_CNT 64 76741569Swpaul#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 76841569Swpaul#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 76941569Swpaul#define RL_NTXSEGS 32 77041569Swpaul 77141569Swpaul#define RL_RING_ALIGN 256 77240516Swpaul#define RL_DUMP_ALIGN 64 773159962Swpaul#define RL_IFQ_MAXLEN 512 774159962Swpaul#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 775159962Swpaul#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 776159962Swpaul#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 777159962Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 778159962Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 779159962Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 780159962Swpaul#ifdef RE_FIXUP_RX 781159962Swpaul#define RE_ETHER_ALIGN sizeof(uint64_t) 782159962Swpaul#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 783159962Swpaul#else 784159962Swpaul#define RE_ETHER_ALIGN 0 785159962Swpaul#define RE_RX_DESC_BUFLEN MCLBYTES 786159962Swpaul#endif 787159962Swpaul 788159962Swpaul#define RL_MSI_MESSAGES 1 789159962Swpaul 790159962Swpaul#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 79140516Swpaul#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 79240516Swpaul 79340516Swpaul/* 79440516Swpaul * The number of bits reserved for MSS in RealTek controllers is 79540516Swpaul * 11bits. This limits the maximum interface MTU size in TSO case 79640516Swpaul * as upper stack should not generate TCP segments with MSS greater 79740516Swpaul * than the limit. 79840516Swpaul */ 79940516Swpaul#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 80040516Swpaul 80140516Swpaul/* see comment in dev/re/if_re.c */ 80240516Swpaul#define RL_JUMBO_FRAMELEN 7440 80340516Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 804159962Swpaul#define RL_MAX_FRAMELEN \ 80567771Swpaul (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 80640516Swpaul 807159962Swpaulstruct rl_txdesc { 808159962Swpaul struct mbuf *tx_m; 809117388Swpaul bus_dmamap_t tx_dmamap; 810118978Swpaul}; 81140516Swpaul 812117388Swpaulstruct rl_rxdesc { 813117388Swpaul struct mbuf *rx_m; 81440516Swpaul bus_dmamap_t rx_dmamap; 81544238Swpaul bus_size_t rx_size; 81644238Swpaul}; 81744238Swpaul 81844238Swpaulstruct rl_list_data { 81944238Swpaul struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 82041243Swpaul struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 82141243Swpaul int rl_tx_desc_cnt; 82241243Swpaul int rl_rx_desc_cnt; 82341243Swpaul int rl_tx_prodidx; 82441243Swpaul int rl_rx_prodidx; 82594400Swpaul int rl_tx_considx; 82694400Swpaul int rl_tx_free; 82794400Swpaul bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 82894400Swpaul bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 82994400Swpaul bus_dmamap_t rl_rx_sparemap; 83044238Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 83144238Swpaul bus_dmamap_t rl_smap; /* stats map */ 83244238Swpaul struct rl_stats *rl_stats; 83344238Swpaul bus_addr_t rl_stats_addr; 83444238Swpaul bus_dma_tag_t rl_rx_list_tag; 83544238Swpaul bus_dmamap_t rl_rx_list_map; 83644238Swpaul struct rl_desc *rl_rx_list; 83744238Swpaul bus_addr_t rl_rx_list_addr; 83844238Swpaul bus_dma_tag_t rl_tx_list_tag; 83944238Swpaul bus_dmamap_t rl_tx_list_map; 84044238Swpaul struct rl_desc *rl_tx_list; 84144238Swpaul bus_addr_t rl_tx_list_addr; 84244238Swpaul}; 84344238Swpaul 84444238Swpaulenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 84544238Swpaul 84644238Swpaulstruct rl_softc { 84744238Swpaul struct ifnet *rl_ifp; /* interface info */ 84844238Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 84944238Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 85072813Swpaul device_t rl_dev; 85172813Swpaul struct resource *rl_res; 85272813Swpaul int rl_res_id; 85372813Swpaul int rl_res_type; 85472813Swpaul struct resource *rl_irq[RL_MSI_MESSAGES]; 85572813Swpaul void *rl_intrhand[RL_MSI_MESSAGES]; 85672813Swpaul device_t rl_miibus; 85772813Swpaul bus_dma_tag_t rl_parent_tag; 85872813Swpaul uint8_t rl_type; 85972813Swpaul int rl_eecmd_read; 860148722Stobez int rl_eewidth; 861148722Stobez uint8_t rl_stats_no_timeout; 862148722Stobez int rl_txthresh; 863148722Stobez struct rl_chain_data rl_cdata; 864148722Stobez struct rl_list_data rl_ldata; 86596112Sjhb struct callout rl_stat_callout; 86696112Sjhb int rl_watchdog_timer; 86796112Sjhb struct mtx rl_mtx; 86896112Sjhb struct mbuf *rl_head; 86996112Sjhb struct mbuf *rl_tail; 870103020Siwasaki uint32_t rl_hwrev; 871103020Siwasaki uint32_t rl_rxlenmask; 872103020Siwasaki int rl_testmode; 873103020Siwasaki int rl_if_flags; 874103020Siwasaki int rl_twister_enable; 875109095Ssanpei enum rl_twist rl_twister; 876103020Siwasaki int rl_twist_row; 877151341Sjhb int rl_twist_col; 878103020Siwasaki int suspended; /* 0 = normal 1 = suspended */ 879103020Siwasaki#ifdef DEVICE_POLLING 880109095Ssanpei int rxcycles; 881109095Ssanpei#endif 882151341Sjhb 883109095Ssanpei struct task rl_txtask; 884111381Sdan struct task rl_inttask; 885134433Ssanpei 886134433Ssanpei int rl_txstart; 887134433Ssanpei uint32_t rl_flags; 888134433Ssanpei#define RL_FLAG_MSI 0x0001 889134433Ssanpei#define RL_FLAG_AUTOPAD 0x0002 890151341Sjhb#define RL_FLAG_PHYWAKE_PM 0x0004 891151341Sjhb#define RL_FLAG_PHYWAKE 0x0008 892151341Sjhb#define RL_FLAG_NOJUMBO 0x0010 893151341Sjhb#define RL_FLAG_PAR 0x0020 894151341Sjhb#define RL_FLAG_DESCV2 0x0040 895151341Sjhb#define RL_FLAG_MACSTAT 0x0080 896151341Sjhb#define RL_FLAG_FASTETHER 0x0100 897151341Sjhb#define RL_FLAG_CMDSTOP 0x0200 898151341Sjhb#define RL_FLAG_MACRESET 0x0400 899151341Sjhb#define RL_FLAG_WOLRXENB 0x1000 900151341Sjhb#define RL_FLAG_MACSLEEP 0x2000 901151341Sjhb#define RL_FLAG_PCIE 0x4000 902151341Sjhb#define RL_FLAG_LINK 0x8000 903151341Sjhb}; 904151341Sjhb 905111381Sdan#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 906111381Sdan#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 907111381Sdan#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 908109095Ssanpei 909111381Sdan/* 910111381Sdan * register space access macros 911111381Sdan */ 912111381Sdan#define CSR_WRITE_STREAM_4(sc, reg, val) \ 913109095Ssanpei bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 914109095Ssanpei#define CSR_WRITE_4(sc, reg, val) \ 915112379Ssanpei bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 916112379Ssanpei#define CSR_WRITE_2(sc, reg, val) \ 917117388Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 918112379Ssanpei#define CSR_WRITE_1(sc, reg, val) \ 919112379Ssanpei bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 920112379Ssanpei 921112379Ssanpei#define CSR_READ_4(sc, reg) \ 922117388Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 923112379Ssanpei#define CSR_READ_2(sc, reg) \ 924112379Ssanpei bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 925117388Swpaul#define CSR_READ_1(sc, reg) \ 926117388Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 927117388Swpaul 928117388Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 929117388Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 930117388Swpaul 931117388Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 932117388Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 933117388Swpaul 934117388Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 935117388Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 936117388Swpaul 937117388Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 938117388Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 939117388Swpaul 940117388Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 941117388Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 942117388Swpaul 943117388Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 944117388Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 945117388Swpaul 946117388Swpaul#define RL_TIMEOUT 1000 947117388Swpaul#define RL_PHY_TIMEOUT 2000 948117388Swpaul 949160883Swpaul/* 950160883Swpaul * General constants that are fun to know. 951160883Swpaul * 952160883Swpaul * RealTek PCI vendor ID 953160883Swpaul */ 954160883Swpaul#define RT_VENDORID 0x10EC 955160883Swpaul 956160883Swpaul/* 957117388Swpaul * RealTek chip device IDs. 95840516Swpaul */ 95950703Swpaul#define RT_DEVICEID_8139D 0x8039 96040516Swpaul#define RT_DEVICEID_8129 0x8129 96140516Swpaul#define RT_DEVICEID_8101E 0x8136 96240516Swpaul#define RT_DEVICEID_8138 0x8138 96340516Swpaul#define RT_DEVICEID_8139 0x8139 96440516Swpaul#define RT_DEVICEID_8169SC 0x8167 96540516Swpaul#define RT_DEVICEID_8168 0x8168 96640516Swpaul#define RT_DEVICEID_8169 0x8169 96740516Swpaul#define RT_DEVICEID_8100 0x8100 96840516Swpaul 96940516Swpaul#define RT_REVID_8139CPLUS 0x20 97040516Swpaul 97140516Swpaul/* 97240516Swpaul * Accton PCI vendor ID 97340516Swpaul */ 97440516Swpaul#define ACCTON_VENDORID 0x1113 97540516Swpaul 97640516Swpaul/* 97740516Swpaul * Accton MPX 5030/5038 device ID. 97840516Swpaul */ 97950097Swpaul#define ACCTON_DEVICEID_5030 0x1211 98050097Swpaul 98150097Swpaul/* 98250097Swpaul * Nortel PCI vendor ID 98340516Swpaul */ 98440516Swpaul#define NORTEL_VENDORID 0x126C 98540516Swpaul 98640516Swpaul/* 98740516Swpaul * Delta Electronics Vendor ID. 98840516Swpaul */ 98940516Swpaul#define DELTA_VENDORID 0x1500 99040516Swpaul 991/* 992 * Delta device IDs. 993 */ 994#define DELTA_DEVICEID_8139 0x1360 995 996/* 997 * Addtron vendor ID. 998 */ 999#define ADDTRON_VENDORID 0x4033 1000 1001/* 1002 * Addtron device IDs. 1003 */ 1004#define ADDTRON_DEVICEID_8139 0x1360 1005 1006/* 1007 * D-Link vendor ID. 1008 */ 1009#define DLINK_VENDORID 0x1186 1010 1011/* 1012 * D-Link DFE-530TX+ device ID 1013 */ 1014#define DLINK_DEVICEID_530TXPLUS 0x1300 1015 1016/* 1017 * D-Link DFE-5280T device ID 1018 */ 1019#define DLINK_DEVICEID_528T 0x4300 1020 1021/* 1022 * D-Link DFE-690TXD device ID 1023 */ 1024#define DLINK_DEVICEID_690TXD 0x1340 1025 1026/* 1027 * Corega K.K vendor ID 1028 */ 1029#define COREGA_VENDORID 0x1259 1030 1031/* 1032 * Corega FEther CB-TXD device ID 1033 */ 1034#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1035 1036/* 1037 * Corega FEtherII CB-TXD device ID 1038 */ 1039#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1040 1041/* 1042 * Corega CG-LAPCIGT device ID 1043 */ 1044#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1045 1046/* 1047 * Linksys vendor ID 1048 */ 1049#define LINKSYS_VENDORID 0x1737 1050 1051/* 1052 * Linksys EG1032 device ID 1053 */ 1054#define LINKSYS_DEVICEID_EG1032 0x1032 1055 1056/* 1057 * Linksys EG1032 rev 3 sub-device ID 1058 */ 1059#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1060 1061/* 1062 * Peppercon vendor ID 1063 */ 1064#define PEPPERCON_VENDORID 0x1743 1065 1066/* 1067 * Peppercon ROL-F device ID 1068 */ 1069#define PEPPERCON_DEVICEID_ROLF 0x8139 1070 1071/* 1072 * Planex Communications, Inc. vendor ID 1073 */ 1074#define PLANEX_VENDORID 0x14ea 1075 1076/* 1077 * Planex FNW-3603-TX device ID 1078 */ 1079#define PLANEX_DEVICEID_FNW3603TX 0xab06 1080 1081/* 1082 * Planex FNW-3800-TX device ID 1083 */ 1084#define PLANEX_DEVICEID_FNW3800TX 0xab07 1085 1086/* 1087 * LevelOne vendor ID 1088 */ 1089#define LEVEL1_VENDORID 0x018A 1090 1091/* 1092 * LevelOne FPC-0106TX devide ID 1093 */ 1094#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1095 1096/* 1097 * Compaq vendor ID 1098 */ 1099#define CP_VENDORID 0x021B 1100 1101/* 1102 * Edimax vendor ID 1103 */ 1104#define EDIMAX_VENDORID 0x13D1 1105 1106/* 1107 * Edimax EP-4103DL cardbus device ID 1108 */ 1109#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1110 1111/* US Robotics vendor ID */ 1112 1113#define USR_VENDORID 0x16EC 1114 1115/* US Robotics 997902 device ID */ 1116 1117#define USR_DEVICEID_997902 0x0116 1118