if_rlreg.h revision 196516
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 196516 2009-08-24 18:58:13Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 8440516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 8640516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8740516Swpaul#define RL_HALTCLK 0x005B 8840516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8940516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 9140516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 9440516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9540516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9640516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9740516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9840516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 10040516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 10140516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 10240516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 10340516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10440516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117120043Swpaul#define RL_CFG2 0x0053 118117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 120117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129117388Swpaul#define RL_PHYAR 0x0060 130117388Swpaul#define RL_TBICSR 0x0064 131117388Swpaul#define RL_TBI_ANAR 0x0068 132117388Swpaul#define RL_TBI_LPAR 0x006A 133117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134186210Syongari#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 135186210Syongari#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ 136117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 137175337Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 138117388Swpaul 139117388Swpaul/* 14040516Swpaul * TX config register bits 14140516Swpaul */ 14240516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 14345633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 14440516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 14545633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 146119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14745633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 148117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14940516Swpaul 150119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 151119868Swpaul#define RL_LOOPTEST_ON 0x00020000 152119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 153119868Swpaul 154159962Swpaul/* Known revision codes. */ 155117388Swpaul 156160843Swpaul#define RL_HWREV_8169 0x00000000 157187483Sjkim#define RL_HWREV_8169S 0x00800000 158187483Sjkim#define RL_HWREV_8110S 0x04000000 159160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 160160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 161180377Syongari#define RL_HWREV_8102EL 0x24800000 162195675Savatar#define RL_HWREV_8102EL_SPIN1 0x24c00000 163185542Syongari#define RL_HWREV_8168D 0x28000000 164196516Syongari#define RL_HWREV_8168DP 0x28800000 165160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 166160843Swpaul#define RL_HWREV_8100E 0x30800000 167160843Swpaul#define RL_HWREV_8101E 0x34000000 168180377Syongari#define RL_HWREV_8102E 0x34800000 169160843Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 170174428Syongari#define RL_HWREV_8168_SPIN3 0x38400000 171180176Syongari#define RL_HWREV_8168C 0x3C000000 172180176Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 173180176Syongari#define RL_HWREV_8168CP 0x3C800000 174160843Swpaul#define RL_HWREV_8139 0x60000000 175160843Swpaul#define RL_HWREV_8139A 0x70000000 176160843Swpaul#define RL_HWREV_8139AG 0x70800000 177160843Swpaul#define RL_HWREV_8139B 0x78000000 178160843Swpaul#define RL_HWREV_8130 0x7C000000 179160843Swpaul#define RL_HWREV_8139C 0x74000000 180160843Swpaul#define RL_HWREV_8139D 0x74400000 181160843Swpaul#define RL_HWREV_8139CPLUS 0x74800000 182160843Swpaul#define RL_HWREV_8101 0x74c00000 183160843Swpaul#define RL_HWREV_8100 0x78800000 184180177Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 185187483Sjkim#define RL_HWREV_8169_8110SCE 0x98000000 186159962Swpaul 18745633Swpaul#define RL_TXDMA_16BYTES 0x00000000 18845633Swpaul#define RL_TXDMA_32BYTES 0x00000100 18945633Swpaul#define RL_TXDMA_64BYTES 0x00000200 19045633Swpaul#define RL_TXDMA_128BYTES 0x00000300 19145633Swpaul#define RL_TXDMA_256BYTES 0x00000400 19245633Swpaul#define RL_TXDMA_512BYTES 0x00000500 19345633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 19445633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 19545633Swpaul 19640516Swpaul/* 19740516Swpaul * Transmit descriptor status register bits. 19840516Swpaul */ 19940516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 20040516Swpaul#define RL_TXSTAT_OWN 0x00002000 20140516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 20240516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 20340516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 20440516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 20540516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 20640516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 20740516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 20840516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 20940516Swpaul 21040516Swpaul/* 21140516Swpaul * Interrupt status register bits. 21240516Swpaul */ 21340516Swpaul#define RL_ISR_RX_OK 0x0001 21440516Swpaul#define RL_ISR_RX_ERR 0x0002 21540516Swpaul#define RL_ISR_TX_OK 0x0004 21640516Swpaul#define RL_ISR_TX_ERR 0x0008 21740516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 21840516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 219119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 22040516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 221117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 222117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 223117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 22440516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 225117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 22640516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 22740516Swpaul 22840516Swpaul#define RL_INTRS \ 22940516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 23040516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 23140516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 23240516Swpaul 233159962Swpaul#ifdef RE_TX_MODERATION 234117388Swpaul#define RL_INTRS_CPLUS \ 235119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 236117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 237117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 238159962Swpaul#else 239159962Swpaul#define RL_INTRS_CPLUS \ 240159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 241159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 242159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 243159962Swpaul#endif 244117388Swpaul 24540516Swpaul/* 24640516Swpaul * Media status register. (8139 only) 24740516Swpaul */ 24840516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 24940516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 25040516Swpaul#define RL_MEDIASTAT_LINK 0x04 25140516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 25240516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 25340516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 25440516Swpaul 25540516Swpaul/* 25640516Swpaul * Receive config register. 25740516Swpaul */ 25840516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 25940516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 26040516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 26140516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 26240516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 26340516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 26440516Swpaul#define RL_RXCFG_WRAP 0x00000080 26545633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 26645633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 26745633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 26845633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 26940516Swpaul 27045633Swpaul#define RL_RXDMA_16BYTES 0x00000000 27145633Swpaul#define RL_RXDMA_32BYTES 0x00000100 27245633Swpaul#define RL_RXDMA_64BYTES 0x00000200 27345633Swpaul#define RL_RXDMA_128BYTES 0x00000300 27445633Swpaul#define RL_RXDMA_256BYTES 0x00000400 27545633Swpaul#define RL_RXDMA_512BYTES 0x00000500 27645633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 27745633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 27845633Swpaul 27940516Swpaul#define RL_RXBUF_8 0x00000000 28040516Swpaul#define RL_RXBUF_16 0x00000800 28140516Swpaul#define RL_RXBUF_32 0x00001000 28245633Swpaul#define RL_RXBUF_64 0x00001800 28340516Swpaul 28445633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 28545633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 28645633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 28745633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 28845633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 28945633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 29045633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 29145633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 29245633Swpaul 29340516Swpaul/* 29440516Swpaul * Bits in RX status header (included with RX'ed packet 29540516Swpaul * in ring buffer). 29640516Swpaul */ 29740516Swpaul#define RL_RXSTAT_RXOK 0x00000001 29840516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 29940516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 30040516Swpaul#define RL_RXSTAT_GIANT 0x00000008 30140516Swpaul#define RL_RXSTAT_RUNT 0x00000010 30240516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 30340516Swpaul#define RL_RXSTAT_BROAD 0x00002000 30440516Swpaul#define RL_RXSTAT_INDIV 0x00004000 30540516Swpaul#define RL_RXSTAT_MULTI 0x00008000 30640516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 30740516Swpaul 30840516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 30940516Swpaul/* 31040516Swpaul * Command register. 31140516Swpaul */ 31240516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 31340516Swpaul#define RL_CMD_TX_ENB 0x0004 31440516Swpaul#define RL_CMD_RX_ENB 0x0008 31540516Swpaul#define RL_CMD_RESET 0x0010 316185900Syongari#define RL_CMD_STOPREQ 0x0080 31740516Swpaul 31840516Swpaul/* 319184515Simp * Twister register values. These are completely undocumented and derived 320184515Simp * from public sources. 321184515Simp */ 322184515Simp#define RL_CSCFG_LINK_OK 0x0400 323184515Simp#define RL_CSCFG_CHANGE 0x0800 324184515Simp#define RL_CSCFG_STATUS 0xf000 325184515Simp#define RL_CSCFG_ROW3 0x7000 326184515Simp#define RL_CSCFG_ROW2 0x3000 327184515Simp#define RL_CSCFG_ROW1 0x1000 328184515Simp#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 329184515Simp#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 330184515Simp 331184515Simp#define RL_NWAYTST_RESET 0 332184515Simp#define RL_NWAYTST_CBL_TEST 0x20 333184515Simp 334184515Simp#define RL_PARA78 0x78 335184515Simp#define RL_PARA78_DEF 0x78fa8388 336184515Simp#define RL_PARA7C 0x7C 337184515Simp#define RL_PARA7C_DEF 0xcb38de43 338184515Simp#define RL_PARA7C_RETUNE 0xfb38de03 339184515Simp/* 34040516Swpaul * EEPROM control register 34140516Swpaul */ 34240516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 34340516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 34440516Swpaul#define RL_EE_CLK 0x04 /* clock */ 34540516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 34640516Swpaul#define RL_EE_MODE (0x40|0x80) 34740516Swpaul 34840516Swpaul#define RL_EEMODE_OFF 0x00 34940516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 35040516Swpaul#define RL_EEMODE_PROGRAM 0x80 35140516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 35240516Swpaul 35340516Swpaul/* 9346 EEPROM commands */ 354171263Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 355171263Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 356159962Swpaul 357159962Swpaul#define RL_9346_WRITE 0x5 358159962Swpaul#define RL_9346_READ 0x6 359159962Swpaul#define RL_9346_ERASE 0x7 360159962Swpaul#define RL_9346_EWEN 0x4 361159962Swpaul#define RL_9346_EWEN_ADDR 0x30 362159962Swpaul#define RL_9456_EWDS 0x4 363159962Swpaul#define RL_9346_EWDS_ADDR 0x00 364159962Swpaul 36540516Swpaul#define RL_EECMD_WRITE 0x140 36667931Swpaul#define RL_EECMD_READ_6BIT 0x180 36767931Swpaul#define RL_EECMD_READ_8BIT 0x600 36840516Swpaul#define RL_EECMD_ERASE 0x1c0 36940516Swpaul 37040516Swpaul#define RL_EE_ID 0x00 37140516Swpaul#define RL_EE_PCI_VID 0x01 37240516Swpaul#define RL_EE_PCI_DID 0x02 37340516Swpaul/* Location of station address inside EEPROM */ 37440516Swpaul#define RL_EE_EADDR 0x07 37540516Swpaul 37640516Swpaul/* 37740516Swpaul * MII register (8129 only) 37840516Swpaul */ 37940516Swpaul#define RL_MII_CLK 0x01 38040516Swpaul#define RL_MII_DATAIN 0x02 38140516Swpaul#define RL_MII_DATAOUT 0x04 38240516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 38340516Swpaul 38440516Swpaul/* 38540516Swpaul * Config 0 register 38640516Swpaul */ 38740516Swpaul#define RL_CFG0_ROM0 0x01 38840516Swpaul#define RL_CFG0_ROM1 0x02 38940516Swpaul#define RL_CFG0_ROM2 0x04 39040516Swpaul#define RL_CFG0_PL0 0x08 39140516Swpaul#define RL_CFG0_PL1 0x10 39240516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 39340516Swpaul#define RL_CFG0_PCS 0x40 39440516Swpaul#define RL_CFG0_SCR 0x80 39540516Swpaul 39640516Swpaul/* 39740516Swpaul * Config 1 register 39840516Swpaul */ 39940516Swpaul#define RL_CFG1_PWRDWN 0x01 400176754Syongari#define RL_CFG1_PME 0x01 40140516Swpaul#define RL_CFG1_SLEEP 0x02 402176754Syongari#define RL_CFG1_VPDEN 0x02 40340516Swpaul#define RL_CFG1_IOMAP 0x04 40440516Swpaul#define RL_CFG1_MEMMAP 0x08 40540516Swpaul#define RL_CFG1_RSVD 0x10 406176754Syongari#define RL_CFG1_LWACT 0x10 40740516Swpaul#define RL_CFG1_DRVLOAD 0x20 40840516Swpaul#define RL_CFG1_LED0 0x40 40940516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 41040516Swpaul#define RL_CFG1_LED1 0x80 41140516Swpaul 41240516Swpaul/* 413176754Syongari * Config 2 register 414176754Syongari */ 415176754Syongari#define RL_CFG2_PCI33MHZ 0x00 416176754Syongari#define RL_CFG2_PCI66MHZ 0x01 417176754Syongari#define RL_CFG2_PCI64BIT 0x08 418176754Syongari#define RL_CFG2_AUXPWR 0x10 419177522Syongari#define RL_CFG2_MSI 0x20 420176754Syongari 421176754Syongari/* 422176754Syongari * Config 3 register 423176754Syongari */ 424176754Syongari#define RL_CFG3_GRANTSEL 0x80 425176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 426176754Syongari#define RL_CFG3_WOL_LINK 0x10 427176754Syongari#define RL_CFG3_FAST_B2B 0x01 428176754Syongari 429176754Syongari/* 430176754Syongari * Config 4 register 431176754Syongari */ 432176754Syongari#define RL_CFG4_LWPTN 0x04 433176754Syongari#define RL_CFG4_LWPME 0x10 434176754Syongari 435176754Syongari/* 436176754Syongari * Config 5 register 437176754Syongari */ 438176754Syongari#define RL_CFG5_WOL_BCAST 0x40 439176754Syongari#define RL_CFG5_WOL_MCAST 0x20 440176754Syongari#define RL_CFG5_WOL_UCAST 0x10 441176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 442176754Syongari#define RL_CFG5_PME_STS 0x01 443176754Syongari 444176754Syongari/* 445117388Swpaul * 8139C+ register definitions 446117388Swpaul */ 447117388Swpaul 448117388Swpaul/* RL_DUMPSTATS_LO register */ 449117388Swpaul 450117388Swpaul#define RL_DUMPSTATS_START 0x00000008 451117388Swpaul 452117388Swpaul/* Transmit start register */ 453117388Swpaul 454117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 455117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 456117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 457117388Swpaul 458120043Swpaul/* 459120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 460120043Swpaul */ 461120043Swpaul#define RL_CFG2_BUSFREQ 0x07 462120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 463120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 464120043Swpaul 465120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 466120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 467120043Swpaul 468120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 469120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 470120043Swpaul 471117388Swpaul/* C+ mode command register */ 472117388Swpaul 473117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 474117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 475117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 476117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 477117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 478117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 479180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 480180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 481180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 482180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 483180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 484180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 485180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 486180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 487180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 488117388Swpaul 489117388Swpaul/* C+ early transmit threshold */ 490117388Swpaul 491117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 492117388Swpaul 493117388Swpaul/* 494117388Swpaul * Gigabit PHY access register (8169 only) 495117388Swpaul */ 496117388Swpaul 497117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 498117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 499117388Swpaul#define RL_PHYAR_BUSY 0x80000000 500117388Swpaul 501117388Swpaul/* 502117388Swpaul * Gigabit media status (8169 only) 503117388Swpaul */ 504117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 505117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 506117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 507117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 508119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 509117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 510117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 511117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 512117388Swpaul 513117388Swpaul/* 51440516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 51540516Swpaul * Instead, there are only four register sets, each or which represents 51640516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 51740516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 51840516Swpaul * the registers so the chip knows where they are. 51940516Swpaul * 52040516Swpaul * We can sort of kludge together the same kind of buffer management 52140516Swpaul * used in previous drivers, but we have to do buffer copies almost all 52240516Swpaul * the time, so it doesn't really buy us much. 52340516Swpaul * 52440516Swpaul * For reception, there's just one large buffer where the chip stores 52540516Swpaul * all received packets. 52640516Swpaul */ 52740516Swpaul 52840516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 52940516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 53040516Swpaul#define RL_TX_LIST_CNT 4 53140516Swpaul#define RL_MIN_FRAMELEN 60 532184240Syongari#define RL_TX_8139_BUF_ALIGN 4 533184240Syongari#define RL_RX_8139_BUF_ALIGN 8 534184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 535184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 536184240Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 53752426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 53852426Swpaul#define RL_TX_THRESH_INIT 96 539119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 540119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 54150703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 54240516Swpaul 54345633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 54445633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 54540516Swpaul 54648028Swpaul#define RL_ETHER_ALIGN 2 54748028Swpaul 548177771Syongari/* 549177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 550177771Syongari */ 551177771Syongari#define RL_IP4CSUMTX_MINLEN 28 552177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 553177771Syongari 55440516Swpaulstruct rl_chain_data { 555131605Sbms uint16_t cur_rx; 556131605Sbms uint8_t *rl_rx_buf; 557131605Sbms uint8_t *rl_rx_buf_ptr; 55840516Swpaul 55945633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 56081713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 561184240Syongari bus_dma_tag_t rl_tx_tag; 562184240Syongari bus_dma_tag_t rl_rx_tag; 563184240Syongari bus_dmamap_t rl_rx_dmamap; 564184240Syongari bus_addr_t rl_rx_buf_paddr; 565131605Sbms uint8_t last_tx; 566131605Sbms uint8_t cur_tx; 56740516Swpaul}; 56840516Swpaul 56945633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 57045633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 57145633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 57245633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 57381713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 57445633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 57545633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 57645633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 57781713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 57845633Swpaul 57940516Swpaulstruct rl_type { 580131605Sbms uint16_t rl_vid; 581131605Sbms uint16_t rl_did; 582117388Swpaul int rl_basetype; 58340516Swpaul char *rl_name; 58440516Swpaul}; 58540516Swpaul 586117388Swpaulstruct rl_hwrev { 587131605Sbms uint32_t rl_rev; 588117388Swpaul int rl_type; 589117388Swpaul char *rl_desc; 590117388Swpaul}; 591117388Swpaul 59240516Swpaulstruct rl_mii_frame { 593131605Sbms uint8_t mii_stdelim; 594131605Sbms uint8_t mii_opcode; 595131605Sbms uint8_t mii_phyaddr; 596131605Sbms uint8_t mii_regaddr; 597131605Sbms uint8_t mii_turnaround; 598131605Sbms uint16_t mii_data; 59940516Swpaul}; 60040516Swpaul 60140516Swpaul/* 60240516Swpaul * MII constants 60340516Swpaul */ 60440516Swpaul#define RL_MII_STARTDELIM 0x01 60540516Swpaul#define RL_MII_READOP 0x02 60640516Swpaul#define RL_MII_WRITEOP 0x01 60740516Swpaul#define RL_MII_TURNAROUND 0x02 60840516Swpaul 60940516Swpaul#define RL_8129 1 61040516Swpaul#define RL_8139 2 611117388Swpaul#define RL_8139CPLUS 3 612117388Swpaul#define RL_8169 4 61340516Swpaul 614117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 615117388Swpaul (x)->rl_type == RL_8169) 616117388Swpaul 617117388Swpaul/* 618117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 619117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 620117388Swpaul * must be allocated in contiguous blocks that are aligned on a 621117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 622117388Swpaul */ 623117388Swpaul 624117388Swpaul/* 625117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 626117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 627117388Swpaul * the checksum offload bits are disabled. The structure layout is 628117388Swpaul * the same for RX and TX descriptors 629117388Swpaul */ 630117388Swpaul 631117388Swpaulstruct rl_desc { 632131605Sbms uint32_t rl_cmdstat; 633131605Sbms uint32_t rl_vlanctl; 634131605Sbms uint32_t rl_bufaddr_lo; 635131605Sbms uint32_t rl_bufaddr_hi; 636117388Swpaul}; 637117388Swpaul 638117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 639117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 640117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 641117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 642117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 643164463Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 644117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 645117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 646117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 647117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 648117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 649117388Swpaul 650117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 651117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 652180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 653180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 654180176Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 655180176Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 656117388Swpaul 657117388Swpaul/* 658117388Swpaul * Error bits are valid only on the last descriptor of a frame 659117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 660117388Swpaul */ 661117388Swpaul 662117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 663117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 664117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 665117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 666117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 667117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 668117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 669117388Swpaul 670117388Swpaul/* 671117388Swpaul * RX descriptor cmd/vlan definitions 672117388Swpaul */ 673117388Swpaul 674117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 675117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 676119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 677117388Swpaul 678117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 679117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 680117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 681117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 682117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 683117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 684117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 685117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 686117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 687117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 688117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 689117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 690117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 691117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 692117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 693180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 694180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 695117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 696117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 697117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 698119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 699119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 700135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 701135896Sjmg RL_RDESC_STAT_CRCERR) 702117388Swpaul 703117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 704117388Swpaul (rl_vlandata valid)*/ 705117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 706180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 707180176Syongari#define RL_RDESC_IPV6 0x80000000 708180176Syongari#define RL_RDESC_IPV4 0x40000000 709117388Swpaul 710117388Swpaul#define RL_PROTOID_NONIP 0x00000000 711117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 712117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 713117388Swpaul#define RL_PROTOID_IP 0x00030000 714117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 715117388Swpaul RL_PROTOID_TCPIP) 716117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 717117388Swpaul RL_PROTOID_UDPIP) 718117388Swpaul 719117388Swpaul/* 720117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 721117388Swpaul */ 722117388Swpaulstruct rl_stats { 723131605Sbms uint32_t rl_tx_pkts_lo; 724131605Sbms uint32_t rl_tx_pkts_hi; 725131605Sbms uint32_t rl_tx_errs_lo; 726131605Sbms uint32_t rl_tx_errs_hi; 727131605Sbms uint32_t rl_tx_errs; 728131605Sbms uint16_t rl_missed_pkts; 729131605Sbms uint16_t rl_rx_framealign_errs; 730131605Sbms uint32_t rl_tx_onecoll; 731131605Sbms uint32_t rl_tx_multicolls; 732131605Sbms uint32_t rl_rx_ucasts_hi; 733131605Sbms uint32_t rl_rx_ucasts_lo; 734131605Sbms uint32_t rl_rx_bcasts_lo; 735131605Sbms uint32_t rl_rx_bcasts_hi; 736131605Sbms uint32_t rl_rx_mcasts; 737131605Sbms uint16_t rl_tx_aborts; 738131605Sbms uint16_t rl_rx_underruns; 739117388Swpaul}; 740117388Swpaul 741135467Sjmg/* 742135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 743135467Sjmg * 744175337Syongari * 8139C+ 745175337Syongari * Number of descriptors supported : up to 64 746175337Syongari * Descriptor alignment : 256 bytes 747175337Syongari * Tx buffer : At least 4 bytes in length. 748175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 749175337Syongari * 750175337Syongari * 8169 751175337Syongari * Number of descriptors supported : up to 1024 752175337Syongari * Descriptor alignment : 256 bytes 753175337Syongari * Tx buffer : At least 4 bytes in length. 754175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 755135467Sjmg */ 756164460Syongari#ifndef __NO_STRICT_ALIGNMENT 757135896Sjmg#define RE_FIXUP_RX 1 758135896Sjmg#endif 759135896Sjmg 760175337Syongari#define RL_8169_TX_DESC_CNT 256 761175337Syongari#define RL_8169_RX_DESC_CNT 256 762175337Syongari#define RL_8139_TX_DESC_CNT 64 763175337Syongari#define RL_8139_RX_DESC_CNT 64 764175337Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 765175337Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 766175337Syongari#define RL_NTXSEGS 32 767159962Swpaul 768117388Swpaul#define RL_RING_ALIGN 256 769117388Swpaul#define RL_IFQ_MAXLEN 512 770175337Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 771175337Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 772175337Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 773117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 774119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 775119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 776135896Sjmg#ifdef RE_FIXUP_RX 777135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 778135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 779135896Sjmg#else 780135896Sjmg#define RE_ETHER_ALIGN 0 781135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 782135896Sjmg#endif 783117388Swpaul 784188474Syongari#define RL_MSI_MESSAGES 1 785171560Syongari 786135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 787135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 788118712Swpaul 789181270Syongari/* 790181270Syongari * The number of bits reserved for MSS in RealTek controllers is 791181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 792181270Syongari * as upper stack should not generate TCP segments with MSS greater 793181270Syongari * than the limit. 794181270Syongari */ 795181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 796181270Syongari 797135896Sjmg/* see comment in dev/re/if_re.c */ 798135896Sjmg#define RL_JUMBO_FRAMELEN 7440 799119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 800176756Syongari#define RL_MAX_FRAMELEN \ 801176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 802119868Swpaul 803175337Syongaristruct rl_txdesc { 804175337Syongari struct mbuf *tx_m; 805175337Syongari bus_dmamap_t tx_dmamap; 806175337Syongari}; 807117388Swpaul 808175337Syongaristruct rl_rxdesc { 809175337Syongari struct mbuf *rx_m; 810175337Syongari bus_dmamap_t rx_dmamap; 811175337Syongari bus_size_t rx_size; 812117388Swpaul}; 813117388Swpaul 814117388Swpaulstruct rl_list_data { 815175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 816175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 817175337Syongari int rl_tx_desc_cnt; 818175337Syongari int rl_rx_desc_cnt; 819117388Swpaul int rl_tx_prodidx; 820117388Swpaul int rl_rx_prodidx; 821117388Swpaul int rl_tx_considx; 822117388Swpaul int rl_tx_free; 823175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 824175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 825175337Syongari bus_dmamap_t rl_rx_sparemap; 826117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 827117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 828117388Swpaul struct rl_stats *rl_stats; 829118712Swpaul bus_addr_t rl_stats_addr; 830117388Swpaul bus_dma_tag_t rl_rx_list_tag; 831117388Swpaul bus_dmamap_t rl_rx_list_map; 832117388Swpaul struct rl_desc *rl_rx_list; 833118712Swpaul bus_addr_t rl_rx_list_addr; 834117388Swpaul bus_dma_tag_t rl_tx_list_tag; 835117388Swpaul bus_dmamap_t rl_tx_list_map; 836117388Swpaul struct rl_desc *rl_tx_list; 837118712Swpaul bus_addr_t rl_tx_list_addr; 838117388Swpaul}; 839117388Swpaul 840184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 841184515Simp 84240516Swpaulstruct rl_softc { 843147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 84441569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 84541569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 846159962Swpaul device_t rl_dev; 84750703Swpaul struct resource *rl_res; 848180169Syongari int rl_res_id; 849180169Syongari int rl_res_type; 850171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 851171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 85250703Swpaul device_t rl_miibus; 85381713Swpaul bus_dma_tag_t rl_parent_tag; 854131605Sbms uint8_t rl_type; 85567931Swpaul int rl_eecmd_read; 856159962Swpaul int rl_eewidth; 857131605Sbms uint8_t rl_stats_no_timeout; 85852426Swpaul int rl_txthresh; 85940516Swpaul struct rl_chain_data rl_cdata; 860117388Swpaul struct rl_list_data rl_ldata; 861150720Sjhb struct callout rl_stat_callout; 862164811Sru int rl_watchdog_timer; 86367087Swpaul struct mtx rl_mtx; 864119868Swpaul struct mbuf *rl_head; 865119868Swpaul struct mbuf *rl_tail; 866131605Sbms uint32_t rl_hwrev; 867131605Sbms uint32_t rl_rxlenmask; 868119868Swpaul int rl_testmode; 869168828Syongari int rl_if_flags; 870184559Simp int rl_twister_enable; 871184515Simp enum rl_twist rl_twister; 872184515Simp int rl_twist_row; 873184515Simp int rl_twist_col; 87486822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 87594883Sluigi#ifdef DEVICE_POLLING 87694883Sluigi int rxcycles; 87794883Sluigi#endif 878159962Swpaul 879159962Swpaul struct task rl_txtask; 880159962Swpaul struct task rl_inttask; 881159962Swpaul 882159962Swpaul int rl_txstart; 883180171Syongari uint32_t rl_flags; 884180171Syongari#define RL_FLAG_MSI 0x0001 885191301Syongari#define RL_FLAG_AUTOPAD 0x0002 886180171Syongari#define RL_FLAG_PHYWAKE 0x0008 887180171Syongari#define RL_FLAG_NOJUMBO 0x0010 888180176Syongari#define RL_FLAG_PAR 0x0020 889180176Syongari#define RL_FLAG_DESCV2 0x0040 890180176Syongari#define RL_FLAG_MACSTAT 0x0080 891185753Syongari#define RL_FLAG_FASTETHER 0x0100 892185900Syongari#define RL_FLAG_CMDSTOP 0x0200 893187483Sjkim#define RL_FLAG_MACRESET 0x0400 894185903Syongari#define RL_FLAG_WOLRXENB 0x1000 895186210Syongari#define RL_FLAG_MACSLEEP 0x2000 896186214Syongari#define RL_FLAG_PCIE 0x4000 897180171Syongari#define RL_FLAG_LINK 0x8000 89840516Swpaul}; 89940516Swpaul 90072200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 90172200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 902122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 90367087Swpaul 90440516Swpaul/* 90540516Swpaul * register space access macros 90640516Swpaul */ 907119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 908119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 90940516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 91041569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 91140516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 91241569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 91340516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 91441569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 91540516Swpaul 91641569Swpaul#define CSR_READ_4(sc, reg) \ 91741569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 91841569Swpaul#define CSR_READ_2(sc, reg) \ 91941569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 92041569Swpaul#define CSR_READ_1(sc, reg) \ 92141569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 92240516Swpaul 923159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 924159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 925159962Swpaul 926159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 927159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 928159962Swpaul 929159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 930159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 931159962Swpaul 932159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 933159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 934159962Swpaul 935159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 936159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 937159962Swpaul 938159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 939159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 940159962Swpaul 94140516Swpaul#define RL_TIMEOUT 1000 942187417Syongari#define RL_PHY_TIMEOUT 2000 94340516Swpaul 94440516Swpaul/* 94540516Swpaul * General constants that are fun to know. 94640516Swpaul * 94740516Swpaul * RealTek PCI vendor ID 94840516Swpaul */ 94940516Swpaul#define RT_VENDORID 0x10EC 95040516Swpaul 95140516Swpaul/* 95240516Swpaul * RealTek chip device IDs. 95340516Swpaul */ 954179831Sremko#define RT_DEVICEID_8139D 0x8039 95540516Swpaul#define RT_DEVICEID_8129 0x8129 956159962Swpaul#define RT_DEVICEID_8101E 0x8136 95767771Swpaul#define RT_DEVICEID_8138 0x8138 95840516Swpaul#define RT_DEVICEID_8139 0x8139 959159962Swpaul#define RT_DEVICEID_8169SC 0x8167 960159962Swpaul#define RT_DEVICEID_8168 0x8168 961117388Swpaul#define RT_DEVICEID_8169 0x8169 962118978Swpaul#define RT_DEVICEID_8100 0x8100 96340516Swpaul 964117388Swpaul#define RT_REVID_8139CPLUS 0x20 965117388Swpaul 96640516Swpaul/* 96744238Swpaul * Accton PCI vendor ID 96844238Swpaul */ 96944238Swpaul#define ACCTON_VENDORID 0x1113 97044238Swpaul 97144238Swpaul/* 97241243Swpaul * Accton MPX 5030/5038 device ID. 97341243Swpaul */ 97441243Swpaul#define ACCTON_DEVICEID_5030 0x1211 97541243Swpaul 97641243Swpaul/* 97794400Swpaul * Nortel PCI vendor ID 97894400Swpaul */ 97994400Swpaul#define NORTEL_VENDORID 0x126C 98094400Swpaul 98194400Swpaul/* 98244238Swpaul * Delta Electronics Vendor ID. 98344238Swpaul */ 98444238Swpaul#define DELTA_VENDORID 0x1500 98544238Swpaul 98644238Swpaul/* 98744238Swpaul * Delta device IDs. 98844238Swpaul */ 98944238Swpaul#define DELTA_DEVICEID_8139 0x1360 99044238Swpaul 99144238Swpaul/* 99244238Swpaul * Addtron vendor ID. 99344238Swpaul */ 99444238Swpaul#define ADDTRON_VENDORID 0x4033 99544238Swpaul 99644238Swpaul/* 99744238Swpaul * Addtron device IDs. 99844238Swpaul */ 99944238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 100044238Swpaul 100144238Swpaul/* 100272813Swpaul * D-Link vendor ID. 100372813Swpaul */ 100472813Swpaul#define DLINK_VENDORID 0x1186 100572813Swpaul 100672813Swpaul/* 100772813Swpaul * D-Link DFE-530TX+ device ID 100872813Swpaul */ 100972813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 101072813Swpaul 101172813Swpaul/* 1012148722Stobez * D-Link DFE-5280T device ID 1013148722Stobez */ 1014148722Stobez#define DLINK_DEVICEID_528T 0x4300 1015148722Stobez 1016148722Stobez/* 101796112Sjhb * D-Link DFE-690TXD device ID 101896112Sjhb */ 101996112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 102096112Sjhb 102196112Sjhb/* 1022103020Siwasaki * Corega K.K vendor ID 1023103020Siwasaki */ 1024103020Siwasaki#define COREGA_VENDORID 0x1259 1025103020Siwasaki 1026103020Siwasaki/* 1027109095Ssanpei * Corega FEther CB-TXD device ID 1028103020Siwasaki */ 1029151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1030103020Siwasaki 1031103020Siwasaki/* 1032109095Ssanpei * Corega FEtherII CB-TXD device ID 1033109095Ssanpei */ 1034151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1035109095Ssanpei 1036111381Sdan/* 1037134433Ssanpei * Corega CG-LAPCIGT device ID 1038134433Ssanpei */ 1039134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1040134433Ssanpei 1041134433Ssanpei/* 1042151341Sjhb * Linksys vendor ID 1043151341Sjhb */ 1044151341Sjhb#define LINKSYS_VENDORID 0x1737 1045151341Sjhb 1046151341Sjhb/* 1047151341Sjhb * Linksys EG1032 device ID 1048151341Sjhb */ 1049151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 1050151341Sjhb 1051151341Sjhb/* 1052151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1053151341Sjhb */ 1054151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1055151341Sjhb 1056151341Sjhb/* 1057111381Sdan * Peppercon vendor ID 1058111381Sdan */ 1059111381Sdan#define PEPPERCON_VENDORID 0x1743 1060109095Ssanpei 1061111381Sdan/* 1062111381Sdan * Peppercon ROL-F device ID 1063111381Sdan */ 1064111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 1065109095Ssanpei 1066109095Ssanpei/* 1067112379Ssanpei * Planex Communications, Inc. vendor ID 1068112379Ssanpei */ 1069117388Swpaul#define PLANEX_VENDORID 0x14ea 1070112379Ssanpei 1071112379Ssanpei/* 1072173948Sremko * Planex FNW-3603-TX device ID 1073173948Sremko */ 1074173948Sremko#define PLANEX_DEVICEID_FNW3603TX 0xab06 1075173948Sremko 1076173948Sremko/* 1077112379Ssanpei * Planex FNW-3800-TX device ID 1078112379Ssanpei */ 1079117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 1080112379Ssanpei 1081112379Ssanpei/* 1082117388Swpaul * LevelOne vendor ID 1083117388Swpaul */ 1084117388Swpaul#define LEVEL1_VENDORID 0x018A 1085117388Swpaul 1086117388Swpaul/* 1087117388Swpaul * LevelOne FPC-0106TX devide ID 1088117388Swpaul */ 1089117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1090117388Swpaul 1091117388Swpaul/* 1092117388Swpaul * Compaq vendor ID 1093117388Swpaul */ 1094117388Swpaul#define CP_VENDORID 0x021B 1095117388Swpaul 1096117388Swpaul/* 1097117388Swpaul * Edimax vendor ID 1098117388Swpaul */ 1099117388Swpaul#define EDIMAX_VENDORID 0x13D1 1100117388Swpaul 1101117388Swpaul/* 1102117388Swpaul * Edimax EP-4103DL cardbus device ID 1103117388Swpaul */ 1104117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1105117388Swpaul 1106160883Swpaul/* US Robotics vendor ID */ 1107160883Swpaul 1108160883Swpaul#define USR_VENDORID 0x16EC 1109160883Swpaul 1110160883Swpaul/* US Robotics 997902 device ID */ 1111160883Swpaul 1112160883Swpaul#define USR_DEVICEID_997902 0x0116 1113160883Swpaul 1114117388Swpaul/* 111540516Swpaul * PCI low memory base and low I/O base register, and 111650703Swpaul * other PCI registers. 111740516Swpaul */ 111840516Swpaul 111940516Swpaul#define RL_PCI_VENDOR_ID 0x00 112040516Swpaul#define RL_PCI_DEVICE_ID 0x02 112140516Swpaul#define RL_PCI_COMMAND 0x04 112240516Swpaul#define RL_PCI_STATUS 0x06 112340516Swpaul#define RL_PCI_CLASSCODE 0x09 112440516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 112540516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 112640516Swpaul#define RL_PCI_LOIO 0x10 112740516Swpaul#define RL_PCI_LOMEM 0x14 112840516Swpaul#define RL_PCI_BIOSROM 0x30 112940516Swpaul#define RL_PCI_INTLINE 0x3C 113040516Swpaul#define RL_PCI_INTPIN 0x3D 113140516Swpaul#define RL_PCI_MINGNT 0x3E 113240516Swpaul#define RL_PCI_MINLAT 0x0F 113340516Swpaul#define RL_PCI_RESETOPT 0x48 113440516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 113540516Swpaul 113650097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 113750097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 113850097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 113950097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 114040516Swpaul 114140516Swpaul#define RL_PSTATE_MASK 0x0003 114240516Swpaul#define RL_PSTATE_D0 0x0000 114340516Swpaul#define RL_PSTATE_D1 0x0002 114440516Swpaul#define RL_PSTATE_D2 0x0002 114540516Swpaul#define RL_PSTATE_D3 0x0003 114640516Swpaul#define RL_PME_EN 0x0010 114740516Swpaul#define RL_PME_STATUS 0x8000 1148