if_rlreg.h revision 184515
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 184515 2008-10-31 23:24:13Z imp $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 8440516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 8640516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8740516Swpaul#define RL_HALTCLK 0x005B 8840516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8940516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 9140516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 9440516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9540516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9640516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9740516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9840516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 10040516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 10140516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 10240516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 10340516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10440516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117120043Swpaul#define RL_CFG2 0x0053 118117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 120117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129117388Swpaul#define RL_PHYAR 0x0060 130117388Swpaul#define RL_TBICSR 0x0064 131117388Swpaul#define RL_TBI_ANAR 0x0068 132117388Swpaul#define RL_TBI_LPAR 0x006A 133117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135175337Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 136117388Swpaul 137117388Swpaul/* 13840516Swpaul * TX config register bits 13940516Swpaul */ 14040516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 14145633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 14240516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 14345633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14545633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14740516Swpaul 148119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 149119868Swpaul#define RL_LOOPTEST_ON 0x00020000 150119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 151119868Swpaul 152159962Swpaul/* Known revision codes. */ 153117388Swpaul 154160843Swpaul#define RL_HWREV_8169 0x00000000 155160843Swpaul#define RL_HWREV_8110S 0x00800000 156160843Swpaul#define RL_HWREV_8169S 0x04000000 157160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 158160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 159180377Syongari#define RL_HWREV_8102EL 0x24800000 160160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 161160843Swpaul#define RL_HWREV_8100E 0x30800000 162160843Swpaul#define RL_HWREV_8101E 0x34000000 163180377Syongari#define RL_HWREV_8102E 0x34800000 164160843Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 165174428Syongari#define RL_HWREV_8168_SPIN3 0x38400000 166180176Syongari#define RL_HWREV_8168C 0x3C000000 167180176Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 168180176Syongari#define RL_HWREV_8168CP 0x3C800000 169160843Swpaul#define RL_HWREV_8139 0x60000000 170160843Swpaul#define RL_HWREV_8139A 0x70000000 171160843Swpaul#define RL_HWREV_8139AG 0x70800000 172160843Swpaul#define RL_HWREV_8139B 0x78000000 173160843Swpaul#define RL_HWREV_8130 0x7C000000 174160843Swpaul#define RL_HWREV_8139C 0x74000000 175160843Swpaul#define RL_HWREV_8139D 0x74400000 176160843Swpaul#define RL_HWREV_8139CPLUS 0x74800000 177160843Swpaul#define RL_HWREV_8101 0x74c00000 178160843Swpaul#define RL_HWREV_8100 0x78800000 179180177Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 180159962Swpaul 18145633Swpaul#define RL_TXDMA_16BYTES 0x00000000 18245633Swpaul#define RL_TXDMA_32BYTES 0x00000100 18345633Swpaul#define RL_TXDMA_64BYTES 0x00000200 18445633Swpaul#define RL_TXDMA_128BYTES 0x00000300 18545633Swpaul#define RL_TXDMA_256BYTES 0x00000400 18645633Swpaul#define RL_TXDMA_512BYTES 0x00000500 18745633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 18845633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 18945633Swpaul 19040516Swpaul/* 19140516Swpaul * Transmit descriptor status register bits. 19240516Swpaul */ 19340516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 19440516Swpaul#define RL_TXSTAT_OWN 0x00002000 19540516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 19640516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 19740516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 19840516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 19940516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 20040516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 20140516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 20240516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 20340516Swpaul 20440516Swpaul/* 20540516Swpaul * Interrupt status register bits. 20640516Swpaul */ 20740516Swpaul#define RL_ISR_RX_OK 0x0001 20840516Swpaul#define RL_ISR_RX_ERR 0x0002 20940516Swpaul#define RL_ISR_TX_OK 0x0004 21040516Swpaul#define RL_ISR_TX_ERR 0x0008 21140516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 21240516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 213119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 21440516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 215117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 216117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 217117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 21840516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 219117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 22040516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 22140516Swpaul 22240516Swpaul#define RL_INTRS \ 22340516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 22440516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 22540516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 22640516Swpaul 227159962Swpaul#ifdef RE_TX_MODERATION 228117388Swpaul#define RL_INTRS_CPLUS \ 229119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 230117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 231117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 232159962Swpaul#else 233159962Swpaul#define RL_INTRS_CPLUS \ 234159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 235159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 236159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 237159962Swpaul#endif 238117388Swpaul 23940516Swpaul/* 24040516Swpaul * Media status register. (8139 only) 24140516Swpaul */ 24240516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 24340516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 24440516Swpaul#define RL_MEDIASTAT_LINK 0x04 24540516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 24640516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 24740516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 24840516Swpaul 24940516Swpaul/* 25040516Swpaul * Receive config register. 25140516Swpaul */ 25240516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 25340516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 25440516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 25540516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 25640516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 25740516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 25840516Swpaul#define RL_RXCFG_WRAP 0x00000080 25945633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 26045633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 26145633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 26245633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 26340516Swpaul 26445633Swpaul#define RL_RXDMA_16BYTES 0x00000000 26545633Swpaul#define RL_RXDMA_32BYTES 0x00000100 26645633Swpaul#define RL_RXDMA_64BYTES 0x00000200 26745633Swpaul#define RL_RXDMA_128BYTES 0x00000300 26845633Swpaul#define RL_RXDMA_256BYTES 0x00000400 26945633Swpaul#define RL_RXDMA_512BYTES 0x00000500 27045633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 27145633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 27245633Swpaul 27340516Swpaul#define RL_RXBUF_8 0x00000000 27440516Swpaul#define RL_RXBUF_16 0x00000800 27540516Swpaul#define RL_RXBUF_32 0x00001000 27645633Swpaul#define RL_RXBUF_64 0x00001800 27740516Swpaul 27845633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 27945633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 28045633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 28145633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 28245633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 28345633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 28445633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 28545633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 28645633Swpaul 28740516Swpaul/* 28840516Swpaul * Bits in RX status header (included with RX'ed packet 28940516Swpaul * in ring buffer). 29040516Swpaul */ 29140516Swpaul#define RL_RXSTAT_RXOK 0x00000001 29240516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 29340516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 29440516Swpaul#define RL_RXSTAT_GIANT 0x00000008 29540516Swpaul#define RL_RXSTAT_RUNT 0x00000010 29640516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 29740516Swpaul#define RL_RXSTAT_BROAD 0x00002000 29840516Swpaul#define RL_RXSTAT_INDIV 0x00004000 29940516Swpaul#define RL_RXSTAT_MULTI 0x00008000 30040516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 30140516Swpaul 30240516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 30340516Swpaul/* 30440516Swpaul * Command register. 30540516Swpaul */ 30640516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 30740516Swpaul#define RL_CMD_TX_ENB 0x0004 30840516Swpaul#define RL_CMD_RX_ENB 0x0008 30940516Swpaul#define RL_CMD_RESET 0x0010 31040516Swpaul 31140516Swpaul/* 312184515Simp * Twister register values. These are completely undocumented and derived 313184515Simp * from public sources. 314184515Simp */ 315184515Simp#define RL_CSCFG_LINK_OK 0x0400 316184515Simp#define RL_CSCFG_CHANGE 0x0800 317184515Simp#define RL_CSCFG_STATUS 0xf000 318184515Simp#define RL_CSCFG_ROW3 0x7000 319184515Simp#define RL_CSCFG_ROW2 0x3000 320184515Simp#define RL_CSCFG_ROW1 0x1000 321184515Simp#define RL_CSCFG_LINK_DOWN_OFF_CMD 0x03c0 322184515Simp#define RL_CSCFG_LINK_DOWN_CMD 0xf3c0 323184515Simp 324184515Simp#define RL_NWAYTST_RESET 0 325184515Simp#define RL_NWAYTST_CBL_TEST 0x20 326184515Simp 327184515Simp#define RL_PARA78 0x78 328184515Simp#define RL_PARA78_DEF 0x78fa8388 329184515Simp#define RL_PARA7C 0x7C 330184515Simp#define RL_PARA7C_DEF 0xcb38de43 331184515Simp#define RL_PARA7C_RETUNE 0xfb38de03 332184515Simp/* 33340516Swpaul * EEPROM control register 33440516Swpaul */ 33540516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 33640516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 33740516Swpaul#define RL_EE_CLK 0x04 /* clock */ 33840516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 33940516Swpaul#define RL_EE_MODE (0x40|0x80) 34040516Swpaul 34140516Swpaul#define RL_EEMODE_OFF 0x00 34240516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 34340516Swpaul#define RL_EEMODE_PROGRAM 0x80 34440516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 34540516Swpaul 34640516Swpaul/* 9346 EEPROM commands */ 347171263Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 348171263Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 349159962Swpaul 350159962Swpaul#define RL_9346_WRITE 0x5 351159962Swpaul#define RL_9346_READ 0x6 352159962Swpaul#define RL_9346_ERASE 0x7 353159962Swpaul#define RL_9346_EWEN 0x4 354159962Swpaul#define RL_9346_EWEN_ADDR 0x30 355159962Swpaul#define RL_9456_EWDS 0x4 356159962Swpaul#define RL_9346_EWDS_ADDR 0x00 357159962Swpaul 35840516Swpaul#define RL_EECMD_WRITE 0x140 35967931Swpaul#define RL_EECMD_READ_6BIT 0x180 36067931Swpaul#define RL_EECMD_READ_8BIT 0x600 36140516Swpaul#define RL_EECMD_ERASE 0x1c0 36240516Swpaul 36340516Swpaul#define RL_EE_ID 0x00 36440516Swpaul#define RL_EE_PCI_VID 0x01 36540516Swpaul#define RL_EE_PCI_DID 0x02 36640516Swpaul/* Location of station address inside EEPROM */ 36740516Swpaul#define RL_EE_EADDR 0x07 36840516Swpaul 36940516Swpaul/* 37040516Swpaul * MII register (8129 only) 37140516Swpaul */ 37240516Swpaul#define RL_MII_CLK 0x01 37340516Swpaul#define RL_MII_DATAIN 0x02 37440516Swpaul#define RL_MII_DATAOUT 0x04 37540516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 37640516Swpaul 37740516Swpaul/* 37840516Swpaul * Config 0 register 37940516Swpaul */ 38040516Swpaul#define RL_CFG0_ROM0 0x01 38140516Swpaul#define RL_CFG0_ROM1 0x02 38240516Swpaul#define RL_CFG0_ROM2 0x04 38340516Swpaul#define RL_CFG0_PL0 0x08 38440516Swpaul#define RL_CFG0_PL1 0x10 38540516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 38640516Swpaul#define RL_CFG0_PCS 0x40 38740516Swpaul#define RL_CFG0_SCR 0x80 38840516Swpaul 38940516Swpaul/* 39040516Swpaul * Config 1 register 39140516Swpaul */ 39240516Swpaul#define RL_CFG1_PWRDWN 0x01 393176754Syongari#define RL_CFG1_PME 0x01 39440516Swpaul#define RL_CFG1_SLEEP 0x02 395176754Syongari#define RL_CFG1_VPDEN 0x02 39640516Swpaul#define RL_CFG1_IOMAP 0x04 39740516Swpaul#define RL_CFG1_MEMMAP 0x08 39840516Swpaul#define RL_CFG1_RSVD 0x10 399176754Syongari#define RL_CFG1_LWACT 0x10 40040516Swpaul#define RL_CFG1_DRVLOAD 0x20 40140516Swpaul#define RL_CFG1_LED0 0x40 40240516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 40340516Swpaul#define RL_CFG1_LED1 0x80 40440516Swpaul 40540516Swpaul/* 406176754Syongari * Config 2 register 407176754Syongari */ 408176754Syongari#define RL_CFG2_PCI33MHZ 0x00 409176754Syongari#define RL_CFG2_PCI66MHZ 0x01 410176754Syongari#define RL_CFG2_PCI64BIT 0x08 411176754Syongari#define RL_CFG2_AUXPWR 0x10 412177522Syongari#define RL_CFG2_MSI 0x20 413176754Syongari 414176754Syongari/* 415176754Syongari * Config 3 register 416176754Syongari */ 417176754Syongari#define RL_CFG3_GRANTSEL 0x80 418176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 419176754Syongari#define RL_CFG3_WOL_LINK 0x10 420176754Syongari#define RL_CFG3_FAST_B2B 0x01 421176754Syongari 422176754Syongari/* 423176754Syongari * Config 4 register 424176754Syongari */ 425176754Syongari#define RL_CFG4_LWPTN 0x04 426176754Syongari#define RL_CFG4_LWPME 0x10 427176754Syongari 428176754Syongari/* 429176754Syongari * Config 5 register 430176754Syongari */ 431176754Syongari#define RL_CFG5_WOL_BCAST 0x40 432176754Syongari#define RL_CFG5_WOL_MCAST 0x20 433176754Syongari#define RL_CFG5_WOL_UCAST 0x10 434176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 435176754Syongari#define RL_CFG5_PME_STS 0x01 436176754Syongari 437176754Syongari/* 438117388Swpaul * 8139C+ register definitions 439117388Swpaul */ 440117388Swpaul 441117388Swpaul/* RL_DUMPSTATS_LO register */ 442117388Swpaul 443117388Swpaul#define RL_DUMPSTATS_START 0x00000008 444117388Swpaul 445117388Swpaul/* Transmit start register */ 446117388Swpaul 447117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 448117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 449117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 450117388Swpaul 451120043Swpaul/* 452120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 453120043Swpaul */ 454120043Swpaul#define RL_CFG2_BUSFREQ 0x07 455120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 456120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 457120043Swpaul 458120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 459120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 460120043Swpaul 461120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 462120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 463120043Swpaul 464117388Swpaul/* C+ mode command register */ 465117388Swpaul 466117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 467117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 468117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 469117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 470117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 471117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 472180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 473180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 474180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 475180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 476180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 477180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 478180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 479180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 480180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 481117388Swpaul 482117388Swpaul/* C+ early transmit threshold */ 483117388Swpaul 484117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 485117388Swpaul 486117388Swpaul/* 487117388Swpaul * Gigabit PHY access register (8169 only) 488117388Swpaul */ 489117388Swpaul 490117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 491117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 492117388Swpaul#define RL_PHYAR_BUSY 0x80000000 493117388Swpaul 494117388Swpaul/* 495117388Swpaul * Gigabit media status (8169 only) 496117388Swpaul */ 497117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 498117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 499117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 500117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 501119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 502117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 503117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 504117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 505117388Swpaul 506117388Swpaul/* 50740516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 50840516Swpaul * Instead, there are only four register sets, each or which represents 50940516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 51040516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 51140516Swpaul * the registers so the chip knows where they are. 51240516Swpaul * 51340516Swpaul * We can sort of kludge together the same kind of buffer management 51440516Swpaul * used in previous drivers, but we have to do buffer copies almost all 51540516Swpaul * the time, so it doesn't really buy us much. 51640516Swpaul * 51740516Swpaul * For reception, there's just one large buffer where the chip stores 51840516Swpaul * all received packets. 51940516Swpaul */ 52040516Swpaul 52140516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 52240516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 52340516Swpaul#define RL_TX_LIST_CNT 4 52440516Swpaul#define RL_MIN_FRAMELEN 60 525184240Syongari#define RL_TX_8139_BUF_ALIGN 4 526184240Syongari#define RL_RX_8139_BUF_ALIGN 8 527184240Syongari#define RL_RX_8139_BUF_RESERVE sizeof(int64_t) 528184240Syongari#define RL_RX_8139_BUF_GUARD_SZ \ 529184240Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN + RL_RX_8139_BUF_RESERVE) 53052426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 53152426Swpaul#define RL_TX_THRESH_INIT 96 532119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 533119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 53450703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 53540516Swpaul 53645633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 53745633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 53840516Swpaul 53948028Swpaul#define RL_ETHER_ALIGN 2 54048028Swpaul 541177771Syongari/* 542177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 543177771Syongari */ 544177771Syongari#define RL_IP4CSUMTX_MINLEN 28 545177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 546177771Syongari 54740516Swpaulstruct rl_chain_data { 548131605Sbms uint16_t cur_rx; 549131605Sbms uint8_t *rl_rx_buf; 550131605Sbms uint8_t *rl_rx_buf_ptr; 55140516Swpaul 55245633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 55381713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 554184240Syongari bus_dma_tag_t rl_tx_tag; 555184240Syongari bus_dma_tag_t rl_rx_tag; 556184240Syongari bus_dmamap_t rl_rx_dmamap; 557184240Syongari bus_addr_t rl_rx_buf_paddr; 558131605Sbms uint8_t last_tx; 559131605Sbms uint8_t cur_tx; 56040516Swpaul}; 56140516Swpaul 56245633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 56345633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 56445633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 56545633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 56681713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 56745633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 56845633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 56945633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 57081713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 57145633Swpaul 57240516Swpaulstruct rl_type { 573131605Sbms uint16_t rl_vid; 574131605Sbms uint16_t rl_did; 575117388Swpaul int rl_basetype; 57640516Swpaul char *rl_name; 57740516Swpaul}; 57840516Swpaul 579117388Swpaulstruct rl_hwrev { 580131605Sbms uint32_t rl_rev; 581117388Swpaul int rl_type; 582117388Swpaul char *rl_desc; 583117388Swpaul}; 584117388Swpaul 58540516Swpaulstruct rl_mii_frame { 586131605Sbms uint8_t mii_stdelim; 587131605Sbms uint8_t mii_opcode; 588131605Sbms uint8_t mii_phyaddr; 589131605Sbms uint8_t mii_regaddr; 590131605Sbms uint8_t mii_turnaround; 591131605Sbms uint16_t mii_data; 59240516Swpaul}; 59340516Swpaul 59440516Swpaul/* 59540516Swpaul * MII constants 59640516Swpaul */ 59740516Swpaul#define RL_MII_STARTDELIM 0x01 59840516Swpaul#define RL_MII_READOP 0x02 59940516Swpaul#define RL_MII_WRITEOP 0x01 60040516Swpaul#define RL_MII_TURNAROUND 0x02 60140516Swpaul 60240516Swpaul#define RL_8129 1 60340516Swpaul#define RL_8139 2 604117388Swpaul#define RL_8139CPLUS 3 605117388Swpaul#define RL_8169 4 60640516Swpaul 607117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 608117388Swpaul (x)->rl_type == RL_8169) 609117388Swpaul 610117388Swpaul/* 611117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 612117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 613117388Swpaul * must be allocated in contiguous blocks that are aligned on a 614117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 615117388Swpaul */ 616117388Swpaul 617117388Swpaul/* 618117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 619117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 620117388Swpaul * the checksum offload bits are disabled. The structure layout is 621117388Swpaul * the same for RX and TX descriptors 622117388Swpaul */ 623117388Swpaul 624117388Swpaulstruct rl_desc { 625131605Sbms uint32_t rl_cmdstat; 626131605Sbms uint32_t rl_vlanctl; 627131605Sbms uint32_t rl_bufaddr_lo; 628131605Sbms uint32_t rl_bufaddr_hi; 629117388Swpaul}; 630117388Swpaul 631117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 632117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 633117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 634117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 635117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 636164463Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 637117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 638117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 639117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 640117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 641117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 642117388Swpaul 643117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 644117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 645180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 646180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 647180176Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 648180176Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 649117388Swpaul 650117388Swpaul/* 651117388Swpaul * Error bits are valid only on the last descriptor of a frame 652117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 653117388Swpaul */ 654117388Swpaul 655117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 656117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 657117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 658117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 659117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 660117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 661117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 662117388Swpaul 663117388Swpaul/* 664117388Swpaul * RX descriptor cmd/vlan definitions 665117388Swpaul */ 666117388Swpaul 667117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 668117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 669119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 670117388Swpaul 671117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 672117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 673117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 674117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 675117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 676117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 677117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 678117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 679117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 680117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 681117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 682117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 683117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 684117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 685117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 686180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 687180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 688117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 689117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 690117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 691119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 692119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 693135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 694135896Sjmg RL_RDESC_STAT_CRCERR) 695117388Swpaul 696117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 697117388Swpaul (rl_vlandata valid)*/ 698117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 699180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 700180176Syongari#define RL_RDESC_IPV6 0x80000000 701180176Syongari#define RL_RDESC_IPV4 0x40000000 702117388Swpaul 703117388Swpaul#define RL_PROTOID_NONIP 0x00000000 704117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 705117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 706117388Swpaul#define RL_PROTOID_IP 0x00030000 707117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 708117388Swpaul RL_PROTOID_TCPIP) 709117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 710117388Swpaul RL_PROTOID_UDPIP) 711117388Swpaul 712117388Swpaul/* 713117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 714117388Swpaul */ 715117388Swpaulstruct rl_stats { 716131605Sbms uint32_t rl_tx_pkts_lo; 717131605Sbms uint32_t rl_tx_pkts_hi; 718131605Sbms uint32_t rl_tx_errs_lo; 719131605Sbms uint32_t rl_tx_errs_hi; 720131605Sbms uint32_t rl_tx_errs; 721131605Sbms uint16_t rl_missed_pkts; 722131605Sbms uint16_t rl_rx_framealign_errs; 723131605Sbms uint32_t rl_tx_onecoll; 724131605Sbms uint32_t rl_tx_multicolls; 725131605Sbms uint32_t rl_rx_ucasts_hi; 726131605Sbms uint32_t rl_rx_ucasts_lo; 727131605Sbms uint32_t rl_rx_bcasts_lo; 728131605Sbms uint32_t rl_rx_bcasts_hi; 729131605Sbms uint32_t rl_rx_mcasts; 730131605Sbms uint16_t rl_tx_aborts; 731131605Sbms uint16_t rl_rx_underruns; 732117388Swpaul}; 733117388Swpaul 734135467Sjmg/* 735135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 736135467Sjmg * 737175337Syongari * 8139C+ 738175337Syongari * Number of descriptors supported : up to 64 739175337Syongari * Descriptor alignment : 256 bytes 740175337Syongari * Tx buffer : At least 4 bytes in length. 741175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 742175337Syongari * 743175337Syongari * 8169 744175337Syongari * Number of descriptors supported : up to 1024 745175337Syongari * Descriptor alignment : 256 bytes 746175337Syongari * Tx buffer : At least 4 bytes in length. 747175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 748135467Sjmg */ 749164460Syongari#ifndef __NO_STRICT_ALIGNMENT 750135896Sjmg#define RE_FIXUP_RX 1 751135896Sjmg#endif 752135896Sjmg 753175337Syongari#define RL_8169_TX_DESC_CNT 256 754175337Syongari#define RL_8169_RX_DESC_CNT 256 755175337Syongari#define RL_8139_TX_DESC_CNT 64 756175337Syongari#define RL_8139_RX_DESC_CNT 64 757175337Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 758175337Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 759175337Syongari#define RL_NTXSEGS 32 760159962Swpaul 761117388Swpaul#define RL_RING_ALIGN 256 762117388Swpaul#define RL_IFQ_MAXLEN 512 763175337Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 764175337Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 765175337Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 766117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 767119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 768119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 769135896Sjmg#ifdef RE_FIXUP_RX 770135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 771135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 772135896Sjmg#else 773135896Sjmg#define RE_ETHER_ALIGN 0 774135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 775135896Sjmg#endif 776117388Swpaul 777171560Syongari#define RL_MSI_MESSAGES 2 778171560Syongari 779135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 780135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 781118712Swpaul 782181270Syongari/* 783181270Syongari * The number of bits reserved for MSS in RealTek controllers is 784181270Syongari * 11bits. This limits the maximum interface MTU size in TSO case 785181270Syongari * as upper stack should not generate TCP segments with MSS greater 786181270Syongari * than the limit. 787181270Syongari */ 788181270Syongari#define RL_TSO_MTU (2047 - ETHER_HDR_LEN - ETHER_CRC_LEN) 789181270Syongari 790135896Sjmg/* see comment in dev/re/if_re.c */ 791135896Sjmg#define RL_JUMBO_FRAMELEN 7440 792119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 793176756Syongari#define RL_MAX_FRAMELEN \ 794176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 795119868Swpaul 796175337Syongaristruct rl_txdesc { 797175337Syongari struct mbuf *tx_m; 798175337Syongari bus_dmamap_t tx_dmamap; 799175337Syongari}; 800117388Swpaul 801175337Syongaristruct rl_rxdesc { 802175337Syongari struct mbuf *rx_m; 803175337Syongari bus_dmamap_t rx_dmamap; 804175337Syongari bus_size_t rx_size; 805117388Swpaul}; 806117388Swpaul 807117388Swpaulstruct rl_list_data { 808175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 809175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 810175337Syongari int rl_tx_desc_cnt; 811175337Syongari int rl_rx_desc_cnt; 812117388Swpaul int rl_tx_prodidx; 813117388Swpaul int rl_rx_prodidx; 814117388Swpaul int rl_tx_considx; 815117388Swpaul int rl_tx_free; 816175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 817175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 818175337Syongari bus_dmamap_t rl_rx_sparemap; 819117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 820117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 821117388Swpaul struct rl_stats *rl_stats; 822118712Swpaul bus_addr_t rl_stats_addr; 823117388Swpaul bus_dma_tag_t rl_rx_list_tag; 824117388Swpaul bus_dmamap_t rl_rx_list_map; 825117388Swpaul struct rl_desc *rl_rx_list; 826118712Swpaul bus_addr_t rl_rx_list_addr; 827117388Swpaul bus_dma_tag_t rl_tx_list_tag; 828117388Swpaul bus_dmamap_t rl_tx_list_map; 829117388Swpaul struct rl_desc *rl_tx_list; 830118712Swpaul bus_addr_t rl_tx_list_addr; 831117388Swpaul}; 832117388Swpaul 833184515Simp#ifdef RL_TWISTER_ENABLE 834184515Simpenum rl_twist { DONE, CHK_LINK, FIND_ROW, SET_PARAM, RECHK_LONG, RETUNE }; 835184515Simp#endif 836184515Simp 83740516Swpaulstruct rl_softc { 838147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 83941569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 84041569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 841159962Swpaul device_t rl_dev; 84250703Swpaul struct resource *rl_res; 843180169Syongari int rl_res_id; 844180169Syongari int rl_res_type; 845171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 846171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 84750703Swpaul device_t rl_miibus; 84881713Swpaul bus_dma_tag_t rl_parent_tag; 849131605Sbms uint8_t rl_type; 85067931Swpaul int rl_eecmd_read; 851159962Swpaul int rl_eewidth; 852131605Sbms uint8_t rl_stats_no_timeout; 85352426Swpaul int rl_txthresh; 85440516Swpaul struct rl_chain_data rl_cdata; 855117388Swpaul struct rl_list_data rl_ldata; 856150720Sjhb struct callout rl_stat_callout; 857164811Sru int rl_watchdog_timer; 85867087Swpaul struct mtx rl_mtx; 859119868Swpaul struct mbuf *rl_head; 860119868Swpaul struct mbuf *rl_tail; 861131605Sbms uint32_t rl_hwrev; 862131605Sbms uint32_t rl_rxlenmask; 863119868Swpaul int rl_testmode; 864168828Syongari int rl_if_flags; 865184515Simp#ifdef RL_TWISTER_ENABLE 866184515Simp enum rl_twist rl_twister; 867184515Simp int rl_twist_row; 868184515Simp int rl_twist_col; 869184515Simp#endif 87086822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 87194883Sluigi#ifdef DEVICE_POLLING 87294883Sluigi int rxcycles; 87394883Sluigi#endif 874159962Swpaul 875159962Swpaul struct task rl_txtask; 876159962Swpaul struct task rl_inttask; 877159962Swpaul 878159962Swpaul int rl_txstart; 879180171Syongari uint32_t rl_flags; 880180171Syongari#define RL_FLAG_MSI 0x0001 881180171Syongari#define RL_FLAG_INVMAR 0x0004 882180171Syongari#define RL_FLAG_PHYWAKE 0x0008 883180171Syongari#define RL_FLAG_NOJUMBO 0x0010 884180176Syongari#define RL_FLAG_PAR 0x0020 885180176Syongari#define RL_FLAG_DESCV2 0x0040 886180176Syongari#define RL_FLAG_MACSTAT 0x0080 887180171Syongari#define RL_FLAG_LINK 0x8000 88840516Swpaul}; 88940516Swpaul 89072200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 89172200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 892122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 89367087Swpaul 89440516Swpaul/* 89540516Swpaul * register space access macros 89640516Swpaul */ 897119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 898119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 89940516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 90041569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 90140516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 90241569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 90340516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 90441569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 90540516Swpaul 90641569Swpaul#define CSR_READ_4(sc, reg) \ 90741569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 90841569Swpaul#define CSR_READ_2(sc, reg) \ 90941569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 91041569Swpaul#define CSR_READ_1(sc, reg) \ 91141569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 91240516Swpaul 913159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 914159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 915159962Swpaul 916159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 917159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 918159962Swpaul 919159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 920159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 921159962Swpaul 922159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 923159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 924159962Swpaul 925159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 926159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 927159962Swpaul 928159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 929159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 930159962Swpaul 93140516Swpaul#define RL_TIMEOUT 1000 93240516Swpaul 93340516Swpaul/* 93440516Swpaul * General constants that are fun to know. 93540516Swpaul * 93640516Swpaul * RealTek PCI vendor ID 93740516Swpaul */ 93840516Swpaul#define RT_VENDORID 0x10EC 93940516Swpaul 94040516Swpaul/* 94140516Swpaul * RealTek chip device IDs. 94240516Swpaul */ 943179831Sremko#define RT_DEVICEID_8139D 0x8039 94440516Swpaul#define RT_DEVICEID_8129 0x8129 945159962Swpaul#define RT_DEVICEID_8101E 0x8136 94667771Swpaul#define RT_DEVICEID_8138 0x8138 94740516Swpaul#define RT_DEVICEID_8139 0x8139 948159962Swpaul#define RT_DEVICEID_8169SC 0x8167 949159962Swpaul#define RT_DEVICEID_8168 0x8168 950117388Swpaul#define RT_DEVICEID_8169 0x8169 951118978Swpaul#define RT_DEVICEID_8100 0x8100 95240516Swpaul 953117388Swpaul#define RT_REVID_8139CPLUS 0x20 954117388Swpaul 95540516Swpaul/* 95644238Swpaul * Accton PCI vendor ID 95744238Swpaul */ 95844238Swpaul#define ACCTON_VENDORID 0x1113 95944238Swpaul 96044238Swpaul/* 96141243Swpaul * Accton MPX 5030/5038 device ID. 96241243Swpaul */ 96341243Swpaul#define ACCTON_DEVICEID_5030 0x1211 96441243Swpaul 96541243Swpaul/* 96694400Swpaul * Nortel PCI vendor ID 96794400Swpaul */ 96894400Swpaul#define NORTEL_VENDORID 0x126C 96994400Swpaul 97094400Swpaul/* 97144238Swpaul * Delta Electronics Vendor ID. 97244238Swpaul */ 97344238Swpaul#define DELTA_VENDORID 0x1500 97444238Swpaul 97544238Swpaul/* 97644238Swpaul * Delta device IDs. 97744238Swpaul */ 97844238Swpaul#define DELTA_DEVICEID_8139 0x1360 97944238Swpaul 98044238Swpaul/* 98144238Swpaul * Addtron vendor ID. 98244238Swpaul */ 98344238Swpaul#define ADDTRON_VENDORID 0x4033 98444238Swpaul 98544238Swpaul/* 98644238Swpaul * Addtron device IDs. 98744238Swpaul */ 98844238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 98944238Swpaul 99044238Swpaul/* 99172813Swpaul * D-Link vendor ID. 99272813Swpaul */ 99372813Swpaul#define DLINK_VENDORID 0x1186 99472813Swpaul 99572813Swpaul/* 99672813Swpaul * D-Link DFE-530TX+ device ID 99772813Swpaul */ 99872813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 99972813Swpaul 100072813Swpaul/* 1001148722Stobez * D-Link DFE-5280T device ID 1002148722Stobez */ 1003148722Stobez#define DLINK_DEVICEID_528T 0x4300 1004148722Stobez 1005148722Stobez/* 100696112Sjhb * D-Link DFE-690TXD device ID 100796112Sjhb */ 100896112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 100996112Sjhb 101096112Sjhb/* 1011103020Siwasaki * Corega K.K vendor ID 1012103020Siwasaki */ 1013103020Siwasaki#define COREGA_VENDORID 0x1259 1014103020Siwasaki 1015103020Siwasaki/* 1016109095Ssanpei * Corega FEther CB-TXD device ID 1017103020Siwasaki */ 1018151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 1019103020Siwasaki 1020103020Siwasaki/* 1021109095Ssanpei * Corega FEtherII CB-TXD device ID 1022109095Ssanpei */ 1023151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 1024109095Ssanpei 1025111381Sdan/* 1026134433Ssanpei * Corega CG-LAPCIGT device ID 1027134433Ssanpei */ 1028134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 1029134433Ssanpei 1030134433Ssanpei/* 1031151341Sjhb * Linksys vendor ID 1032151341Sjhb */ 1033151341Sjhb#define LINKSYS_VENDORID 0x1737 1034151341Sjhb 1035151341Sjhb/* 1036151341Sjhb * Linksys EG1032 device ID 1037151341Sjhb */ 1038151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 1039151341Sjhb 1040151341Sjhb/* 1041151341Sjhb * Linksys EG1032 rev 3 sub-device ID 1042151341Sjhb */ 1043151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 1044151341Sjhb 1045151341Sjhb/* 1046111381Sdan * Peppercon vendor ID 1047111381Sdan */ 1048111381Sdan#define PEPPERCON_VENDORID 0x1743 1049109095Ssanpei 1050111381Sdan/* 1051111381Sdan * Peppercon ROL-F device ID 1052111381Sdan */ 1053111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 1054109095Ssanpei 1055109095Ssanpei/* 1056112379Ssanpei * Planex Communications, Inc. vendor ID 1057112379Ssanpei */ 1058117388Swpaul#define PLANEX_VENDORID 0x14ea 1059112379Ssanpei 1060112379Ssanpei/* 1061173948Sremko * Planex FNW-3603-TX device ID 1062173948Sremko */ 1063173948Sremko#define PLANEX_DEVICEID_FNW3603TX 0xab06 1064173948Sremko 1065173948Sremko/* 1066112379Ssanpei * Planex FNW-3800-TX device ID 1067112379Ssanpei */ 1068117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 1069112379Ssanpei 1070112379Ssanpei/* 1071117388Swpaul * LevelOne vendor ID 1072117388Swpaul */ 1073117388Swpaul#define LEVEL1_VENDORID 0x018A 1074117388Swpaul 1075117388Swpaul/* 1076117388Swpaul * LevelOne FPC-0106TX devide ID 1077117388Swpaul */ 1078117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1079117388Swpaul 1080117388Swpaul/* 1081117388Swpaul * Compaq vendor ID 1082117388Swpaul */ 1083117388Swpaul#define CP_VENDORID 0x021B 1084117388Swpaul 1085117388Swpaul/* 1086117388Swpaul * Edimax vendor ID 1087117388Swpaul */ 1088117388Swpaul#define EDIMAX_VENDORID 0x13D1 1089117388Swpaul 1090117388Swpaul/* 1091117388Swpaul * Edimax EP-4103DL cardbus device ID 1092117388Swpaul */ 1093117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1094117388Swpaul 1095160883Swpaul/* US Robotics vendor ID */ 1096160883Swpaul 1097160883Swpaul#define USR_VENDORID 0x16EC 1098160883Swpaul 1099160883Swpaul/* US Robotics 997902 device ID */ 1100160883Swpaul 1101160883Swpaul#define USR_DEVICEID_997902 0x0116 1102160883Swpaul 1103117388Swpaul/* 110440516Swpaul * PCI low memory base and low I/O base register, and 110550703Swpaul * other PCI registers. 110640516Swpaul */ 110740516Swpaul 110840516Swpaul#define RL_PCI_VENDOR_ID 0x00 110940516Swpaul#define RL_PCI_DEVICE_ID 0x02 111040516Swpaul#define RL_PCI_COMMAND 0x04 111140516Swpaul#define RL_PCI_STATUS 0x06 111240516Swpaul#define RL_PCI_CLASSCODE 0x09 111340516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 111440516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 111540516Swpaul#define RL_PCI_LOIO 0x10 111640516Swpaul#define RL_PCI_LOMEM 0x14 111740516Swpaul#define RL_PCI_BIOSROM 0x30 111840516Swpaul#define RL_PCI_INTLINE 0x3C 111940516Swpaul#define RL_PCI_INTPIN 0x3D 112040516Swpaul#define RL_PCI_MINGNT 0x3E 112140516Swpaul#define RL_PCI_MINLAT 0x0F 112240516Swpaul#define RL_PCI_RESETOPT 0x48 112340516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 112440516Swpaul 112550097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 112650097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 112750097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 112850097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 112940516Swpaul 113040516Swpaul#define RL_PSTATE_MASK 0x0003 113140516Swpaul#define RL_PSTATE_D0 0x0000 113240516Swpaul#define RL_PSTATE_D1 0x0002 113340516Swpaul#define RL_PSTATE_D2 0x0002 113440516Swpaul#define RL_PSTATE_D3 0x0003 113540516Swpaul#define RL_PME_EN 0x0010 113640516Swpaul#define RL_PME_STATUS 0x8000 1137