if_rlreg.h revision 180177
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 180177 2008-07-02 08:00:14Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 8440516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 8640516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8740516Swpaul#define RL_HALTCLK 0x005B 8840516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8940516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 9140516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 9440516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9540516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9640516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9740516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9840516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 10040516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 10140516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 10240516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 10340516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10440516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117120043Swpaul#define RL_CFG2 0x0053 118117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 120117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129117388Swpaul#define RL_PHYAR 0x0060 130117388Swpaul#define RL_TBICSR 0x0064 131117388Swpaul#define RL_TBI_ANAR 0x0068 132117388Swpaul#define RL_TBI_LPAR 0x006A 133117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135175337Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 136117388Swpaul 137117388Swpaul/* 13840516Swpaul * TX config register bits 13940516Swpaul */ 14040516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 14145633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 14240516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 14345633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14545633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14740516Swpaul 148119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 149119868Swpaul#define RL_LOOPTEST_ON 0x00020000 150119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 151119868Swpaul 152159962Swpaul/* Known revision codes. */ 153117388Swpaul 154160843Swpaul#define RL_HWREV_8169 0x00000000 155160843Swpaul#define RL_HWREV_8110S 0x00800000 156160843Swpaul#define RL_HWREV_8169S 0x04000000 157160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 158160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 159160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 160160843Swpaul#define RL_HWREV_8100E 0x30800000 161160843Swpaul#define RL_HWREV_8101E 0x34000000 162160843Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 163174428Syongari#define RL_HWREV_8168_SPIN3 0x38400000 164180176Syongari#define RL_HWREV_8168C 0x3C000000 165180176Syongari#define RL_HWREV_8168C_SPIN2 0x3C400000 166180176Syongari#define RL_HWREV_8168CP 0x3C800000 167160843Swpaul#define RL_HWREV_8139 0x60000000 168160843Swpaul#define RL_HWREV_8139A 0x70000000 169160843Swpaul#define RL_HWREV_8139AG 0x70800000 170160843Swpaul#define RL_HWREV_8139B 0x78000000 171160843Swpaul#define RL_HWREV_8130 0x7C000000 172160843Swpaul#define RL_HWREV_8139C 0x74000000 173160843Swpaul#define RL_HWREV_8139D 0x74400000 174160843Swpaul#define RL_HWREV_8139CPLUS 0x74800000 175160843Swpaul#define RL_HWREV_8101 0x74c00000 176160843Swpaul#define RL_HWREV_8100 0x78800000 177180177Syongari#define RL_HWREV_8169_8110SBL 0x7CC00000 178159962Swpaul 17945633Swpaul#define RL_TXDMA_16BYTES 0x00000000 18045633Swpaul#define RL_TXDMA_32BYTES 0x00000100 18145633Swpaul#define RL_TXDMA_64BYTES 0x00000200 18245633Swpaul#define RL_TXDMA_128BYTES 0x00000300 18345633Swpaul#define RL_TXDMA_256BYTES 0x00000400 18445633Swpaul#define RL_TXDMA_512BYTES 0x00000500 18545633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 18645633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 18745633Swpaul 18840516Swpaul/* 18940516Swpaul * Transmit descriptor status register bits. 19040516Swpaul */ 19140516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 19240516Swpaul#define RL_TXSTAT_OWN 0x00002000 19340516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 19440516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 19540516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 19640516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 19740516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 19840516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 19940516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 20040516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 20140516Swpaul 20240516Swpaul/* 20340516Swpaul * Interrupt status register bits. 20440516Swpaul */ 20540516Swpaul#define RL_ISR_RX_OK 0x0001 20640516Swpaul#define RL_ISR_RX_ERR 0x0002 20740516Swpaul#define RL_ISR_TX_OK 0x0004 20840516Swpaul#define RL_ISR_TX_ERR 0x0008 20940516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 21040516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 211119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 21240516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 213117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 214117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 215117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 21640516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 217117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 21840516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 21940516Swpaul 22040516Swpaul#define RL_INTRS \ 22140516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 22240516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 22340516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 22440516Swpaul 225159962Swpaul#ifdef RE_TX_MODERATION 226117388Swpaul#define RL_INTRS_CPLUS \ 227119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 228117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 229117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 230159962Swpaul#else 231159962Swpaul#define RL_INTRS_CPLUS \ 232159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 233159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 234159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 235159962Swpaul#endif 236117388Swpaul 23740516Swpaul/* 23840516Swpaul * Media status register. (8139 only) 23940516Swpaul */ 24040516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 24140516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 24240516Swpaul#define RL_MEDIASTAT_LINK 0x04 24340516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 24440516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 24540516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 24640516Swpaul 24740516Swpaul/* 24840516Swpaul * Receive config register. 24940516Swpaul */ 25040516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 25140516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 25240516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 25340516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 25440516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 25540516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 25640516Swpaul#define RL_RXCFG_WRAP 0x00000080 25745633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 25845633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 25945633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 26045633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 26140516Swpaul 26245633Swpaul#define RL_RXDMA_16BYTES 0x00000000 26345633Swpaul#define RL_RXDMA_32BYTES 0x00000100 26445633Swpaul#define RL_RXDMA_64BYTES 0x00000200 26545633Swpaul#define RL_RXDMA_128BYTES 0x00000300 26645633Swpaul#define RL_RXDMA_256BYTES 0x00000400 26745633Swpaul#define RL_RXDMA_512BYTES 0x00000500 26845633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 26945633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 27045633Swpaul 27140516Swpaul#define RL_RXBUF_8 0x00000000 27240516Swpaul#define RL_RXBUF_16 0x00000800 27340516Swpaul#define RL_RXBUF_32 0x00001000 27445633Swpaul#define RL_RXBUF_64 0x00001800 27540516Swpaul 27645633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 27745633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 27845633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 27945633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 28045633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 28145633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 28245633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 28345633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 28445633Swpaul 28540516Swpaul/* 28640516Swpaul * Bits in RX status header (included with RX'ed packet 28740516Swpaul * in ring buffer). 28840516Swpaul */ 28940516Swpaul#define RL_RXSTAT_RXOK 0x00000001 29040516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 29140516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 29240516Swpaul#define RL_RXSTAT_GIANT 0x00000008 29340516Swpaul#define RL_RXSTAT_RUNT 0x00000010 29440516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 29540516Swpaul#define RL_RXSTAT_BROAD 0x00002000 29640516Swpaul#define RL_RXSTAT_INDIV 0x00004000 29740516Swpaul#define RL_RXSTAT_MULTI 0x00008000 29840516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 29940516Swpaul 30040516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 30140516Swpaul/* 30240516Swpaul * Command register. 30340516Swpaul */ 30440516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 30540516Swpaul#define RL_CMD_TX_ENB 0x0004 30640516Swpaul#define RL_CMD_RX_ENB 0x0008 30740516Swpaul#define RL_CMD_RESET 0x0010 30840516Swpaul 30940516Swpaul/* 31040516Swpaul * EEPROM control register 31140516Swpaul */ 31240516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 31340516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 31440516Swpaul#define RL_EE_CLK 0x04 /* clock */ 31540516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 31640516Swpaul#define RL_EE_MODE (0x40|0x80) 31740516Swpaul 31840516Swpaul#define RL_EEMODE_OFF 0x00 31940516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 32040516Swpaul#define RL_EEMODE_PROGRAM 0x80 32140516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 32240516Swpaul 32340516Swpaul/* 9346 EEPROM commands */ 324171263Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 325171263Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 326159962Swpaul 327159962Swpaul#define RL_9346_WRITE 0x5 328159962Swpaul#define RL_9346_READ 0x6 329159962Swpaul#define RL_9346_ERASE 0x7 330159962Swpaul#define RL_9346_EWEN 0x4 331159962Swpaul#define RL_9346_EWEN_ADDR 0x30 332159962Swpaul#define RL_9456_EWDS 0x4 333159962Swpaul#define RL_9346_EWDS_ADDR 0x00 334159962Swpaul 33540516Swpaul#define RL_EECMD_WRITE 0x140 33667931Swpaul#define RL_EECMD_READ_6BIT 0x180 33767931Swpaul#define RL_EECMD_READ_8BIT 0x600 33840516Swpaul#define RL_EECMD_ERASE 0x1c0 33940516Swpaul 34040516Swpaul#define RL_EE_ID 0x00 34140516Swpaul#define RL_EE_PCI_VID 0x01 34240516Swpaul#define RL_EE_PCI_DID 0x02 34340516Swpaul/* Location of station address inside EEPROM */ 34440516Swpaul#define RL_EE_EADDR 0x07 34540516Swpaul 34640516Swpaul/* 34740516Swpaul * MII register (8129 only) 34840516Swpaul */ 34940516Swpaul#define RL_MII_CLK 0x01 35040516Swpaul#define RL_MII_DATAIN 0x02 35140516Swpaul#define RL_MII_DATAOUT 0x04 35240516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 35340516Swpaul 35440516Swpaul/* 35540516Swpaul * Config 0 register 35640516Swpaul */ 35740516Swpaul#define RL_CFG0_ROM0 0x01 35840516Swpaul#define RL_CFG0_ROM1 0x02 35940516Swpaul#define RL_CFG0_ROM2 0x04 36040516Swpaul#define RL_CFG0_PL0 0x08 36140516Swpaul#define RL_CFG0_PL1 0x10 36240516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 36340516Swpaul#define RL_CFG0_PCS 0x40 36440516Swpaul#define RL_CFG0_SCR 0x80 36540516Swpaul 36640516Swpaul/* 36740516Swpaul * Config 1 register 36840516Swpaul */ 36940516Swpaul#define RL_CFG1_PWRDWN 0x01 370176754Syongari#define RL_CFG1_PME 0x01 37140516Swpaul#define RL_CFG1_SLEEP 0x02 372176754Syongari#define RL_CFG1_VPDEN 0x02 37340516Swpaul#define RL_CFG1_IOMAP 0x04 37440516Swpaul#define RL_CFG1_MEMMAP 0x08 37540516Swpaul#define RL_CFG1_RSVD 0x10 376176754Syongari#define RL_CFG1_LWACT 0x10 37740516Swpaul#define RL_CFG1_DRVLOAD 0x20 37840516Swpaul#define RL_CFG1_LED0 0x40 37940516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 38040516Swpaul#define RL_CFG1_LED1 0x80 38140516Swpaul 38240516Swpaul/* 383176754Syongari * Config 2 register 384176754Syongari */ 385176754Syongari#define RL_CFG2_PCI33MHZ 0x00 386176754Syongari#define RL_CFG2_PCI66MHZ 0x01 387176754Syongari#define RL_CFG2_PCI64BIT 0x08 388176754Syongari#define RL_CFG2_AUXPWR 0x10 389177522Syongari#define RL_CFG2_MSI 0x20 390176754Syongari 391176754Syongari/* 392176754Syongari * Config 3 register 393176754Syongari */ 394176754Syongari#define RL_CFG3_GRANTSEL 0x80 395176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 396176754Syongari#define RL_CFG3_WOL_LINK 0x10 397176754Syongari#define RL_CFG3_FAST_B2B 0x01 398176754Syongari 399176754Syongari/* 400176754Syongari * Config 4 register 401176754Syongari */ 402176754Syongari#define RL_CFG4_LWPTN 0x04 403176754Syongari#define RL_CFG4_LWPME 0x10 404176754Syongari 405176754Syongari/* 406176754Syongari * Config 5 register 407176754Syongari */ 408176754Syongari#define RL_CFG5_WOL_BCAST 0x40 409176754Syongari#define RL_CFG5_WOL_MCAST 0x20 410176754Syongari#define RL_CFG5_WOL_UCAST 0x10 411176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 412176754Syongari#define RL_CFG5_PME_STS 0x01 413176754Syongari 414176754Syongari/* 415117388Swpaul * 8139C+ register definitions 416117388Swpaul */ 417117388Swpaul 418117388Swpaul/* RL_DUMPSTATS_LO register */ 419117388Swpaul 420117388Swpaul#define RL_DUMPSTATS_START 0x00000008 421117388Swpaul 422117388Swpaul/* Transmit start register */ 423117388Swpaul 424117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 425117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 426117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 427117388Swpaul 428120043Swpaul/* 429120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 430120043Swpaul */ 431120043Swpaul#define RL_CFG2_BUSFREQ 0x07 432120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 433120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 434120043Swpaul 435120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 436120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 437120043Swpaul 438120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 439120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 440120043Swpaul 441117388Swpaul/* C+ mode command register */ 442117388Swpaul 443117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 444117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 445117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 446117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 447117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 448117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 449180176Syongari#define RL_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */ 450180176Syongari#define RL_CPLUSCMD_ASF 0x0100 /* 8168C/CP */ 451180176Syongari#define RL_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */ 452180176Syongari#define RL_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */ 453180176Syongari#define RL_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */ 454180176Syongari#define RL_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */ 455180176Syongari#define RL_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */ 456180176Syongari#define RL_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */ 457180176Syongari#define RL_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */ 458117388Swpaul 459117388Swpaul/* C+ early transmit threshold */ 460117388Swpaul 461117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 462117388Swpaul 463117388Swpaul/* 464117388Swpaul * Gigabit PHY access register (8169 only) 465117388Swpaul */ 466117388Swpaul 467117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 468117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 469117388Swpaul#define RL_PHYAR_BUSY 0x80000000 470117388Swpaul 471117388Swpaul/* 472117388Swpaul * Gigabit media status (8169 only) 473117388Swpaul */ 474117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 475117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 476117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 477117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 478119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 479117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 480117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 481117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 482117388Swpaul 483117388Swpaul/* 48440516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 48540516Swpaul * Instead, there are only four register sets, each or which represents 48640516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 48740516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 48840516Swpaul * the registers so the chip knows where they are. 48940516Swpaul * 49040516Swpaul * We can sort of kludge together the same kind of buffer management 49140516Swpaul * used in previous drivers, but we have to do buffer copies almost all 49240516Swpaul * the time, so it doesn't really buy us much. 49340516Swpaul * 49440516Swpaul * For reception, there's just one large buffer where the chip stores 49540516Swpaul * all received packets. 49640516Swpaul */ 49740516Swpaul 49840516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 49940516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 50040516Swpaul#define RL_TX_LIST_CNT 4 50140516Swpaul#define RL_MIN_FRAMELEN 60 50252426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 50352426Swpaul#define RL_TX_THRESH_INIT 96 504119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 505119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 50650703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 50740516Swpaul 50845633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 50945633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 51040516Swpaul 51148028Swpaul#define RL_ETHER_ALIGN 2 51248028Swpaul 513177771Syongari/* 514177771Syongari * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets. 515177771Syongari */ 516177771Syongari#define RL_IP4CSUMTX_MINLEN 28 517177771Syongari#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN) 518177771Syongari 51940516Swpaulstruct rl_chain_data { 520131605Sbms uint16_t cur_rx; 521131605Sbms uint8_t *rl_rx_buf; 522131605Sbms uint8_t *rl_rx_buf_ptr; 52381713Swpaul bus_dmamap_t rl_rx_dmamap; 52440516Swpaul 52545633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 52681713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 527131605Sbms uint8_t last_tx; 528131605Sbms uint8_t cur_tx; 52940516Swpaul}; 53040516Swpaul 53145633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 53245633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 53345633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 53445633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 53581713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 53645633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 53745633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 53845633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 53981713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 54045633Swpaul 54140516Swpaulstruct rl_type { 542131605Sbms uint16_t rl_vid; 543131605Sbms uint16_t rl_did; 544117388Swpaul int rl_basetype; 54540516Swpaul char *rl_name; 54640516Swpaul}; 54740516Swpaul 548117388Swpaulstruct rl_hwrev { 549131605Sbms uint32_t rl_rev; 550117388Swpaul int rl_type; 551117388Swpaul char *rl_desc; 552117388Swpaul}; 553117388Swpaul 55440516Swpaulstruct rl_mii_frame { 555131605Sbms uint8_t mii_stdelim; 556131605Sbms uint8_t mii_opcode; 557131605Sbms uint8_t mii_phyaddr; 558131605Sbms uint8_t mii_regaddr; 559131605Sbms uint8_t mii_turnaround; 560131605Sbms uint16_t mii_data; 56140516Swpaul}; 56240516Swpaul 56340516Swpaul/* 56440516Swpaul * MII constants 56540516Swpaul */ 56640516Swpaul#define RL_MII_STARTDELIM 0x01 56740516Swpaul#define RL_MII_READOP 0x02 56840516Swpaul#define RL_MII_WRITEOP 0x01 56940516Swpaul#define RL_MII_TURNAROUND 0x02 57040516Swpaul 57140516Swpaul#define RL_8129 1 57240516Swpaul#define RL_8139 2 573117388Swpaul#define RL_8139CPLUS 3 574117388Swpaul#define RL_8169 4 57540516Swpaul 576117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 577117388Swpaul (x)->rl_type == RL_8169) 578117388Swpaul 579117388Swpaul/* 580117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 581117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 582117388Swpaul * must be allocated in contiguous blocks that are aligned on a 583117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 584117388Swpaul */ 585117388Swpaul 586117388Swpaul/* 587117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 588117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 589117388Swpaul * the checksum offload bits are disabled. The structure layout is 590117388Swpaul * the same for RX and TX descriptors 591117388Swpaul */ 592117388Swpaul 593117388Swpaulstruct rl_desc { 594131605Sbms uint32_t rl_cmdstat; 595131605Sbms uint32_t rl_vlanctl; 596131605Sbms uint32_t rl_bufaddr_lo; 597131605Sbms uint32_t rl_bufaddr_hi; 598117388Swpaul}; 599117388Swpaul 600117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 601117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 602117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 603117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 604117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 605164463Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 606117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 607117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 608117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 609117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 610117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 611117388Swpaul 612117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 613117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 614180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 615180176Syongari#define RL_TDESC_CMD_UDPCSUMV2 0x80000000 616180176Syongari#define RL_TDESC_CMD_TCPCSUMV2 0x40000000 617180176Syongari#define RL_TDESC_CMD_IPCSUMV2 0x20000000 618117388Swpaul 619117388Swpaul/* 620117388Swpaul * Error bits are valid only on the last descriptor of a frame 621117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 622117388Swpaul */ 623117388Swpaul 624117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 625117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 626117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 627117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 628117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 629117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 630117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 631117388Swpaul 632117388Swpaul/* 633117388Swpaul * RX descriptor cmd/vlan definitions 634117388Swpaul */ 635117388Swpaul 636117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 637117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 638119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 639117388Swpaul 640117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 641117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 642117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 643117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 644117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 645117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 646117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 647117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 648117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 649117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 650117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 651117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 652117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 653117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 654117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 655180176Syongari#define RL_RDESC_STAT_UDP 0x00020000 /* UDP, 8168C/CP, 8111C/CP */ 656180176Syongari#define RL_RDESC_STAT_TCP 0x00010000 /* TCP, 8168C/CP, 8111C/CP */ 657117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 658117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 659117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 660119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 661119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 662135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 663135896Sjmg RL_RDESC_STAT_CRCERR) 664117388Swpaul 665117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 666117388Swpaul (rl_vlandata valid)*/ 667117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 668180176Syongari/* RTL8168C/RTL8168CP/RTL8111C/RTL8111CP */ 669180176Syongari#define RL_RDESC_IPV6 0x80000000 670180176Syongari#define RL_RDESC_IPV4 0x40000000 671117388Swpaul 672117388Swpaul#define RL_PROTOID_NONIP 0x00000000 673117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 674117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 675117388Swpaul#define RL_PROTOID_IP 0x00030000 676117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 677117388Swpaul RL_PROTOID_TCPIP) 678117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 679117388Swpaul RL_PROTOID_UDPIP) 680117388Swpaul 681117388Swpaul/* 682117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 683117388Swpaul */ 684117388Swpaulstruct rl_stats { 685131605Sbms uint32_t rl_tx_pkts_lo; 686131605Sbms uint32_t rl_tx_pkts_hi; 687131605Sbms uint32_t rl_tx_errs_lo; 688131605Sbms uint32_t rl_tx_errs_hi; 689131605Sbms uint32_t rl_tx_errs; 690131605Sbms uint16_t rl_missed_pkts; 691131605Sbms uint16_t rl_rx_framealign_errs; 692131605Sbms uint32_t rl_tx_onecoll; 693131605Sbms uint32_t rl_tx_multicolls; 694131605Sbms uint32_t rl_rx_ucasts_hi; 695131605Sbms uint32_t rl_rx_ucasts_lo; 696131605Sbms uint32_t rl_rx_bcasts_lo; 697131605Sbms uint32_t rl_rx_bcasts_hi; 698131605Sbms uint32_t rl_rx_mcasts; 699131605Sbms uint16_t rl_tx_aborts; 700131605Sbms uint16_t rl_rx_underruns; 701117388Swpaul}; 702117388Swpaul 703135467Sjmg/* 704135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 705135467Sjmg * 706175337Syongari * 8139C+ 707175337Syongari * Number of descriptors supported : up to 64 708175337Syongari * Descriptor alignment : 256 bytes 709175337Syongari * Tx buffer : At least 4 bytes in length. 710175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 711175337Syongari * 712175337Syongari * 8169 713175337Syongari * Number of descriptors supported : up to 1024 714175337Syongari * Descriptor alignment : 256 bytes 715175337Syongari * Tx buffer : At least 4 bytes in length. 716175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 717135467Sjmg */ 718164460Syongari#ifndef __NO_STRICT_ALIGNMENT 719135896Sjmg#define RE_FIXUP_RX 1 720135896Sjmg#endif 721135896Sjmg 722175337Syongari#define RL_8169_TX_DESC_CNT 256 723175337Syongari#define RL_8169_RX_DESC_CNT 256 724175337Syongari#define RL_8139_TX_DESC_CNT 64 725175337Syongari#define RL_8139_RX_DESC_CNT 64 726175337Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 727175337Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 728175337Syongari#define RL_NTXSEGS 32 729159962Swpaul 730117388Swpaul#define RL_RING_ALIGN 256 731117388Swpaul#define RL_IFQ_MAXLEN 512 732175337Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 733175337Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 734175337Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 735117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 736119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 737119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 738135896Sjmg#ifdef RE_FIXUP_RX 739135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 740135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 741135896Sjmg#else 742135896Sjmg#define RE_ETHER_ALIGN 0 743135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 744135896Sjmg#endif 745117388Swpaul 746171560Syongari#define RL_MSI_MESSAGES 2 747171560Syongari 748135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 749135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 750118712Swpaul 751135896Sjmg/* see comment in dev/re/if_re.c */ 752135896Sjmg#define RL_JUMBO_FRAMELEN 7440 753119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 754176756Syongari#define RL_MAX_FRAMELEN \ 755176756Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN) 756119868Swpaul 757175337Syongaristruct rl_txdesc { 758175337Syongari struct mbuf *tx_m; 759175337Syongari bus_dmamap_t tx_dmamap; 760175337Syongari}; 761117388Swpaul 762175337Syongaristruct rl_rxdesc { 763175337Syongari struct mbuf *rx_m; 764175337Syongari bus_dmamap_t rx_dmamap; 765175337Syongari bus_size_t rx_size; 766117388Swpaul}; 767117388Swpaul 768117388Swpaulstruct rl_list_data { 769175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 770175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 771175337Syongari int rl_tx_desc_cnt; 772175337Syongari int rl_rx_desc_cnt; 773117388Swpaul int rl_tx_prodidx; 774117388Swpaul int rl_rx_prodidx; 775117388Swpaul int rl_tx_considx; 776117388Swpaul int rl_tx_free; 777175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 778175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 779175337Syongari bus_dmamap_t rl_rx_sparemap; 780117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 781117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 782117388Swpaul struct rl_stats *rl_stats; 783118712Swpaul bus_addr_t rl_stats_addr; 784117388Swpaul bus_dma_tag_t rl_rx_list_tag; 785117388Swpaul bus_dmamap_t rl_rx_list_map; 786117388Swpaul struct rl_desc *rl_rx_list; 787118712Swpaul bus_addr_t rl_rx_list_addr; 788117388Swpaul bus_dma_tag_t rl_tx_list_tag; 789117388Swpaul bus_dmamap_t rl_tx_list_map; 790117388Swpaul struct rl_desc *rl_tx_list; 791118712Swpaul bus_addr_t rl_tx_list_addr; 792117388Swpaul}; 793117388Swpaul 79440516Swpaulstruct rl_softc { 795147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 79641569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 79741569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 798159962Swpaul device_t rl_dev; 79950703Swpaul struct resource *rl_res; 800180169Syongari int rl_res_id; 801180169Syongari int rl_res_type; 802171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 803171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 80450703Swpaul device_t rl_miibus; 80581713Swpaul bus_dma_tag_t rl_parent_tag; 80681713Swpaul bus_dma_tag_t rl_tag; 807131605Sbms uint8_t rl_type; 80867931Swpaul int rl_eecmd_read; 809159962Swpaul int rl_eewidth; 810131605Sbms uint8_t rl_stats_no_timeout; 81152426Swpaul int rl_txthresh; 81240516Swpaul struct rl_chain_data rl_cdata; 813117388Swpaul struct rl_list_data rl_ldata; 814150720Sjhb struct callout rl_stat_callout; 815164811Sru int rl_watchdog_timer; 81667087Swpaul struct mtx rl_mtx; 817119868Swpaul struct mbuf *rl_head; 818119868Swpaul struct mbuf *rl_tail; 819131605Sbms uint32_t rl_hwrev; 820131605Sbms uint32_t rl_rxlenmask; 821119868Swpaul int rl_testmode; 822168828Syongari int rl_if_flags; 82386822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 82494883Sluigi#ifdef DEVICE_POLLING 82594883Sluigi int rxcycles; 82694883Sluigi#endif 827159962Swpaul 828159962Swpaul struct task rl_txtask; 829159962Swpaul struct task rl_inttask; 830159962Swpaul 831159962Swpaul int rl_txstart; 832180171Syongari uint32_t rl_flags; 833180171Syongari#define RL_FLAG_MSI 0x0001 834180171Syongari#define RL_FLAG_INVMAR 0x0004 835180171Syongari#define RL_FLAG_PHYWAKE 0x0008 836180171Syongari#define RL_FLAG_NOJUMBO 0x0010 837180176Syongari#define RL_FLAG_PAR 0x0020 838180176Syongari#define RL_FLAG_DESCV2 0x0040 839180176Syongari#define RL_FLAG_MACSTAT 0x0080 840180171Syongari#define RL_FLAG_LINK 0x8000 84140516Swpaul}; 84240516Swpaul 84372200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 84472200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 845122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 84667087Swpaul 84740516Swpaul/* 84840516Swpaul * register space access macros 84940516Swpaul */ 850119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 851119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 85240516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 85341569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 85440516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 85541569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 85640516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 85741569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 85840516Swpaul 85941569Swpaul#define CSR_READ_4(sc, reg) \ 86041569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 86141569Swpaul#define CSR_READ_2(sc, reg) \ 86241569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 86341569Swpaul#define CSR_READ_1(sc, reg) \ 86441569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 86540516Swpaul 866159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 867159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 868159962Swpaul 869159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 870159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 871159962Swpaul 872159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 873159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 874159962Swpaul 875159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 876159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 877159962Swpaul 878159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 879159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 880159962Swpaul 881159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 882159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 883159962Swpaul 88440516Swpaul#define RL_TIMEOUT 1000 88540516Swpaul 88640516Swpaul/* 88740516Swpaul * General constants that are fun to know. 88840516Swpaul * 88940516Swpaul * RealTek PCI vendor ID 89040516Swpaul */ 89140516Swpaul#define RT_VENDORID 0x10EC 89240516Swpaul 89340516Swpaul/* 89440516Swpaul * RealTek chip device IDs. 89540516Swpaul */ 896179831Sremko#define RT_DEVICEID_8139D 0x8039 89740516Swpaul#define RT_DEVICEID_8129 0x8129 898159962Swpaul#define RT_DEVICEID_8101E 0x8136 89967771Swpaul#define RT_DEVICEID_8138 0x8138 90040516Swpaul#define RT_DEVICEID_8139 0x8139 901159962Swpaul#define RT_DEVICEID_8169SC 0x8167 902159962Swpaul#define RT_DEVICEID_8168 0x8168 903117388Swpaul#define RT_DEVICEID_8169 0x8169 904118978Swpaul#define RT_DEVICEID_8100 0x8100 90540516Swpaul 906117388Swpaul#define RT_REVID_8139CPLUS 0x20 907117388Swpaul 90840516Swpaul/* 90944238Swpaul * Accton PCI vendor ID 91044238Swpaul */ 91144238Swpaul#define ACCTON_VENDORID 0x1113 91244238Swpaul 91344238Swpaul/* 91441243Swpaul * Accton MPX 5030/5038 device ID. 91541243Swpaul */ 91641243Swpaul#define ACCTON_DEVICEID_5030 0x1211 91741243Swpaul 91841243Swpaul/* 91994400Swpaul * Nortel PCI vendor ID 92094400Swpaul */ 92194400Swpaul#define NORTEL_VENDORID 0x126C 92294400Swpaul 92394400Swpaul/* 92444238Swpaul * Delta Electronics Vendor ID. 92544238Swpaul */ 92644238Swpaul#define DELTA_VENDORID 0x1500 92744238Swpaul 92844238Swpaul/* 92944238Swpaul * Delta device IDs. 93044238Swpaul */ 93144238Swpaul#define DELTA_DEVICEID_8139 0x1360 93244238Swpaul 93344238Swpaul/* 93444238Swpaul * Addtron vendor ID. 93544238Swpaul */ 93644238Swpaul#define ADDTRON_VENDORID 0x4033 93744238Swpaul 93844238Swpaul/* 93944238Swpaul * Addtron device IDs. 94044238Swpaul */ 94144238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 94244238Swpaul 94344238Swpaul/* 94472813Swpaul * D-Link vendor ID. 94572813Swpaul */ 94672813Swpaul#define DLINK_VENDORID 0x1186 94772813Swpaul 94872813Swpaul/* 94972813Swpaul * D-Link DFE-530TX+ device ID 95072813Swpaul */ 95172813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 95272813Swpaul 95372813Swpaul/* 954148722Stobez * D-Link DFE-5280T device ID 955148722Stobez */ 956148722Stobez#define DLINK_DEVICEID_528T 0x4300 957148722Stobez 958148722Stobez/* 95996112Sjhb * D-Link DFE-690TXD device ID 96096112Sjhb */ 96196112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 96296112Sjhb 96396112Sjhb/* 964103020Siwasaki * Corega K.K vendor ID 965103020Siwasaki */ 966103020Siwasaki#define COREGA_VENDORID 0x1259 967103020Siwasaki 968103020Siwasaki/* 969109095Ssanpei * Corega FEther CB-TXD device ID 970103020Siwasaki */ 971151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 972103020Siwasaki 973103020Siwasaki/* 974109095Ssanpei * Corega FEtherII CB-TXD device ID 975109095Ssanpei */ 976151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 977109095Ssanpei 978111381Sdan/* 979134433Ssanpei * Corega CG-LAPCIGT device ID 980134433Ssanpei */ 981134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 982134433Ssanpei 983134433Ssanpei/* 984151341Sjhb * Linksys vendor ID 985151341Sjhb */ 986151341Sjhb#define LINKSYS_VENDORID 0x1737 987151341Sjhb 988151341Sjhb/* 989151341Sjhb * Linksys EG1032 device ID 990151341Sjhb */ 991151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 992151341Sjhb 993151341Sjhb/* 994151341Sjhb * Linksys EG1032 rev 3 sub-device ID 995151341Sjhb */ 996151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 997151341Sjhb 998151341Sjhb/* 999111381Sdan * Peppercon vendor ID 1000111381Sdan */ 1001111381Sdan#define PEPPERCON_VENDORID 0x1743 1002109095Ssanpei 1003111381Sdan/* 1004111381Sdan * Peppercon ROL-F device ID 1005111381Sdan */ 1006111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 1007109095Ssanpei 1008109095Ssanpei/* 1009112379Ssanpei * Planex Communications, Inc. vendor ID 1010112379Ssanpei */ 1011117388Swpaul#define PLANEX_VENDORID 0x14ea 1012112379Ssanpei 1013112379Ssanpei/* 1014173948Sremko * Planex FNW-3603-TX device ID 1015173948Sremko */ 1016173948Sremko#define PLANEX_DEVICEID_FNW3603TX 0xab06 1017173948Sremko 1018173948Sremko/* 1019112379Ssanpei * Planex FNW-3800-TX device ID 1020112379Ssanpei */ 1021117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 1022112379Ssanpei 1023112379Ssanpei/* 1024117388Swpaul * LevelOne vendor ID 1025117388Swpaul */ 1026117388Swpaul#define LEVEL1_VENDORID 0x018A 1027117388Swpaul 1028117388Swpaul/* 1029117388Swpaul * LevelOne FPC-0106TX devide ID 1030117388Swpaul */ 1031117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 1032117388Swpaul 1033117388Swpaul/* 1034117388Swpaul * Compaq vendor ID 1035117388Swpaul */ 1036117388Swpaul#define CP_VENDORID 0x021B 1037117388Swpaul 1038117388Swpaul/* 1039117388Swpaul * Edimax vendor ID 1040117388Swpaul */ 1041117388Swpaul#define EDIMAX_VENDORID 0x13D1 1042117388Swpaul 1043117388Swpaul/* 1044117388Swpaul * Edimax EP-4103DL cardbus device ID 1045117388Swpaul */ 1046117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1047117388Swpaul 1048160883Swpaul/* US Robotics vendor ID */ 1049160883Swpaul 1050160883Swpaul#define USR_VENDORID 0x16EC 1051160883Swpaul 1052160883Swpaul/* US Robotics 997902 device ID */ 1053160883Swpaul 1054160883Swpaul#define USR_DEVICEID_997902 0x0116 1055160883Swpaul 1056117388Swpaul/* 105740516Swpaul * PCI low memory base and low I/O base register, and 105850703Swpaul * other PCI registers. 105940516Swpaul */ 106040516Swpaul 106140516Swpaul#define RL_PCI_VENDOR_ID 0x00 106240516Swpaul#define RL_PCI_DEVICE_ID 0x02 106340516Swpaul#define RL_PCI_COMMAND 0x04 106440516Swpaul#define RL_PCI_STATUS 0x06 106540516Swpaul#define RL_PCI_CLASSCODE 0x09 106640516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 106740516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 106840516Swpaul#define RL_PCI_LOIO 0x10 106940516Swpaul#define RL_PCI_LOMEM 0x14 107040516Swpaul#define RL_PCI_BIOSROM 0x30 107140516Swpaul#define RL_PCI_INTLINE 0x3C 107240516Swpaul#define RL_PCI_INTPIN 0x3D 107340516Swpaul#define RL_PCI_MINGNT 0x3E 107440516Swpaul#define RL_PCI_MINLAT 0x0F 107540516Swpaul#define RL_PCI_RESETOPT 0x48 107640516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 107740516Swpaul 107850097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 107950097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 108050097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 108150097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 108240516Swpaul 108340516Swpaul#define RL_PSTATE_MASK 0x0003 108440516Swpaul#define RL_PSTATE_D0 0x0000 108540516Swpaul#define RL_PSTATE_D1 0x0002 108640516Swpaul#define RL_PSTATE_D2 0x0002 108740516Swpaul#define RL_PSTATE_D3 0x0003 108840516Swpaul#define RL_PME_EN 0x0010 108940516Swpaul#define RL_PME_STATUS 0x8000 1090