if_rlreg.h revision 176754
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 176754 2008-03-03 03:33:58Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79176754Syongari#define RL_CFG2 0x0053 /* config register #2 */ 80176754Syongari#define RL_CFG3 0x0054 /* config register #3 */ 81176754Syongari#define RL_CFG4 0x0055 /* config register #4 */ 82176754Syongari#define RL_CFG5 0x0056 /* config register #5 */ 83176754Syongari /* 0057 reserved */ 8440516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8540516Swpaul /* 0059-005A reserved */ 8640516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8740516Swpaul#define RL_HALTCLK 0x005B 8840516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8940516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 9040516Swpaul /* 005F reserved */ 9140516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 9240516Swpaul 9340516Swpaul/* Direct PHY access registers only available on 8139 */ 9440516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9540516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9640516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9740516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9840516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9940516Swpaul 10040516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 10140516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 10240516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 10340516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10440516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10540516Swpaul 106117388Swpaul/* 107117388Swpaul * When operating in special C+ mode, some of the registers in an 108117388Swpaul * 8139C+ chip have different definitions. These are also used for 109117388Swpaul * the 8169 gigE chip. 110117388Swpaul */ 111117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 112117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 113117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 114117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 115117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 116117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 117120043Swpaul#define RL_CFG2 0x0053 118117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 119117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 120117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 121117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 122117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 123117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12440516Swpaul 12540516Swpaul/* 126117388Swpaul * Registers specific to the 8169 gigE chip 127117388Swpaul */ 128118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129117388Swpaul#define RL_PHYAR 0x0060 130117388Swpaul#define RL_TBICSR 0x0064 131117388Swpaul#define RL_TBI_ANAR 0x0068 132117388Swpaul#define RL_TBI_LPAR 0x006A 133117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 134117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135175337Syongari#define RL_GTXSTART 0x0038 /* 8 bits */ 136117388Swpaul 137117388Swpaul/* 13840516Swpaul * TX config register bits 13940516Swpaul */ 14040516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 14145633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 14240516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 14345633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 144119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14545633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 146117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14740516Swpaul 148119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 149119868Swpaul#define RL_LOOPTEST_ON 0x00020000 150119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 151119868Swpaul 152159962Swpaul/* Known revision codes. */ 153117388Swpaul 154160843Swpaul#define RL_HWREV_8169 0x00000000 155160843Swpaul#define RL_HWREV_8110S 0x00800000 156160843Swpaul#define RL_HWREV_8169S 0x04000000 157160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 158160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 159160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 160160843Swpaul#define RL_HWREV_8100E 0x30800000 161160843Swpaul#define RL_HWREV_8101E 0x34000000 162160843Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 163174428Syongari#define RL_HWREV_8168_SPIN3 0x38400000 164160843Swpaul#define RL_HWREV_8139 0x60000000 165160843Swpaul#define RL_HWREV_8139A 0x70000000 166160843Swpaul#define RL_HWREV_8139AG 0x70800000 167160843Swpaul#define RL_HWREV_8139B 0x78000000 168160843Swpaul#define RL_HWREV_8130 0x7C000000 169160843Swpaul#define RL_HWREV_8139C 0x74000000 170160843Swpaul#define RL_HWREV_8139D 0x74400000 171160843Swpaul#define RL_HWREV_8139CPLUS 0x74800000 172160843Swpaul#define RL_HWREV_8101 0x74c00000 173160843Swpaul#define RL_HWREV_8100 0x78800000 174159962Swpaul 17545633Swpaul#define RL_TXDMA_16BYTES 0x00000000 17645633Swpaul#define RL_TXDMA_32BYTES 0x00000100 17745633Swpaul#define RL_TXDMA_64BYTES 0x00000200 17845633Swpaul#define RL_TXDMA_128BYTES 0x00000300 17945633Swpaul#define RL_TXDMA_256BYTES 0x00000400 18045633Swpaul#define RL_TXDMA_512BYTES 0x00000500 18145633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 18245633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 18345633Swpaul 18440516Swpaul/* 18540516Swpaul * Transmit descriptor status register bits. 18640516Swpaul */ 18740516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 18840516Swpaul#define RL_TXSTAT_OWN 0x00002000 18940516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 19040516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 19140516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 19240516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 19340516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 19440516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 19540516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 19640516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 19740516Swpaul 19840516Swpaul/* 19940516Swpaul * Interrupt status register bits. 20040516Swpaul */ 20140516Swpaul#define RL_ISR_RX_OK 0x0001 20240516Swpaul#define RL_ISR_RX_ERR 0x0002 20340516Swpaul#define RL_ISR_TX_OK 0x0004 20440516Swpaul#define RL_ISR_TX_ERR 0x0008 20540516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 20640516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 207119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 20840516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 209117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 210117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 211117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 21240516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 213117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 21440516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 21540516Swpaul 21640516Swpaul#define RL_INTRS \ 21740516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 21840516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 21940516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 22040516Swpaul 221159962Swpaul#ifdef RE_TX_MODERATION 222117388Swpaul#define RL_INTRS_CPLUS \ 223119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 224117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 226159962Swpaul#else 227159962Swpaul#define RL_INTRS_CPLUS \ 228159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 229159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 230159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 231159962Swpaul#endif 232117388Swpaul 23340516Swpaul/* 23440516Swpaul * Media status register. (8139 only) 23540516Swpaul */ 23640516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 23740516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 23840516Swpaul#define RL_MEDIASTAT_LINK 0x04 23940516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 24040516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 24140516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 24240516Swpaul 24340516Swpaul/* 24440516Swpaul * Receive config register. 24540516Swpaul */ 24640516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 24740516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 24840516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 24940516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 25040516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 25140516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 25240516Swpaul#define RL_RXCFG_WRAP 0x00000080 25345633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 25445633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 25545633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 25645633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 25740516Swpaul 25845633Swpaul#define RL_RXDMA_16BYTES 0x00000000 25945633Swpaul#define RL_RXDMA_32BYTES 0x00000100 26045633Swpaul#define RL_RXDMA_64BYTES 0x00000200 26145633Swpaul#define RL_RXDMA_128BYTES 0x00000300 26245633Swpaul#define RL_RXDMA_256BYTES 0x00000400 26345633Swpaul#define RL_RXDMA_512BYTES 0x00000500 26445633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 26545633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 26645633Swpaul 26740516Swpaul#define RL_RXBUF_8 0x00000000 26840516Swpaul#define RL_RXBUF_16 0x00000800 26940516Swpaul#define RL_RXBUF_32 0x00001000 27045633Swpaul#define RL_RXBUF_64 0x00001800 27140516Swpaul 27245633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 27345633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 27445633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 27545633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 27645633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 27745633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 27845633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 27945633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 28045633Swpaul 28140516Swpaul/* 28240516Swpaul * Bits in RX status header (included with RX'ed packet 28340516Swpaul * in ring buffer). 28440516Swpaul */ 28540516Swpaul#define RL_RXSTAT_RXOK 0x00000001 28640516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 28740516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 28840516Swpaul#define RL_RXSTAT_GIANT 0x00000008 28940516Swpaul#define RL_RXSTAT_RUNT 0x00000010 29040516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 29140516Swpaul#define RL_RXSTAT_BROAD 0x00002000 29240516Swpaul#define RL_RXSTAT_INDIV 0x00004000 29340516Swpaul#define RL_RXSTAT_MULTI 0x00008000 29440516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 29540516Swpaul 29640516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 29740516Swpaul/* 29840516Swpaul * Command register. 29940516Swpaul */ 30040516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 30140516Swpaul#define RL_CMD_TX_ENB 0x0004 30240516Swpaul#define RL_CMD_RX_ENB 0x0008 30340516Swpaul#define RL_CMD_RESET 0x0010 30440516Swpaul 30540516Swpaul/* 30640516Swpaul * EEPROM control register 30740516Swpaul */ 30840516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 30940516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 31040516Swpaul#define RL_EE_CLK 0x04 /* clock */ 31140516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 31240516Swpaul#define RL_EE_MODE (0x40|0x80) 31340516Swpaul 31440516Swpaul#define RL_EEMODE_OFF 0x00 31540516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 31640516Swpaul#define RL_EEMODE_PROGRAM 0x80 31740516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 31840516Swpaul 31940516Swpaul/* 9346 EEPROM commands */ 320171263Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 321171263Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 322159962Swpaul 323159962Swpaul#define RL_9346_WRITE 0x5 324159962Swpaul#define RL_9346_READ 0x6 325159962Swpaul#define RL_9346_ERASE 0x7 326159962Swpaul#define RL_9346_EWEN 0x4 327159962Swpaul#define RL_9346_EWEN_ADDR 0x30 328159962Swpaul#define RL_9456_EWDS 0x4 329159962Swpaul#define RL_9346_EWDS_ADDR 0x00 330159962Swpaul 33140516Swpaul#define RL_EECMD_WRITE 0x140 33267931Swpaul#define RL_EECMD_READ_6BIT 0x180 33367931Swpaul#define RL_EECMD_READ_8BIT 0x600 33440516Swpaul#define RL_EECMD_ERASE 0x1c0 33540516Swpaul 33640516Swpaul#define RL_EE_ID 0x00 33740516Swpaul#define RL_EE_PCI_VID 0x01 33840516Swpaul#define RL_EE_PCI_DID 0x02 33940516Swpaul/* Location of station address inside EEPROM */ 34040516Swpaul#define RL_EE_EADDR 0x07 34140516Swpaul 34240516Swpaul/* 34340516Swpaul * MII register (8129 only) 34440516Swpaul */ 34540516Swpaul#define RL_MII_CLK 0x01 34640516Swpaul#define RL_MII_DATAIN 0x02 34740516Swpaul#define RL_MII_DATAOUT 0x04 34840516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 34940516Swpaul 35040516Swpaul/* 35140516Swpaul * Config 0 register 35240516Swpaul */ 35340516Swpaul#define RL_CFG0_ROM0 0x01 35440516Swpaul#define RL_CFG0_ROM1 0x02 35540516Swpaul#define RL_CFG0_ROM2 0x04 35640516Swpaul#define RL_CFG0_PL0 0x08 35740516Swpaul#define RL_CFG0_PL1 0x10 35840516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 35940516Swpaul#define RL_CFG0_PCS 0x40 36040516Swpaul#define RL_CFG0_SCR 0x80 36140516Swpaul 36240516Swpaul/* 36340516Swpaul * Config 1 register 36440516Swpaul */ 36540516Swpaul#define RL_CFG1_PWRDWN 0x01 366176754Syongari#define RL_CFG1_PME 0x01 36740516Swpaul#define RL_CFG1_SLEEP 0x02 368176754Syongari#define RL_CFG1_VPDEN 0x02 36940516Swpaul#define RL_CFG1_IOMAP 0x04 37040516Swpaul#define RL_CFG1_MEMMAP 0x08 37140516Swpaul#define RL_CFG1_RSVD 0x10 372176754Syongari#define RL_CFG1_LWACT 0x10 37340516Swpaul#define RL_CFG1_DRVLOAD 0x20 37440516Swpaul#define RL_CFG1_LED0 0x40 37540516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 37640516Swpaul#define RL_CFG1_LED1 0x80 37740516Swpaul 37840516Swpaul/* 379176754Syongari * Config 2 register 380176754Syongari */ 381176754Syongari#define RL_CFG2_PCI33MHZ 0x00 382176754Syongari#define RL_CFG2_PCI66MHZ 0x01 383176754Syongari#define RL_CFG2_PCI64BIT 0x08 384176754Syongari#define RL_CFG2_AUXPWR 0x10 385176754Syongari 386176754Syongari/* 387176754Syongari * Config 3 register 388176754Syongari */ 389176754Syongari#define RL_CFG3_GRANTSEL 0x80 390176754Syongari#define RL_CFG3_WOL_MAGIC 0x20 391176754Syongari#define RL_CFG3_WOL_LINK 0x10 392176754Syongari#define RL_CFG3_FAST_B2B 0x01 393176754Syongari 394176754Syongari/* 395176754Syongari * Config 4 register 396176754Syongari */ 397176754Syongari#define RL_CFG4_LWPTN 0x04 398176754Syongari#define RL_CFG4_LWPME 0x10 399176754Syongari 400176754Syongari/* 401176754Syongari * Config 5 register 402176754Syongari */ 403176754Syongari#define RL_CFG5_WOL_BCAST 0x40 404176754Syongari#define RL_CFG5_WOL_MCAST 0x20 405176754Syongari#define RL_CFG5_WOL_UCAST 0x10 406176754Syongari#define RL_CFG5_WOL_LANWAKE 0x02 407176754Syongari#define RL_CFG5_PME_STS 0x01 408176754Syongari 409176754Syongari/* 410117388Swpaul * 8139C+ register definitions 411117388Swpaul */ 412117388Swpaul 413117388Swpaul/* RL_DUMPSTATS_LO register */ 414117388Swpaul 415117388Swpaul#define RL_DUMPSTATS_START 0x00000008 416117388Swpaul 417117388Swpaul/* Transmit start register */ 418117388Swpaul 419117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 420117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 421117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 422117388Swpaul 423120043Swpaul/* 424120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 425120043Swpaul */ 426120043Swpaul#define RL_CFG2_BUSFREQ 0x07 427120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 428120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 429120043Swpaul 430120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 431120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 432120043Swpaul 433120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 434120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 435120043Swpaul 436117388Swpaul/* C+ mode command register */ 437117388Swpaul 438117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 439117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 440117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 441117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 442117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 443117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 444117388Swpaul 445117388Swpaul/* C+ early transmit threshold */ 446117388Swpaul 447117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 448117388Swpaul 449117388Swpaul/* 450117388Swpaul * Gigabit PHY access register (8169 only) 451117388Swpaul */ 452117388Swpaul 453117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 454117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 455117388Swpaul#define RL_PHYAR_BUSY 0x80000000 456117388Swpaul 457117388Swpaul/* 458117388Swpaul * Gigabit media status (8169 only) 459117388Swpaul */ 460117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 461117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 462117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 463117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 464119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 465117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 466117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 467117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 468117388Swpaul 469117388Swpaul/* 47040516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 47140516Swpaul * Instead, there are only four register sets, each or which represents 47240516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 47340516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 47440516Swpaul * the registers so the chip knows where they are. 47540516Swpaul * 47640516Swpaul * We can sort of kludge together the same kind of buffer management 47740516Swpaul * used in previous drivers, but we have to do buffer copies almost all 47840516Swpaul * the time, so it doesn't really buy us much. 47940516Swpaul * 48040516Swpaul * For reception, there's just one large buffer where the chip stores 48140516Swpaul * all received packets. 48240516Swpaul */ 48340516Swpaul 48440516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 48540516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 48640516Swpaul#define RL_TX_LIST_CNT 4 48740516Swpaul#define RL_MIN_FRAMELEN 60 48852426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 48952426Swpaul#define RL_TX_THRESH_INIT 96 490119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 491119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 49250703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 49340516Swpaul 49445633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 49545633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 49640516Swpaul 49748028Swpaul#define RL_ETHER_ALIGN 2 49848028Swpaul 49940516Swpaulstruct rl_chain_data { 500131605Sbms uint16_t cur_rx; 501131605Sbms uint8_t *rl_rx_buf; 502131605Sbms uint8_t *rl_rx_buf_ptr; 50381713Swpaul bus_dmamap_t rl_rx_dmamap; 50440516Swpaul 50545633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 50681713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 507131605Sbms uint8_t last_tx; 508131605Sbms uint8_t cur_tx; 50940516Swpaul}; 51040516Swpaul 51145633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 51245633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 51345633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 51445633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 51581713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 51645633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 51745633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 51845633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 51981713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 52045633Swpaul 52140516Swpaulstruct rl_type { 522131605Sbms uint16_t rl_vid; 523131605Sbms uint16_t rl_did; 524117388Swpaul int rl_basetype; 52540516Swpaul char *rl_name; 52640516Swpaul}; 52740516Swpaul 528117388Swpaulstruct rl_hwrev { 529131605Sbms uint32_t rl_rev; 530117388Swpaul int rl_type; 531117388Swpaul char *rl_desc; 532117388Swpaul}; 533117388Swpaul 53440516Swpaulstruct rl_mii_frame { 535131605Sbms uint8_t mii_stdelim; 536131605Sbms uint8_t mii_opcode; 537131605Sbms uint8_t mii_phyaddr; 538131605Sbms uint8_t mii_regaddr; 539131605Sbms uint8_t mii_turnaround; 540131605Sbms uint16_t mii_data; 54140516Swpaul}; 54240516Swpaul 54340516Swpaul/* 54440516Swpaul * MII constants 54540516Swpaul */ 54640516Swpaul#define RL_MII_STARTDELIM 0x01 54740516Swpaul#define RL_MII_READOP 0x02 54840516Swpaul#define RL_MII_WRITEOP 0x01 54940516Swpaul#define RL_MII_TURNAROUND 0x02 55040516Swpaul 55140516Swpaul#define RL_8129 1 55240516Swpaul#define RL_8139 2 553117388Swpaul#define RL_8139CPLUS 3 554117388Swpaul#define RL_8169 4 55540516Swpaul 556117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 557117388Swpaul (x)->rl_type == RL_8169) 558117388Swpaul 559117388Swpaul/* 560117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 561117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 562117388Swpaul * must be allocated in contiguous blocks that are aligned on a 563117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 564117388Swpaul */ 565117388Swpaul 566117388Swpaul/* 567117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 568117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 569117388Swpaul * the checksum offload bits are disabled. The structure layout is 570117388Swpaul * the same for RX and TX descriptors 571117388Swpaul */ 572117388Swpaul 573117388Swpaulstruct rl_desc { 574131605Sbms uint32_t rl_cmdstat; 575131605Sbms uint32_t rl_vlanctl; 576131605Sbms uint32_t rl_bufaddr_lo; 577131605Sbms uint32_t rl_bufaddr_hi; 578117388Swpaul}; 579117388Swpaul 580117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 581117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 582117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 583117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 584117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 585164463Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 586117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 587117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 588117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 589117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 590117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 591117388Swpaul 592117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 593117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 594117388Swpaul 595117388Swpaul/* 596117388Swpaul * Error bits are valid only on the last descriptor of a frame 597117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 598117388Swpaul */ 599117388Swpaul 600117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 601117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 602117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 603117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 604117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 605117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 606117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 607117388Swpaul 608117388Swpaul/* 609117388Swpaul * RX descriptor cmd/vlan definitions 610117388Swpaul */ 611117388Swpaul 612117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 613117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 614119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 615117388Swpaul 616117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 617117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 618117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 619117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 620117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 621117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 622117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 623117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 624117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 625117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 626117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 627117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 628117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 629117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 630117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 631117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 632117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 633117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 634119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 635119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 636135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 637135896Sjmg RL_RDESC_STAT_CRCERR) 638117388Swpaul 639117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 640117388Swpaul (rl_vlandata valid)*/ 641117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 642117388Swpaul 643117388Swpaul#define RL_PROTOID_NONIP 0x00000000 644117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 645117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 646117388Swpaul#define RL_PROTOID_IP 0x00030000 647117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 648117388Swpaul RL_PROTOID_TCPIP) 649117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 650117388Swpaul RL_PROTOID_UDPIP) 651117388Swpaul 652117388Swpaul/* 653117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 654117388Swpaul */ 655117388Swpaulstruct rl_stats { 656131605Sbms uint32_t rl_tx_pkts_lo; 657131605Sbms uint32_t rl_tx_pkts_hi; 658131605Sbms uint32_t rl_tx_errs_lo; 659131605Sbms uint32_t rl_tx_errs_hi; 660131605Sbms uint32_t rl_tx_errs; 661131605Sbms uint16_t rl_missed_pkts; 662131605Sbms uint16_t rl_rx_framealign_errs; 663131605Sbms uint32_t rl_tx_onecoll; 664131605Sbms uint32_t rl_tx_multicolls; 665131605Sbms uint32_t rl_rx_ucasts_hi; 666131605Sbms uint32_t rl_rx_ucasts_lo; 667131605Sbms uint32_t rl_rx_bcasts_lo; 668131605Sbms uint32_t rl_rx_bcasts_hi; 669131605Sbms uint32_t rl_rx_mcasts; 670131605Sbms uint16_t rl_tx_aborts; 671131605Sbms uint16_t rl_rx_underruns; 672117388Swpaul}; 673117388Swpaul 674135467Sjmg/* 675135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 676135467Sjmg * 677175337Syongari * 8139C+ 678175337Syongari * Number of descriptors supported : up to 64 679175337Syongari * Descriptor alignment : 256 bytes 680175337Syongari * Tx buffer : At least 4 bytes in length. 681175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 682175337Syongari * 683175337Syongari * 8169 684175337Syongari * Number of descriptors supported : up to 1024 685175337Syongari * Descriptor alignment : 256 bytes 686175337Syongari * Tx buffer : At least 4 bytes in length. 687175337Syongari * Rx buffer : At least 8 bytes in length and 8 bytes alignment required. 688135467Sjmg */ 689164460Syongari#ifndef __NO_STRICT_ALIGNMENT 690135896Sjmg#define RE_FIXUP_RX 1 691135896Sjmg#endif 692135896Sjmg 693175337Syongari#define RL_8169_TX_DESC_CNT 256 694175337Syongari#define RL_8169_RX_DESC_CNT 256 695175337Syongari#define RL_8139_TX_DESC_CNT 64 696175337Syongari#define RL_8139_RX_DESC_CNT 64 697175337Syongari#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT 698175337Syongari#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT 699175337Syongari#define RL_NTXSEGS 32 700159962Swpaul 701117388Swpaul#define RL_RING_ALIGN 256 702117388Swpaul#define RL_IFQ_MAXLEN 512 703175337Syongari#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 704175337Syongari#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1)) 705175337Syongari#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1)) 706117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 707119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 708119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 709135896Sjmg#ifdef RE_FIXUP_RX 710135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 711135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 712135896Sjmg#else 713135896Sjmg#define RE_ETHER_ALIGN 0 714135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 715135896Sjmg#endif 716117388Swpaul 717171560Syongari#define RL_MSI_MESSAGES 2 718171560Syongari 719135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 720135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 721118712Swpaul 722135896Sjmg/* see comment in dev/re/if_re.c */ 723135896Sjmg#define RL_JUMBO_FRAMELEN 7440 724119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 725119868Swpaul 726175337Syongaristruct rl_txdesc { 727175337Syongari struct mbuf *tx_m; 728175337Syongari bus_dmamap_t tx_dmamap; 729175337Syongari}; 730117388Swpaul 731175337Syongaristruct rl_rxdesc { 732175337Syongari struct mbuf *rx_m; 733175337Syongari bus_dmamap_t rx_dmamap; 734175337Syongari bus_size_t rx_size; 735117388Swpaul}; 736117388Swpaul 737117388Swpaulstruct rl_list_data { 738175337Syongari struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT]; 739175337Syongari struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT]; 740175337Syongari int rl_tx_desc_cnt; 741175337Syongari int rl_rx_desc_cnt; 742117388Swpaul int rl_tx_prodidx; 743117388Swpaul int rl_rx_prodidx; 744117388Swpaul int rl_tx_considx; 745117388Swpaul int rl_tx_free; 746175337Syongari bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */ 747175337Syongari bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */ 748175337Syongari bus_dmamap_t rl_rx_sparemap; 749117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 750117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 751117388Swpaul struct rl_stats *rl_stats; 752118712Swpaul bus_addr_t rl_stats_addr; 753117388Swpaul bus_dma_tag_t rl_rx_list_tag; 754117388Swpaul bus_dmamap_t rl_rx_list_map; 755117388Swpaul struct rl_desc *rl_rx_list; 756118712Swpaul bus_addr_t rl_rx_list_addr; 757117388Swpaul bus_dma_tag_t rl_tx_list_tag; 758117388Swpaul bus_dmamap_t rl_tx_list_map; 759117388Swpaul struct rl_desc *rl_tx_list; 760118712Swpaul bus_addr_t rl_tx_list_addr; 761117388Swpaul}; 762117388Swpaul 76340516Swpaulstruct rl_softc { 764147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 76541569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 76641569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 767159962Swpaul device_t rl_dev; 76850703Swpaul struct resource *rl_res; 769171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 770171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 77150703Swpaul device_t rl_miibus; 77281713Swpaul bus_dma_tag_t rl_parent_tag; 77381713Swpaul bus_dma_tag_t rl_tag; 774131605Sbms uint8_t rl_type; 77567931Swpaul int rl_eecmd_read; 776159962Swpaul int rl_eewidth; 777131605Sbms uint8_t rl_stats_no_timeout; 77852426Swpaul int rl_txthresh; 77940516Swpaul struct rl_chain_data rl_cdata; 780117388Swpaul struct rl_list_data rl_ldata; 781150720Sjhb struct callout rl_stat_callout; 782164811Sru int rl_watchdog_timer; 78367087Swpaul struct mtx rl_mtx; 784119868Swpaul struct mbuf *rl_head; 785119868Swpaul struct mbuf *rl_tail; 786131605Sbms uint32_t rl_hwrev; 787131605Sbms uint32_t rl_rxlenmask; 788119868Swpaul int rl_testmode; 789168828Syongari int rl_if_flags; 79086822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 79194883Sluigi#ifdef DEVICE_POLLING 79294883Sluigi int rxcycles; 79394883Sluigi#endif 794159962Swpaul 795159962Swpaul struct task rl_txtask; 796159962Swpaul struct task rl_inttask; 797159962Swpaul 798159962Swpaul int rl_txstart; 799159962Swpaul int rl_link; 800171560Syongari int rl_msi; 80140516Swpaul}; 80240516Swpaul 80372200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 80472200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 805122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 80667087Swpaul 80740516Swpaul/* 80840516Swpaul * register space access macros 80940516Swpaul */ 810119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 811119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 81240516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 81341569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 81440516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 81541569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 81640516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 81741569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 81840516Swpaul 81941569Swpaul#define CSR_READ_4(sc, reg) \ 82041569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 82141569Swpaul#define CSR_READ_2(sc, reg) \ 82241569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 82341569Swpaul#define CSR_READ_1(sc, reg) \ 82441569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 82540516Swpaul 826159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 827159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 828159962Swpaul 829159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 830159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 831159962Swpaul 832159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 833159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 834159962Swpaul 835159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 836159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 837159962Swpaul 838159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 839159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 840159962Swpaul 841159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 842159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 843159962Swpaul 84440516Swpaul#define RL_TIMEOUT 1000 84540516Swpaul 84640516Swpaul/* 84740516Swpaul * General constants that are fun to know. 84840516Swpaul * 84940516Swpaul * RealTek PCI vendor ID 85040516Swpaul */ 85140516Swpaul#define RT_VENDORID 0x10EC 85240516Swpaul 85340516Swpaul/* 85440516Swpaul * RealTek chip device IDs. 85540516Swpaul */ 85640516Swpaul#define RT_DEVICEID_8129 0x8129 857159962Swpaul#define RT_DEVICEID_8101E 0x8136 85867771Swpaul#define RT_DEVICEID_8138 0x8138 85940516Swpaul#define RT_DEVICEID_8139 0x8139 860159962Swpaul#define RT_DEVICEID_8169SC 0x8167 861159962Swpaul#define RT_DEVICEID_8168 0x8168 862117388Swpaul#define RT_DEVICEID_8169 0x8169 863118978Swpaul#define RT_DEVICEID_8100 0x8100 86440516Swpaul 865117388Swpaul#define RT_REVID_8139CPLUS 0x20 866117388Swpaul 86740516Swpaul/* 86844238Swpaul * Accton PCI vendor ID 86944238Swpaul */ 87044238Swpaul#define ACCTON_VENDORID 0x1113 87144238Swpaul 87244238Swpaul/* 87341243Swpaul * Accton MPX 5030/5038 device ID. 87441243Swpaul */ 87541243Swpaul#define ACCTON_DEVICEID_5030 0x1211 87641243Swpaul 87741243Swpaul/* 87894400Swpaul * Nortel PCI vendor ID 87994400Swpaul */ 88094400Swpaul#define NORTEL_VENDORID 0x126C 88194400Swpaul 88294400Swpaul/* 88344238Swpaul * Delta Electronics Vendor ID. 88444238Swpaul */ 88544238Swpaul#define DELTA_VENDORID 0x1500 88644238Swpaul 88744238Swpaul/* 88844238Swpaul * Delta device IDs. 88944238Swpaul */ 89044238Swpaul#define DELTA_DEVICEID_8139 0x1360 89144238Swpaul 89244238Swpaul/* 89344238Swpaul * Addtron vendor ID. 89444238Swpaul */ 89544238Swpaul#define ADDTRON_VENDORID 0x4033 89644238Swpaul 89744238Swpaul/* 89844238Swpaul * Addtron device IDs. 89944238Swpaul */ 90044238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 90144238Swpaul 90244238Swpaul/* 90372813Swpaul * D-Link vendor ID. 90472813Swpaul */ 90572813Swpaul#define DLINK_VENDORID 0x1186 90672813Swpaul 90772813Swpaul/* 90872813Swpaul * D-Link DFE-530TX+ device ID 90972813Swpaul */ 91072813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 91172813Swpaul 91272813Swpaul/* 913148722Stobez * D-Link DFE-5280T device ID 914148722Stobez */ 915148722Stobez#define DLINK_DEVICEID_528T 0x4300 916148722Stobez 917148722Stobez/* 91896112Sjhb * D-Link DFE-690TXD device ID 91996112Sjhb */ 92096112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 92196112Sjhb 92296112Sjhb/* 923103020Siwasaki * Corega K.K vendor ID 924103020Siwasaki */ 925103020Siwasaki#define COREGA_VENDORID 0x1259 926103020Siwasaki 927103020Siwasaki/* 928109095Ssanpei * Corega FEther CB-TXD device ID 929103020Siwasaki */ 930151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 931103020Siwasaki 932103020Siwasaki/* 933109095Ssanpei * Corega FEtherII CB-TXD device ID 934109095Ssanpei */ 935151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 936109095Ssanpei 937111381Sdan/* 938134433Ssanpei * Corega CG-LAPCIGT device ID 939134433Ssanpei */ 940134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 941134433Ssanpei 942134433Ssanpei/* 943151341Sjhb * Linksys vendor ID 944151341Sjhb */ 945151341Sjhb#define LINKSYS_VENDORID 0x1737 946151341Sjhb 947151341Sjhb/* 948151341Sjhb * Linksys EG1032 device ID 949151341Sjhb */ 950151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 951151341Sjhb 952151341Sjhb/* 953151341Sjhb * Linksys EG1032 rev 3 sub-device ID 954151341Sjhb */ 955151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 956151341Sjhb 957151341Sjhb/* 958111381Sdan * Peppercon vendor ID 959111381Sdan */ 960111381Sdan#define PEPPERCON_VENDORID 0x1743 961109095Ssanpei 962111381Sdan/* 963111381Sdan * Peppercon ROL-F device ID 964111381Sdan */ 965111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 966109095Ssanpei 967109095Ssanpei/* 968112379Ssanpei * Planex Communications, Inc. vendor ID 969112379Ssanpei */ 970117388Swpaul#define PLANEX_VENDORID 0x14ea 971112379Ssanpei 972112379Ssanpei/* 973173948Sremko * Planex FNW-3603-TX device ID 974173948Sremko */ 975173948Sremko#define PLANEX_DEVICEID_FNW3603TX 0xab06 976173948Sremko 977173948Sremko/* 978112379Ssanpei * Planex FNW-3800-TX device ID 979112379Ssanpei */ 980117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 981112379Ssanpei 982112379Ssanpei/* 983117388Swpaul * LevelOne vendor ID 984117388Swpaul */ 985117388Swpaul#define LEVEL1_VENDORID 0x018A 986117388Swpaul 987117388Swpaul/* 988117388Swpaul * LevelOne FPC-0106TX devide ID 989117388Swpaul */ 990117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 991117388Swpaul 992117388Swpaul/* 993117388Swpaul * Compaq vendor ID 994117388Swpaul */ 995117388Swpaul#define CP_VENDORID 0x021B 996117388Swpaul 997117388Swpaul/* 998117388Swpaul * Edimax vendor ID 999117388Swpaul */ 1000117388Swpaul#define EDIMAX_VENDORID 0x13D1 1001117388Swpaul 1002117388Swpaul/* 1003117388Swpaul * Edimax EP-4103DL cardbus device ID 1004117388Swpaul */ 1005117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 1006117388Swpaul 1007160883Swpaul/* US Robotics vendor ID */ 1008160883Swpaul 1009160883Swpaul#define USR_VENDORID 0x16EC 1010160883Swpaul 1011160883Swpaul/* US Robotics 997902 device ID */ 1012160883Swpaul 1013160883Swpaul#define USR_DEVICEID_997902 0x0116 1014160883Swpaul 1015117388Swpaul/* 101640516Swpaul * PCI low memory base and low I/O base register, and 101750703Swpaul * other PCI registers. 101840516Swpaul */ 101940516Swpaul 102040516Swpaul#define RL_PCI_VENDOR_ID 0x00 102140516Swpaul#define RL_PCI_DEVICE_ID 0x02 102240516Swpaul#define RL_PCI_COMMAND 0x04 102340516Swpaul#define RL_PCI_STATUS 0x06 102440516Swpaul#define RL_PCI_CLASSCODE 0x09 102540516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 102640516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 102740516Swpaul#define RL_PCI_LOIO 0x10 102840516Swpaul#define RL_PCI_LOMEM 0x14 102940516Swpaul#define RL_PCI_BIOSROM 0x30 103040516Swpaul#define RL_PCI_INTLINE 0x3C 103140516Swpaul#define RL_PCI_INTPIN 0x3D 103240516Swpaul#define RL_PCI_MINGNT 0x3E 103340516Swpaul#define RL_PCI_MINLAT 0x0F 103440516Swpaul#define RL_PCI_RESETOPT 0x48 103540516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 103640516Swpaul 103750097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 103850097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 103950097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 104050097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 104140516Swpaul 104240516Swpaul#define RL_PSTATE_MASK 0x0003 104340516Swpaul#define RL_PSTATE_D0 0x0000 104440516Swpaul#define RL_PSTATE_D1 0x0002 104540516Swpaul#define RL_PSTATE_D2 0x0002 104640516Swpaul#define RL_PSTATE_D3 0x0003 104740516Swpaul#define RL_PME_EN 0x0010 104840516Swpaul#define RL_PME_STATUS 0x8000 1049