if_rlreg.h revision 171560
1139825Simp/*- 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 171560 2007-07-24 01:24:03Z yongari $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79120043Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113120043Swpaul#define RL_CFG2 0x0053 114117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 116117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12040516Swpaul 12140516Swpaul/* 122117388Swpaul * Registers specific to the 8169 gigE chip 123117388Swpaul */ 124118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125117388Swpaul#define RL_PHYAR 0x0060 126117388Swpaul#define RL_TBICSR 0x0064 127117388Swpaul#define RL_TBI_ANAR 0x0068 128117388Swpaul#define RL_TBI_LPAR 0x006A 129117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 132117388Swpaul 133117388Swpaul/* 13440516Swpaul * TX config register bits 13540516Swpaul */ 13640516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13745633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13840516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13945633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14145633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14340516Swpaul 144119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 145119868Swpaul#define RL_LOOPTEST_ON 0x00020000 146119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 147119868Swpaul 148159962Swpaul/* Known revision codes. */ 149117388Swpaul 150160843Swpaul#define RL_HWREV_8169 0x00000000 151160843Swpaul#define RL_HWREV_8110S 0x00800000 152160843Swpaul#define RL_HWREV_8169S 0x04000000 153160843Swpaul#define RL_HWREV_8169_8110SB 0x10000000 154160843Swpaul#define RL_HWREV_8169_8110SC 0x18000000 155160843Swpaul#define RL_HWREV_8168_SPIN1 0x30000000 156160843Swpaul#define RL_HWREV_8100E 0x30800000 157160843Swpaul#define RL_HWREV_8101E 0x34000000 158160843Swpaul#define RL_HWREV_8168_SPIN2 0x38000000 159160843Swpaul#define RL_HWREV_8139 0x60000000 160160843Swpaul#define RL_HWREV_8139A 0x70000000 161160843Swpaul#define RL_HWREV_8139AG 0x70800000 162160843Swpaul#define RL_HWREV_8139B 0x78000000 163160843Swpaul#define RL_HWREV_8130 0x7C000000 164160843Swpaul#define RL_HWREV_8139C 0x74000000 165160843Swpaul#define RL_HWREV_8139D 0x74400000 166160843Swpaul#define RL_HWREV_8139CPLUS 0x74800000 167160843Swpaul#define RL_HWREV_8101 0x74c00000 168160843Swpaul#define RL_HWREV_8100 0x78800000 169159962Swpaul 17045633Swpaul#define RL_TXDMA_16BYTES 0x00000000 17145633Swpaul#define RL_TXDMA_32BYTES 0x00000100 17245633Swpaul#define RL_TXDMA_64BYTES 0x00000200 17345633Swpaul#define RL_TXDMA_128BYTES 0x00000300 17445633Swpaul#define RL_TXDMA_256BYTES 0x00000400 17545633Swpaul#define RL_TXDMA_512BYTES 0x00000500 17645633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 17745633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 17845633Swpaul 17940516Swpaul/* 18040516Swpaul * Transmit descriptor status register bits. 18140516Swpaul */ 18240516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 18340516Swpaul#define RL_TXSTAT_OWN 0x00002000 18440516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 18540516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 18640516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 18740516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 18840516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 18940516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 19040516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 19140516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 19240516Swpaul 19340516Swpaul/* 19440516Swpaul * Interrupt status register bits. 19540516Swpaul */ 19640516Swpaul#define RL_ISR_RX_OK 0x0001 19740516Swpaul#define RL_ISR_RX_ERR 0x0002 19840516Swpaul#define RL_ISR_TX_OK 0x0004 19940516Swpaul#define RL_ISR_TX_ERR 0x0008 20040516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 20140516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 202119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 20340516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 204117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 205117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 206117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 20740516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 208117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 20940516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 21040516Swpaul 21140516Swpaul#define RL_INTRS \ 21240516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 21340516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 21440516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 21540516Swpaul 216159962Swpaul#ifdef RE_TX_MODERATION 217117388Swpaul#define RL_INTRS_CPLUS \ 218119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 219117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 220117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 221159962Swpaul#else 222159962Swpaul#define RL_INTRS_CPLUS \ 223159962Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \ 224159962Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 225159962Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 226159962Swpaul#endif 227117388Swpaul 22840516Swpaul/* 22940516Swpaul * Media status register. (8139 only) 23040516Swpaul */ 23140516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 23240516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 23340516Swpaul#define RL_MEDIASTAT_LINK 0x04 23440516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 23540516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 23640516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 23740516Swpaul 23840516Swpaul/* 23940516Swpaul * Receive config register. 24040516Swpaul */ 24140516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 24240516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 24340516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 24440516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 24540516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 24640516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 24740516Swpaul#define RL_RXCFG_WRAP 0x00000080 24845633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 24945633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 25045633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 25145633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 25240516Swpaul 25345633Swpaul#define RL_RXDMA_16BYTES 0x00000000 25445633Swpaul#define RL_RXDMA_32BYTES 0x00000100 25545633Swpaul#define RL_RXDMA_64BYTES 0x00000200 25645633Swpaul#define RL_RXDMA_128BYTES 0x00000300 25745633Swpaul#define RL_RXDMA_256BYTES 0x00000400 25845633Swpaul#define RL_RXDMA_512BYTES 0x00000500 25945633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 26045633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 26145633Swpaul 26240516Swpaul#define RL_RXBUF_8 0x00000000 26340516Swpaul#define RL_RXBUF_16 0x00000800 26440516Swpaul#define RL_RXBUF_32 0x00001000 26545633Swpaul#define RL_RXBUF_64 0x00001800 26640516Swpaul 26745633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 26845633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 26945633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 27045633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 27145633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 27245633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 27345633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 27445633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 27545633Swpaul 27640516Swpaul/* 27740516Swpaul * Bits in RX status header (included with RX'ed packet 27840516Swpaul * in ring buffer). 27940516Swpaul */ 28040516Swpaul#define RL_RXSTAT_RXOK 0x00000001 28140516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 28240516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 28340516Swpaul#define RL_RXSTAT_GIANT 0x00000008 28440516Swpaul#define RL_RXSTAT_RUNT 0x00000010 28540516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 28640516Swpaul#define RL_RXSTAT_BROAD 0x00002000 28740516Swpaul#define RL_RXSTAT_INDIV 0x00004000 28840516Swpaul#define RL_RXSTAT_MULTI 0x00008000 28940516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 29040516Swpaul 29140516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 29240516Swpaul/* 29340516Swpaul * Command register. 29440516Swpaul */ 29540516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 29640516Swpaul#define RL_CMD_TX_ENB 0x0004 29740516Swpaul#define RL_CMD_RX_ENB 0x0008 29840516Swpaul#define RL_CMD_RESET 0x0010 29940516Swpaul 30040516Swpaul/* 30140516Swpaul * EEPROM control register 30240516Swpaul */ 30340516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 30440516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 30540516Swpaul#define RL_EE_CLK 0x04 /* clock */ 30640516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 30740516Swpaul#define RL_EE_MODE (0x40|0x80) 30840516Swpaul 30940516Swpaul#define RL_EEMODE_OFF 0x00 31040516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 31140516Swpaul#define RL_EEMODE_PROGRAM 0x80 31240516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 31340516Swpaul 31440516Swpaul/* 9346 EEPROM commands */ 315171263Syongari#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */ 316171263Syongari#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */ 317159962Swpaul 318159962Swpaul#define RL_9346_WRITE 0x5 319159962Swpaul#define RL_9346_READ 0x6 320159962Swpaul#define RL_9346_ERASE 0x7 321159962Swpaul#define RL_9346_EWEN 0x4 322159962Swpaul#define RL_9346_EWEN_ADDR 0x30 323159962Swpaul#define RL_9456_EWDS 0x4 324159962Swpaul#define RL_9346_EWDS_ADDR 0x00 325159962Swpaul 32640516Swpaul#define RL_EECMD_WRITE 0x140 32767931Swpaul#define RL_EECMD_READ_6BIT 0x180 32867931Swpaul#define RL_EECMD_READ_8BIT 0x600 32940516Swpaul#define RL_EECMD_ERASE 0x1c0 33040516Swpaul 33140516Swpaul#define RL_EE_ID 0x00 33240516Swpaul#define RL_EE_PCI_VID 0x01 33340516Swpaul#define RL_EE_PCI_DID 0x02 33440516Swpaul/* Location of station address inside EEPROM */ 33540516Swpaul#define RL_EE_EADDR 0x07 33640516Swpaul 33740516Swpaul/* 33840516Swpaul * MII register (8129 only) 33940516Swpaul */ 34040516Swpaul#define RL_MII_CLK 0x01 34140516Swpaul#define RL_MII_DATAIN 0x02 34240516Swpaul#define RL_MII_DATAOUT 0x04 34340516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 34440516Swpaul 34540516Swpaul/* 34640516Swpaul * Config 0 register 34740516Swpaul */ 34840516Swpaul#define RL_CFG0_ROM0 0x01 34940516Swpaul#define RL_CFG0_ROM1 0x02 35040516Swpaul#define RL_CFG0_ROM2 0x04 35140516Swpaul#define RL_CFG0_PL0 0x08 35240516Swpaul#define RL_CFG0_PL1 0x10 35340516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 35440516Swpaul#define RL_CFG0_PCS 0x40 35540516Swpaul#define RL_CFG0_SCR 0x80 35640516Swpaul 35740516Swpaul/* 35840516Swpaul * Config 1 register 35940516Swpaul */ 36040516Swpaul#define RL_CFG1_PWRDWN 0x01 36140516Swpaul#define RL_CFG1_SLEEP 0x02 36240516Swpaul#define RL_CFG1_IOMAP 0x04 36340516Swpaul#define RL_CFG1_MEMMAP 0x08 36440516Swpaul#define RL_CFG1_RSVD 0x10 36540516Swpaul#define RL_CFG1_DRVLOAD 0x20 36640516Swpaul#define RL_CFG1_LED0 0x40 36740516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 36840516Swpaul#define RL_CFG1_LED1 0x80 36940516Swpaul 37040516Swpaul/* 371117388Swpaul * 8139C+ register definitions 372117388Swpaul */ 373117388Swpaul 374117388Swpaul/* RL_DUMPSTATS_LO register */ 375117388Swpaul 376117388Swpaul#define RL_DUMPSTATS_START 0x00000008 377117388Swpaul 378117388Swpaul/* Transmit start register */ 379117388Swpaul 380117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 381117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 382117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 383117388Swpaul 384120043Swpaul/* 385120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 386120043Swpaul */ 387120043Swpaul#define RL_CFG2_BUSFREQ 0x07 388120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 389120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 390120043Swpaul 391120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 392120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 393120043Swpaul 394120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 395120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 396120043Swpaul 397117388Swpaul/* C+ mode command register */ 398117388Swpaul 399117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 400117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 401117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 402117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 403117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 404117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 405117388Swpaul 406117388Swpaul/* C+ early transmit threshold */ 407117388Swpaul 408117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 409117388Swpaul 410117388Swpaul/* 411117388Swpaul * Gigabit PHY access register (8169 only) 412117388Swpaul */ 413117388Swpaul 414117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 415117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 416117388Swpaul#define RL_PHYAR_BUSY 0x80000000 417117388Swpaul 418117388Swpaul/* 419117388Swpaul * Gigabit media status (8169 only) 420117388Swpaul */ 421117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 422117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 423117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 424117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 425119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 426117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 427117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 428117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 429117388Swpaul 430117388Swpaul/* 43140516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 43240516Swpaul * Instead, there are only four register sets, each or which represents 43340516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 43440516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 43540516Swpaul * the registers so the chip knows where they are. 43640516Swpaul * 43740516Swpaul * We can sort of kludge together the same kind of buffer management 43840516Swpaul * used in previous drivers, but we have to do buffer copies almost all 43940516Swpaul * the time, so it doesn't really buy us much. 44040516Swpaul * 44140516Swpaul * For reception, there's just one large buffer where the chip stores 44240516Swpaul * all received packets. 44340516Swpaul */ 44440516Swpaul 44540516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 44640516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 44740516Swpaul#define RL_TX_LIST_CNT 4 44840516Swpaul#define RL_MIN_FRAMELEN 60 44952426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 45052426Swpaul#define RL_TX_THRESH_INIT 96 451119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 452119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 45350703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 45440516Swpaul 45545633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 45645633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 45740516Swpaul 45848028Swpaul#define RL_ETHER_ALIGN 2 45948028Swpaul 46040516Swpaulstruct rl_chain_data { 461131605Sbms uint16_t cur_rx; 462131605Sbms uint8_t *rl_rx_buf; 463131605Sbms uint8_t *rl_rx_buf_ptr; 46481713Swpaul bus_dmamap_t rl_rx_dmamap; 46540516Swpaul 46645633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 46781713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 468131605Sbms uint8_t last_tx; 469131605Sbms uint8_t cur_tx; 47040516Swpaul}; 47140516Swpaul 47245633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 47345633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 47445633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 47545633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 47681713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 47745633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 47845633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 47945633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 48081713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 48145633Swpaul 48240516Swpaulstruct rl_type { 483131605Sbms uint16_t rl_vid; 484131605Sbms uint16_t rl_did; 485117388Swpaul int rl_basetype; 48640516Swpaul char *rl_name; 48740516Swpaul}; 48840516Swpaul 489117388Swpaulstruct rl_hwrev { 490131605Sbms uint32_t rl_rev; 491117388Swpaul int rl_type; 492117388Swpaul char *rl_desc; 493117388Swpaul}; 494117388Swpaul 49540516Swpaulstruct rl_mii_frame { 496131605Sbms uint8_t mii_stdelim; 497131605Sbms uint8_t mii_opcode; 498131605Sbms uint8_t mii_phyaddr; 499131605Sbms uint8_t mii_regaddr; 500131605Sbms uint8_t mii_turnaround; 501131605Sbms uint16_t mii_data; 50240516Swpaul}; 50340516Swpaul 50440516Swpaul/* 50540516Swpaul * MII constants 50640516Swpaul */ 50740516Swpaul#define RL_MII_STARTDELIM 0x01 50840516Swpaul#define RL_MII_READOP 0x02 50940516Swpaul#define RL_MII_WRITEOP 0x01 51040516Swpaul#define RL_MII_TURNAROUND 0x02 51140516Swpaul 51240516Swpaul#define RL_8129 1 51340516Swpaul#define RL_8139 2 514117388Swpaul#define RL_8139CPLUS 3 515117388Swpaul#define RL_8169 4 51640516Swpaul 517117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 518117388Swpaul (x)->rl_type == RL_8169) 519117388Swpaul 520117388Swpaul/* 521117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 522117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 523117388Swpaul * must be allocated in contiguous blocks that are aligned on a 524117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 525117388Swpaul */ 526117388Swpaul 527117388Swpaul/* 528117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 529117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 530117388Swpaul * the checksum offload bits are disabled. The structure layout is 531117388Swpaul * the same for RX and TX descriptors 532117388Swpaul */ 533117388Swpaul 534117388Swpaulstruct rl_desc { 535131605Sbms uint32_t rl_cmdstat; 536131605Sbms uint32_t rl_vlanctl; 537131605Sbms uint32_t rl_bufaddr_lo; 538131605Sbms uint32_t rl_bufaddr_hi; 539117388Swpaul}; 540117388Swpaul 541117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 542117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 543117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 544117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 545117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 546164463Syongari#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */ 547117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 548117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 549117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 550117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 551117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 552117388Swpaul 553117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 554117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 555117388Swpaul 556117388Swpaul/* 557117388Swpaul * Error bits are valid only on the last descriptor of a frame 558117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 559117388Swpaul */ 560117388Swpaul 561117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 562117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 563117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 564117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 565117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 566117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 567117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 568117388Swpaul 569117388Swpaul/* 570117388Swpaul * RX descriptor cmd/vlan definitions 571117388Swpaul */ 572117388Swpaul 573117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 574117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 575119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 576117388Swpaul 577117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 578117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 579117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 580117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 581117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 582117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 583117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 584117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 585117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 586117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 587117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 588117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 589117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 590117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 591117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 592117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 593117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 594117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 595119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 596119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 597135896Sjmg#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \ 598135896Sjmg RL_RDESC_STAT_CRCERR) 599117388Swpaul 600117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 601117388Swpaul (rl_vlandata valid)*/ 602117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 603117388Swpaul 604117388Swpaul#define RL_PROTOID_NONIP 0x00000000 605117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 606117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 607117388Swpaul#define RL_PROTOID_IP 0x00030000 608117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 609117388Swpaul RL_PROTOID_TCPIP) 610117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 611117388Swpaul RL_PROTOID_UDPIP) 612117388Swpaul 613117388Swpaul/* 614117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 615117388Swpaul */ 616117388Swpaulstruct rl_stats { 617131605Sbms uint32_t rl_tx_pkts_lo; 618131605Sbms uint32_t rl_tx_pkts_hi; 619131605Sbms uint32_t rl_tx_errs_lo; 620131605Sbms uint32_t rl_tx_errs_hi; 621131605Sbms uint32_t rl_tx_errs; 622131605Sbms uint16_t rl_missed_pkts; 623131605Sbms uint16_t rl_rx_framealign_errs; 624131605Sbms uint32_t rl_tx_onecoll; 625131605Sbms uint32_t rl_tx_multicolls; 626131605Sbms uint32_t rl_rx_ucasts_hi; 627131605Sbms uint32_t rl_rx_ucasts_lo; 628131605Sbms uint32_t rl_rx_bcasts_lo; 629131605Sbms uint32_t rl_rx_bcasts_hi; 630131605Sbms uint32_t rl_rx_mcasts; 631131605Sbms uint16_t rl_tx_aborts; 632131605Sbms uint16_t rl_rx_underruns; 633117388Swpaul}; 634117388Swpaul 635135467Sjmg/* 636135467Sjmg * Rx/Tx descriptor parameters (8139C+ and 8169 only) 637135467Sjmg * 638135467Sjmg * Tx/Rx count must be equal. Shared code like re_dma_map_desc assumes this. 639135896Sjmg * Buffers must be a multiple of 8 bytes. Currently limit to 64 descriptors 640135896Sjmg * due to the 8139C+. We need to put the number of descriptors in the ring 641135896Sjmg * structure and use that value instead. 642135467Sjmg */ 643164460Syongari#ifndef __NO_STRICT_ALIGNMENT 644135896Sjmg#define RE_FIXUP_RX 1 645135896Sjmg#endif 646135896Sjmg 647117388Swpaul#define RL_TX_DESC_CNT 64 648166057Smarius#define RL_TX_DESC_THLD 4 649135469Sjmg#define RL_RX_DESC_CNT RL_TX_DESC_CNT 650159962Swpaul 651117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 652117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 653117388Swpaul#define RL_RING_ALIGN 256 654117388Swpaul#define RL_IFQ_MAXLEN 512 655117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 656117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 657119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 658119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 659135896Sjmg#ifdef RE_FIXUP_RX 660135896Sjmg#define RE_ETHER_ALIGN sizeof(uint64_t) 661135896Sjmg#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN) 662135896Sjmg#else 663135896Sjmg#define RE_ETHER_ALIGN 0 664135896Sjmg#define RE_RX_DESC_BUFLEN MCLBYTES 665135896Sjmg#endif 666117388Swpaul 667171560Syongari#define RL_MSI_MESSAGES 2 668171560Syongari 669135467Sjmg#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 670135467Sjmg#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32) 671118712Swpaul 672135896Sjmg/* see comment in dev/re/if_re.c */ 673135896Sjmg#define RL_JUMBO_FRAMELEN 7440 674119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 675119868Swpaul 676117388Swpaulstruct rl_softc; 677117388Swpaul 678117388Swpaulstruct rl_dmaload_arg { 679117388Swpaul int rl_idx; 680117388Swpaul int rl_maxsegs; 681131605Sbms uint32_t rl_flags; 682117388Swpaul struct rl_desc *rl_ring; 683117388Swpaul}; 684117388Swpaul 685117388Swpaulstruct rl_list_data { 686117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 687159962Swpaul struct mbuf *rl_rx_mbuf[RL_RX_DESC_CNT]; 688117388Swpaul int rl_tx_prodidx; 689117388Swpaul int rl_rx_prodidx; 690117388Swpaul int rl_tx_considx; 691117388Swpaul int rl_tx_free; 692117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 693117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 694117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 695117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 696117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 697117388Swpaul struct rl_stats *rl_stats; 698118712Swpaul bus_addr_t rl_stats_addr; 699117388Swpaul bus_dma_tag_t rl_rx_list_tag; 700117388Swpaul bus_dmamap_t rl_rx_list_map; 701117388Swpaul struct rl_desc *rl_rx_list; 702118712Swpaul bus_addr_t rl_rx_list_addr; 703117388Swpaul bus_dma_tag_t rl_tx_list_tag; 704117388Swpaul bus_dmamap_t rl_tx_list_map; 705117388Swpaul struct rl_desc *rl_tx_list; 706118712Swpaul bus_addr_t rl_tx_list_addr; 707117388Swpaul}; 708117388Swpaul 70940516Swpaulstruct rl_softc { 710147256Sbrooks struct ifnet *rl_ifp; /* interface info */ 71141569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 71241569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 713159962Swpaul device_t rl_dev; 71450703Swpaul struct resource *rl_res; 715171560Syongari struct resource *rl_irq[RL_MSI_MESSAGES]; 716171560Syongari void *rl_intrhand[RL_MSI_MESSAGES]; 71750703Swpaul device_t rl_miibus; 71881713Swpaul bus_dma_tag_t rl_parent_tag; 71981713Swpaul bus_dma_tag_t rl_tag; 720131605Sbms uint8_t rl_type; 72167931Swpaul int rl_eecmd_read; 722159962Swpaul int rl_eewidth; 723131605Sbms uint8_t rl_stats_no_timeout; 72452426Swpaul int rl_txthresh; 72540516Swpaul struct rl_chain_data rl_cdata; 726117388Swpaul struct rl_list_data rl_ldata; 727150720Sjhb struct callout rl_stat_callout; 728164811Sru int rl_watchdog_timer; 72967087Swpaul struct mtx rl_mtx; 730119868Swpaul struct mbuf *rl_head; 731119868Swpaul struct mbuf *rl_tail; 732131605Sbms uint32_t rl_hwrev; 733131605Sbms uint32_t rl_rxlenmask; 734119868Swpaul int rl_testmode; 735168828Syongari int rl_if_flags; 73686822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 73794883Sluigi#ifdef DEVICE_POLLING 73894883Sluigi int rxcycles; 73994883Sluigi#endif 740159962Swpaul 741159962Swpaul struct task rl_txtask; 742159962Swpaul struct task rl_inttask; 743159962Swpaul 744159962Swpaul struct mtx rl_intlock; 745159962Swpaul int rl_txstart; 746159962Swpaul int rl_link; 747171560Syongari int rl_msi; 74840516Swpaul}; 74940516Swpaul 75072200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 75172200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 752122689Ssam#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 75367087Swpaul 75440516Swpaul/* 75540516Swpaul * register space access macros 75640516Swpaul */ 757119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 758119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 75940516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 76041569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 76140516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 76241569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 76340516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 76441569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 76540516Swpaul 76641569Swpaul#define CSR_READ_4(sc, reg) \ 76741569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 76841569Swpaul#define CSR_READ_2(sc, reg) \ 76941569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 77041569Swpaul#define CSR_READ_1(sc, reg) \ 77141569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 77240516Swpaul 773159962Swpaul#define CSR_SETBIT_1(sc, offset, val) \ 774159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val)) 775159962Swpaul 776159962Swpaul#define CSR_CLRBIT_1(sc, offset, val) \ 777159962Swpaul CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val)) 778159962Swpaul 779159962Swpaul#define CSR_SETBIT_2(sc, offset, val) \ 780159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val)) 781159962Swpaul 782159962Swpaul#define CSR_CLRBIT_2(sc, offset, val) \ 783159962Swpaul CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val)) 784159962Swpaul 785159962Swpaul#define CSR_SETBIT_4(sc, offset, val) \ 786159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val)) 787159962Swpaul 788159962Swpaul#define CSR_CLRBIT_4(sc, offset, val) \ 789159962Swpaul CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val)) 790159962Swpaul 79140516Swpaul#define RL_TIMEOUT 1000 79240516Swpaul 79340516Swpaul/* 79440516Swpaul * General constants that are fun to know. 79540516Swpaul * 79640516Swpaul * RealTek PCI vendor ID 79740516Swpaul */ 79840516Swpaul#define RT_VENDORID 0x10EC 79940516Swpaul 80040516Swpaul/* 80140516Swpaul * RealTek chip device IDs. 80240516Swpaul */ 80340516Swpaul#define RT_DEVICEID_8129 0x8129 804159962Swpaul#define RT_DEVICEID_8101E 0x8136 80567771Swpaul#define RT_DEVICEID_8138 0x8138 80640516Swpaul#define RT_DEVICEID_8139 0x8139 807159962Swpaul#define RT_DEVICEID_8169SC 0x8167 808159962Swpaul#define RT_DEVICEID_8168 0x8168 809117388Swpaul#define RT_DEVICEID_8169 0x8169 810118978Swpaul#define RT_DEVICEID_8100 0x8100 81140516Swpaul 812117388Swpaul#define RT_REVID_8139CPLUS 0x20 813117388Swpaul 81440516Swpaul/* 81544238Swpaul * Accton PCI vendor ID 81644238Swpaul */ 81744238Swpaul#define ACCTON_VENDORID 0x1113 81844238Swpaul 81944238Swpaul/* 82041243Swpaul * Accton MPX 5030/5038 device ID. 82141243Swpaul */ 82241243Swpaul#define ACCTON_DEVICEID_5030 0x1211 82341243Swpaul 82441243Swpaul/* 82594400Swpaul * Nortel PCI vendor ID 82694400Swpaul */ 82794400Swpaul#define NORTEL_VENDORID 0x126C 82894400Swpaul 82994400Swpaul/* 83044238Swpaul * Delta Electronics Vendor ID. 83144238Swpaul */ 83244238Swpaul#define DELTA_VENDORID 0x1500 83344238Swpaul 83444238Swpaul/* 83544238Swpaul * Delta device IDs. 83644238Swpaul */ 83744238Swpaul#define DELTA_DEVICEID_8139 0x1360 83844238Swpaul 83944238Swpaul/* 84044238Swpaul * Addtron vendor ID. 84144238Swpaul */ 84244238Swpaul#define ADDTRON_VENDORID 0x4033 84344238Swpaul 84444238Swpaul/* 84544238Swpaul * Addtron device IDs. 84644238Swpaul */ 84744238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 84844238Swpaul 84944238Swpaul/* 85072813Swpaul * D-Link vendor ID. 85172813Swpaul */ 85272813Swpaul#define DLINK_VENDORID 0x1186 85372813Swpaul 85472813Swpaul/* 85572813Swpaul * D-Link DFE-530TX+ device ID 85672813Swpaul */ 85772813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 85872813Swpaul 85972813Swpaul/* 860148722Stobez * D-Link DFE-5280T device ID 861148722Stobez */ 862148722Stobez#define DLINK_DEVICEID_528T 0x4300 863148722Stobez 864148722Stobez/* 86596112Sjhb * D-Link DFE-690TXD device ID 86696112Sjhb */ 86796112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 86896112Sjhb 86996112Sjhb/* 870103020Siwasaki * Corega K.K vendor ID 871103020Siwasaki */ 872103020Siwasaki#define COREGA_VENDORID 0x1259 873103020Siwasaki 874103020Siwasaki/* 875109095Ssanpei * Corega FEther CB-TXD device ID 876103020Siwasaki */ 877151341Sjhb#define COREGA_DEVICEID_FETHERCBTXD 0xa117 878103020Siwasaki 879103020Siwasaki/* 880109095Ssanpei * Corega FEtherII CB-TXD device ID 881109095Ssanpei */ 882151341Sjhb#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 883109095Ssanpei 884111381Sdan/* 885134433Ssanpei * Corega CG-LAPCIGT device ID 886134433Ssanpei */ 887134433Ssanpei#define COREGA_DEVICEID_CGLAPCIGT 0xc107 888134433Ssanpei 889134433Ssanpei/* 890151341Sjhb * Linksys vendor ID 891151341Sjhb */ 892151341Sjhb#define LINKSYS_VENDORID 0x1737 893151341Sjhb 894151341Sjhb/* 895151341Sjhb * Linksys EG1032 device ID 896151341Sjhb */ 897151341Sjhb#define LINKSYS_DEVICEID_EG1032 0x1032 898151341Sjhb 899151341Sjhb/* 900151341Sjhb * Linksys EG1032 rev 3 sub-device ID 901151341Sjhb */ 902151341Sjhb#define LINKSYS_SUBDEVICE_EG1032_REV3 0x0024 903151341Sjhb 904151341Sjhb/* 905111381Sdan * Peppercon vendor ID 906111381Sdan */ 907111381Sdan#define PEPPERCON_VENDORID 0x1743 908109095Ssanpei 909111381Sdan/* 910111381Sdan * Peppercon ROL-F device ID 911111381Sdan */ 912111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 913109095Ssanpei 914109095Ssanpei/* 915112379Ssanpei * Planex Communications, Inc. vendor ID 916112379Ssanpei */ 917117388Swpaul#define PLANEX_VENDORID 0x14ea 918112379Ssanpei 919112379Ssanpei/* 920112379Ssanpei * Planex FNW-3800-TX device ID 921112379Ssanpei */ 922117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 923112379Ssanpei 924112379Ssanpei/* 925117388Swpaul * LevelOne vendor ID 926117388Swpaul */ 927117388Swpaul#define LEVEL1_VENDORID 0x018A 928117388Swpaul 929117388Swpaul/* 930117388Swpaul * LevelOne FPC-0106TX devide ID 931117388Swpaul */ 932117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 933117388Swpaul 934117388Swpaul/* 935117388Swpaul * Compaq vendor ID 936117388Swpaul */ 937117388Swpaul#define CP_VENDORID 0x021B 938117388Swpaul 939117388Swpaul/* 940117388Swpaul * Edimax vendor ID 941117388Swpaul */ 942117388Swpaul#define EDIMAX_VENDORID 0x13D1 943117388Swpaul 944117388Swpaul/* 945117388Swpaul * Edimax EP-4103DL cardbus device ID 946117388Swpaul */ 947117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 948117388Swpaul 949160883Swpaul/* US Robotics vendor ID */ 950160883Swpaul 951160883Swpaul#define USR_VENDORID 0x16EC 952160883Swpaul 953160883Swpaul/* US Robotics 997902 device ID */ 954160883Swpaul 955160883Swpaul#define USR_DEVICEID_997902 0x0116 956160883Swpaul 957117388Swpaul/* 95840516Swpaul * PCI low memory base and low I/O base register, and 95950703Swpaul * other PCI registers. 96040516Swpaul */ 96140516Swpaul 96240516Swpaul#define RL_PCI_VENDOR_ID 0x00 96340516Swpaul#define RL_PCI_DEVICE_ID 0x02 96440516Swpaul#define RL_PCI_COMMAND 0x04 96540516Swpaul#define RL_PCI_STATUS 0x06 96640516Swpaul#define RL_PCI_CLASSCODE 0x09 96740516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 96840516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 96940516Swpaul#define RL_PCI_LOIO 0x10 97040516Swpaul#define RL_PCI_LOMEM 0x14 97140516Swpaul#define RL_PCI_BIOSROM 0x30 97240516Swpaul#define RL_PCI_INTLINE 0x3C 97340516Swpaul#define RL_PCI_INTPIN 0x3D 97440516Swpaul#define RL_PCI_MINGNT 0x3E 97540516Swpaul#define RL_PCI_MINLAT 0x0F 97640516Swpaul#define RL_PCI_RESETOPT 0x48 97740516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 97840516Swpaul 97950097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 98050097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 98150097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 98250097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 98340516Swpaul 98440516Swpaul#define RL_PSTATE_MASK 0x0003 98540516Swpaul#define RL_PSTATE_D0 0x0000 98640516Swpaul#define RL_PSTATE_D1 0x0002 98740516Swpaul#define RL_PSTATE_D2 0x0002 98840516Swpaul#define RL_PSTATE_D3 0x0003 98940516Swpaul#define RL_PME_EN 0x0010 99040516Swpaul#define RL_PME_STATUS 0x8000 991