if_rlreg.h revision 120043
140516Swpaul/* 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 120043 2003-09-13 23:51:35Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 79120043Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113120043Swpaul#define RL_CFG2 0x0053 114117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 115117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 116117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 117117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 119117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 12040516Swpaul 12140516Swpaul/* 122117388Swpaul * Registers specific to the 8169 gigE chip 123117388Swpaul */ 124118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 125117388Swpaul#define RL_PHYAR 0x0060 126117388Swpaul#define RL_TBICSR 0x0064 127117388Swpaul#define RL_TBI_ANAR 0x0068 128117388Swpaul#define RL_TBI_LPAR 0x006A 129117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 130117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 131117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 132117388Swpaul 133117388Swpaul/* 13440516Swpaul * TX config register bits 13540516Swpaul */ 13640516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13745633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13840516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13945633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 140119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14145633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 142117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14340516Swpaul 144119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 145119868Swpaul#define RL_LOOPTEST_ON 0x00020000 146119981Swpaul#define RL_LOOPTEST_ON_CPLUS 0x00060000 147119868Swpaul 148118586Swpaul#define RL_HWREV_8169 0x00000000 149119949Swpaul#define RL_HWREV_8169S 0x04000000 150119949Swpaul#define RL_HWREV_8110S 0x00800000 151117388Swpaul#define RL_HWREV_8139 0x60000000 152117388Swpaul#define RL_HWREV_8139A 0x70000000 153117388Swpaul#define RL_HWREV_8139AG 0x70800000 154117388Swpaul#define RL_HWREV_8139B 0x78000000 155117388Swpaul#define RL_HWREV_8130 0x7C000000 156117388Swpaul#define RL_HWREV_8139C 0x74000000 157117388Swpaul#define RL_HWREV_8139D 0x74400000 158117388Swpaul#define RL_HWREV_8139CPLUS 0x74800000 159118586Swpaul#define RL_HWREV_8101 0x74c00000 160118586Swpaul#define RL_HWREV_8100 0x78800000 161117388Swpaul 16245633Swpaul#define RL_TXDMA_16BYTES 0x00000000 16345633Swpaul#define RL_TXDMA_32BYTES 0x00000100 16445633Swpaul#define RL_TXDMA_64BYTES 0x00000200 16545633Swpaul#define RL_TXDMA_128BYTES 0x00000300 16645633Swpaul#define RL_TXDMA_256BYTES 0x00000400 16745633Swpaul#define RL_TXDMA_512BYTES 0x00000500 16845633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 16945633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 17045633Swpaul 17140516Swpaul/* 17240516Swpaul * Transmit descriptor status register bits. 17340516Swpaul */ 17440516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 17540516Swpaul#define RL_TXSTAT_OWN 0x00002000 17640516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 17740516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 17840516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 17940516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 18040516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 18140516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 18240516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 18340516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 18440516Swpaul 18540516Swpaul/* 18640516Swpaul * Interrupt status register bits. 18740516Swpaul */ 18840516Swpaul#define RL_ISR_RX_OK 0x0001 18940516Swpaul#define RL_ISR_RX_ERR 0x0002 19040516Swpaul#define RL_ISR_TX_OK 0x0004 19140516Swpaul#define RL_ISR_TX_ERR 0x0008 19240516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 19340516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 194119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 19540516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 196117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 197117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 198117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 19940516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 200117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 20140516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 20240516Swpaul 20340516Swpaul#define RL_INTRS \ 20440516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 20540516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 20640516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 20740516Swpaul 208117388Swpaul#define RL_INTRS_CPLUS \ 209119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 210117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 211117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 212117388Swpaul 21340516Swpaul/* 21440516Swpaul * Media status register. (8139 only) 21540516Swpaul */ 21640516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 21740516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 21840516Swpaul#define RL_MEDIASTAT_LINK 0x04 21940516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 22040516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 22140516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 22240516Swpaul 22340516Swpaul/* 22440516Swpaul * Receive config register. 22540516Swpaul */ 22640516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 22740516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 22840516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 22940516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 23040516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 23140516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 23240516Swpaul#define RL_RXCFG_WRAP 0x00000080 23345633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 23445633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 23545633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 23645633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 23740516Swpaul 23845633Swpaul#define RL_RXDMA_16BYTES 0x00000000 23945633Swpaul#define RL_RXDMA_32BYTES 0x00000100 24045633Swpaul#define RL_RXDMA_64BYTES 0x00000200 24145633Swpaul#define RL_RXDMA_128BYTES 0x00000300 24245633Swpaul#define RL_RXDMA_256BYTES 0x00000400 24345633Swpaul#define RL_RXDMA_512BYTES 0x00000500 24445633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 24545633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 24645633Swpaul 24740516Swpaul#define RL_RXBUF_8 0x00000000 24840516Swpaul#define RL_RXBUF_16 0x00000800 24940516Swpaul#define RL_RXBUF_32 0x00001000 25045633Swpaul#define RL_RXBUF_64 0x00001800 25140516Swpaul 25245633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 25345633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 25445633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 25545633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 25645633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 25745633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 25845633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 25945633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 26045633Swpaul 26140516Swpaul/* 26240516Swpaul * Bits in RX status header (included with RX'ed packet 26340516Swpaul * in ring buffer). 26440516Swpaul */ 26540516Swpaul#define RL_RXSTAT_RXOK 0x00000001 26640516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 26740516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 26840516Swpaul#define RL_RXSTAT_GIANT 0x00000008 26940516Swpaul#define RL_RXSTAT_RUNT 0x00000010 27040516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 27140516Swpaul#define RL_RXSTAT_BROAD 0x00002000 27240516Swpaul#define RL_RXSTAT_INDIV 0x00004000 27340516Swpaul#define RL_RXSTAT_MULTI 0x00008000 27440516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 27540516Swpaul 27640516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 27740516Swpaul/* 27840516Swpaul * Command register. 27940516Swpaul */ 28040516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 28140516Swpaul#define RL_CMD_TX_ENB 0x0004 28240516Swpaul#define RL_CMD_RX_ENB 0x0008 28340516Swpaul#define RL_CMD_RESET 0x0010 28440516Swpaul 28540516Swpaul/* 28640516Swpaul * EEPROM control register 28740516Swpaul */ 28840516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 28940516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 29040516Swpaul#define RL_EE_CLK 0x04 /* clock */ 29140516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 29240516Swpaul#define RL_EE_MODE (0x40|0x80) 29340516Swpaul 29440516Swpaul#define RL_EEMODE_OFF 0x00 29540516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 29640516Swpaul#define RL_EEMODE_PROGRAM 0x80 29740516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 29840516Swpaul 29940516Swpaul/* 9346 EEPROM commands */ 30040516Swpaul#define RL_EECMD_WRITE 0x140 30167931Swpaul#define RL_EECMD_READ_6BIT 0x180 30267931Swpaul#define RL_EECMD_READ_8BIT 0x600 30340516Swpaul#define RL_EECMD_ERASE 0x1c0 30440516Swpaul 30540516Swpaul#define RL_EE_ID 0x00 30640516Swpaul#define RL_EE_PCI_VID 0x01 30740516Swpaul#define RL_EE_PCI_DID 0x02 30840516Swpaul/* Location of station address inside EEPROM */ 30940516Swpaul#define RL_EE_EADDR 0x07 31040516Swpaul 31140516Swpaul/* 31240516Swpaul * MII register (8129 only) 31340516Swpaul */ 31440516Swpaul#define RL_MII_CLK 0x01 31540516Swpaul#define RL_MII_DATAIN 0x02 31640516Swpaul#define RL_MII_DATAOUT 0x04 31740516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 31840516Swpaul 31940516Swpaul/* 32040516Swpaul * Config 0 register 32140516Swpaul */ 32240516Swpaul#define RL_CFG0_ROM0 0x01 32340516Swpaul#define RL_CFG0_ROM1 0x02 32440516Swpaul#define RL_CFG0_ROM2 0x04 32540516Swpaul#define RL_CFG0_PL0 0x08 32640516Swpaul#define RL_CFG0_PL1 0x10 32740516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 32840516Swpaul#define RL_CFG0_PCS 0x40 32940516Swpaul#define RL_CFG0_SCR 0x80 33040516Swpaul 33140516Swpaul/* 33240516Swpaul * Config 1 register 33340516Swpaul */ 33440516Swpaul#define RL_CFG1_PWRDWN 0x01 33540516Swpaul#define RL_CFG1_SLEEP 0x02 33640516Swpaul#define RL_CFG1_IOMAP 0x04 33740516Swpaul#define RL_CFG1_MEMMAP 0x08 33840516Swpaul#define RL_CFG1_RSVD 0x10 33940516Swpaul#define RL_CFG1_DRVLOAD 0x20 34040516Swpaul#define RL_CFG1_LED0 0x40 34140516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 34240516Swpaul#define RL_CFG1_LED1 0x80 34340516Swpaul 34440516Swpaul/* 345117388Swpaul * 8139C+ register definitions 346117388Swpaul */ 347117388Swpaul 348117388Swpaul/* RL_DUMPSTATS_LO register */ 349117388Swpaul 350117388Swpaul#define RL_DUMPSTATS_START 0x00000008 351117388Swpaul 352117388Swpaul/* Transmit start register */ 353117388Swpaul 354117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 355117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 356117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 357117388Swpaul 358120043Swpaul/* 359120043Swpaul * Config 2 register, 8139C+/8169/8169S/8110S only 360120043Swpaul */ 361120043Swpaul#define RL_CFG2_BUSFREQ 0x07 362120043Swpaul#define RL_CFG2_BUSWIDTH 0x08 363120043Swpaul#define RL_CFG2_AUXPWRSTS 0x10 364120043Swpaul 365120043Swpaul#define RL_BUSFREQ_33MHZ 0x00 366120043Swpaul#define RL_BUSFREQ_66MHZ 0x01 367120043Swpaul 368120043Swpaul#define RL_BUSWIDTH_32BITS 0x00 369120043Swpaul#define RL_BUSWIDTH_64BITS 0x08 370120043Swpaul 371117388Swpaul/* C+ mode command register */ 372117388Swpaul 373117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 374117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 375117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 376117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 377117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 378117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 379117388Swpaul 380117388Swpaul/* C+ early transmit threshold */ 381117388Swpaul 382117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 383117388Swpaul 384117388Swpaul/* 385117388Swpaul * Gigabit PHY access register (8169 only) 386117388Swpaul */ 387117388Swpaul 388117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 389117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 390117388Swpaul#define RL_PHYAR_BUSY 0x80000000 391117388Swpaul 392117388Swpaul/* 393117388Swpaul * Gigabit media status (8169 only) 394117388Swpaul */ 395117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 396117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 397117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 398117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 399119976Swpaul#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */ 400117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 401117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 402117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 403117388Swpaul 404117388Swpaul/* 40540516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 40640516Swpaul * Instead, there are only four register sets, each or which represents 40740516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 40840516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 40940516Swpaul * the registers so the chip knows where they are. 41040516Swpaul * 41140516Swpaul * We can sort of kludge together the same kind of buffer management 41240516Swpaul * used in previous drivers, but we have to do buffer copies almost all 41340516Swpaul * the time, so it doesn't really buy us much. 41440516Swpaul * 41540516Swpaul * For reception, there's just one large buffer where the chip stores 41640516Swpaul * all received packets. 41740516Swpaul */ 41840516Swpaul 41940516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 42040516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 42140516Swpaul#define RL_TX_LIST_CNT 4 42240516Swpaul#define RL_MIN_FRAMELEN 60 42352426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 42452426Swpaul#define RL_TX_THRESH_INIT 96 425119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 426119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 42750703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 42840516Swpaul 42945633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 43045633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 43140516Swpaul 43248028Swpaul#define RL_ETHER_ALIGN 2 43348028Swpaul 43440516Swpaulstruct rl_chain_data { 43540516Swpaul u_int16_t cur_rx; 43640516Swpaul caddr_t rl_rx_buf; 43748028Swpaul caddr_t rl_rx_buf_ptr; 43881713Swpaul bus_dmamap_t rl_rx_dmamap; 43940516Swpaul 44045633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 44181713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 44245633Swpaul u_int8_t last_tx; 44345633Swpaul u_int8_t cur_tx; 44440516Swpaul}; 44540516Swpaul 44645633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 44745633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 44845633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 44945633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 45081713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 45145633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 45245633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 45345633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 45481713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 45545633Swpaul 45640516Swpaulstruct rl_type { 45740516Swpaul u_int16_t rl_vid; 45840516Swpaul u_int16_t rl_did; 459117388Swpaul int rl_basetype; 46040516Swpaul char *rl_name; 46140516Swpaul}; 46240516Swpaul 463117388Swpaulstruct rl_hwrev { 464117388Swpaul u_int32_t rl_rev; 465117388Swpaul int rl_type; 466117388Swpaul char *rl_desc; 467117388Swpaul}; 468117388Swpaul 46940516Swpaulstruct rl_mii_frame { 47040516Swpaul u_int8_t mii_stdelim; 47140516Swpaul u_int8_t mii_opcode; 47240516Swpaul u_int8_t mii_phyaddr; 47340516Swpaul u_int8_t mii_regaddr; 47440516Swpaul u_int8_t mii_turnaround; 47540516Swpaul u_int16_t mii_data; 47640516Swpaul}; 47740516Swpaul 47840516Swpaul/* 47940516Swpaul * MII constants 48040516Swpaul */ 48140516Swpaul#define RL_MII_STARTDELIM 0x01 48240516Swpaul#define RL_MII_READOP 0x02 48340516Swpaul#define RL_MII_WRITEOP 0x01 48440516Swpaul#define RL_MII_TURNAROUND 0x02 48540516Swpaul 48640516Swpaul#define RL_8129 1 48740516Swpaul#define RL_8139 2 488117388Swpaul#define RL_8139CPLUS 3 489117388Swpaul#define RL_8169 4 49040516Swpaul 491117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 492117388Swpaul (x)->rl_type == RL_8169) 493117388Swpaul 494117388Swpaul/* 495117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 496117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 497117388Swpaul * must be allocated in contiguous blocks that are aligned on a 498117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 499117388Swpaul */ 500117388Swpaul 501117388Swpaul/* 502117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 503117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 504117388Swpaul * the checksum offload bits are disabled. The structure layout is 505117388Swpaul * the same for RX and TX descriptors 506117388Swpaul */ 507117388Swpaul 508117388Swpaulstruct rl_desc { 509117388Swpaul u_int32_t rl_cmdstat; 510117388Swpaul u_int32_t rl_vlanctl; 511117388Swpaul u_int32_t rl_bufaddr_lo; 512117388Swpaul u_int32_t rl_bufaddr_hi; 513117388Swpaul}; 514117388Swpaul 515117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 516117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 517117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 518117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 519117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 520117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 521117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 522117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 523117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 524117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 525117388Swpaul 526117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 527117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 528117388Swpaul 529117388Swpaul/* 530117388Swpaul * Error bits are valid only on the last descriptor of a frame 531117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 532117388Swpaul */ 533117388Swpaul 534117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 535117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 536117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 537117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 538117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 539117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 540117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 541117388Swpaul 542117388Swpaul/* 543117388Swpaul * RX descriptor cmd/vlan definitions 544117388Swpaul */ 545117388Swpaul 546117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 547117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 548119981Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 549117388Swpaul 550117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 551117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 552117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 553117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 554117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 555117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 556117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 557117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 558117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 559117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 560117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 561117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 562117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 563117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 564117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 565117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 566117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 567117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 568119981Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 569119981Swpaul#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 570117388Swpaul 571117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 572117388Swpaul (rl_vlandata valid)*/ 573117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 574117388Swpaul 575117388Swpaul#define RL_PROTOID_NONIP 0x00000000 576117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 577117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 578117388Swpaul#define RL_PROTOID_IP 0x00030000 579117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 580117388Swpaul RL_PROTOID_TCPIP) 581117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 582117388Swpaul RL_PROTOID_UDPIP) 583117388Swpaul 584117388Swpaul/* 585117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 586117388Swpaul */ 587117388Swpaulstruct rl_stats { 588117388Swpaul u_int32_t rl_tx_pkts_lo; 589117388Swpaul u_int32_t rl_tx_pkts_hi; 590117388Swpaul u_int32_t rl_tx_errs_lo; 591117388Swpaul u_int32_t rl_tx_errs_hi; 592117388Swpaul u_int32_t rl_tx_errs; 593117388Swpaul u_int16_t rl_missed_pkts; 594117388Swpaul u_int16_t rl_rx_framealign_errs; 595117388Swpaul u_int32_t rl_tx_onecoll; 596117388Swpaul u_int32_t rl_tx_multicolls; 597117388Swpaul u_int32_t rl_rx_ucasts_hi; 598117388Swpaul u_int32_t rl_rx_ucasts_lo; 599117388Swpaul u_int32_t rl_rx_bcasts_lo; 600117388Swpaul u_int32_t rl_rx_bcasts_hi; 601117388Swpaul u_int32_t rl_rx_mcasts; 602117388Swpaul u_int16_t rl_tx_aborts; 603117388Swpaul u_int16_t rl_rx_underruns; 604117388Swpaul}; 605117388Swpaul 606117388Swpaul#define RL_RX_DESC_CNT 64 607117388Swpaul#define RL_TX_DESC_CNT 64 608117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 609117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 610117388Swpaul#define RL_RING_ALIGN 256 611117388Swpaul#define RL_IFQ_MAXLEN 512 612117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 613117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 614119981Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask) 615119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 616117388Swpaul 617118712Swpaul#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 618118712Swpaul#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 619118712Swpaul 620119868Swpaul#define RL_JUMBO_FRAMELEN 9018 621119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 622119868Swpaul#define RL_JSLOTS 128 623119868Swpaul 624119868Swpaul#define RL_JRAWLEN (RL_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 625119868Swpaul#define RL_JLEN (RL_JRAWLEN + (sizeof(u_int64_t) - \ 626119868Swpaul (RL_JRAWLEN % sizeof(u_int64_t)))) 627119868Swpaul#define RL_JPAGESZ PAGE_SIZE 628119868Swpaul#define RL_RESID (RL_JPAGESZ - (RL_JLEN * RL_JSLOTS) % RL_JPAGESZ) 629119868Swpaul#define RL_JMEM ((RL_JLEN * RL_JSLOTS) + RL_RESID) 630119868Swpaul 631117388Swpaulstruct rl_softc; 632117388Swpaul 633117388Swpaulstruct rl_dmaload_arg { 634117388Swpaul struct rl_softc *sc; 635117388Swpaul int rl_idx; 636117388Swpaul int rl_maxsegs; 637118889Swpaul u_int32_t rl_flags; 638117388Swpaul struct rl_desc *rl_ring; 639117388Swpaul}; 640117388Swpaul 641117388Swpaulstruct rl_list_data { 642117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 643117388Swpaul struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 644117388Swpaul int rl_tx_prodidx; 645117388Swpaul int rl_rx_prodidx; 646117388Swpaul int rl_tx_considx; 647117388Swpaul int rl_tx_free; 648117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 649117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 650117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 651117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 652117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 653117388Swpaul struct rl_stats *rl_stats; 654118712Swpaul bus_addr_t rl_stats_addr; 655117388Swpaul bus_dma_tag_t rl_rx_list_tag; 656117388Swpaul bus_dmamap_t rl_rx_list_map; 657117388Swpaul struct rl_desc *rl_rx_list; 658118712Swpaul bus_addr_t rl_rx_list_addr; 659117388Swpaul bus_dma_tag_t rl_tx_list_tag; 660117388Swpaul bus_dmamap_t rl_tx_list_map; 661117388Swpaul struct rl_desc *rl_tx_list; 662118712Swpaul bus_addr_t rl_tx_list_addr; 663117388Swpaul}; 664117388Swpaul 66540516Swpaulstruct rl_softc { 66640516Swpaul struct arpcom arpcom; /* interface info */ 66741569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 66841569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 66950703Swpaul struct resource *rl_res; 67050703Swpaul struct resource *rl_irq; 67150703Swpaul void *rl_intrhand; 67250703Swpaul device_t rl_miibus; 67381713Swpaul bus_dma_tag_t rl_parent_tag; 67481713Swpaul bus_dma_tag_t rl_tag; 67540516Swpaul u_int8_t rl_unit; /* interface number */ 67640516Swpaul u_int8_t rl_type; 67767931Swpaul int rl_eecmd_read; 67840516Swpaul u_int8_t rl_stats_no_timeout; 67952426Swpaul int rl_txthresh; 68040516Swpaul struct rl_chain_data rl_cdata; 681117388Swpaul struct rl_list_data rl_ldata; 68250703Swpaul struct callout_handle rl_stat_ch; 68367087Swpaul struct mtx rl_mtx; 684119868Swpaul struct mbuf *rl_head; 685119868Swpaul struct mbuf *rl_tail; 686119868Swpaul u_int32_t rl_hwrev; 687119981Swpaul u_int32_t rl_rxlenmask; 688119868Swpaul int rl_testmode; 68986822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 69094883Sluigi#ifdef DEVICE_POLLING 69194883Sluigi int rxcycles; 69294883Sluigi#endif 69386822Siwasaki 69486822Siwasaki u_int32_t saved_maps[5]; /* pci data */ 69586822Siwasaki u_int32_t saved_biosaddr; 69686822Siwasaki u_int8_t saved_intline; 69786822Siwasaki u_int8_t saved_cachelnsz; 69886822Siwasaki u_int8_t saved_lattimer; 69940516Swpaul}; 70040516Swpaul 70172200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 70272200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 70367087Swpaul 70440516Swpaul/* 70540516Swpaul * register space access macros 70640516Swpaul */ 707119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 708119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 70940516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 71041569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 71140516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 71241569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 71340516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 71441569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 71540516Swpaul 71641569Swpaul#define CSR_READ_4(sc, reg) \ 71741569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 71841569Swpaul#define CSR_READ_2(sc, reg) \ 71941569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 72041569Swpaul#define CSR_READ_1(sc, reg) \ 72141569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 72240516Swpaul 72340516Swpaul#define RL_TIMEOUT 1000 72440516Swpaul 72540516Swpaul/* 72640516Swpaul * General constants that are fun to know. 72740516Swpaul * 72840516Swpaul * RealTek PCI vendor ID 72940516Swpaul */ 73040516Swpaul#define RT_VENDORID 0x10EC 73140516Swpaul 73240516Swpaul/* 73340516Swpaul * RealTek chip device IDs. 73440516Swpaul */ 73540516Swpaul#define RT_DEVICEID_8129 0x8129 73667771Swpaul#define RT_DEVICEID_8138 0x8138 73740516Swpaul#define RT_DEVICEID_8139 0x8139 738117388Swpaul#define RT_DEVICEID_8169 0x8169 739118978Swpaul#define RT_DEVICEID_8100 0x8100 74040516Swpaul 741117388Swpaul#define RT_REVID_8139CPLUS 0x20 742117388Swpaul 74340516Swpaul/* 74444238Swpaul * Accton PCI vendor ID 74544238Swpaul */ 74644238Swpaul#define ACCTON_VENDORID 0x1113 74744238Swpaul 74844238Swpaul/* 74941243Swpaul * Accton MPX 5030/5038 device ID. 75041243Swpaul */ 75141243Swpaul#define ACCTON_DEVICEID_5030 0x1211 75241243Swpaul 75341243Swpaul/* 75494400Swpaul * Nortel PCI vendor ID 75594400Swpaul */ 75694400Swpaul#define NORTEL_VENDORID 0x126C 75794400Swpaul 75894400Swpaul/* 75944238Swpaul * Delta Electronics Vendor ID. 76044238Swpaul */ 76144238Swpaul#define DELTA_VENDORID 0x1500 76244238Swpaul 76344238Swpaul/* 76444238Swpaul * Delta device IDs. 76544238Swpaul */ 76644238Swpaul#define DELTA_DEVICEID_8139 0x1360 76744238Swpaul 76844238Swpaul/* 76944238Swpaul * Addtron vendor ID. 77044238Swpaul */ 77144238Swpaul#define ADDTRON_VENDORID 0x4033 77244238Swpaul 77344238Swpaul/* 77444238Swpaul * Addtron device IDs. 77544238Swpaul */ 77644238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 77744238Swpaul 77844238Swpaul/* 77972813Swpaul * D-Link vendor ID. 78072813Swpaul */ 78172813Swpaul#define DLINK_VENDORID 0x1186 78272813Swpaul 78372813Swpaul/* 78472813Swpaul * D-Link DFE-530TX+ device ID 78572813Swpaul */ 78672813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 78772813Swpaul 78872813Swpaul/* 78996112Sjhb * D-Link DFE-690TXD device ID 79096112Sjhb */ 79196112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 79296112Sjhb 79396112Sjhb/* 794103020Siwasaki * Corega K.K vendor ID 795103020Siwasaki */ 796103020Siwasaki#define COREGA_VENDORID 0x1259 797103020Siwasaki 798103020Siwasaki/* 799109095Ssanpei * Corega FEther CB-TXD device ID 800103020Siwasaki */ 801109095Ssanpei#define COREGA_DEVICEID_FETHERCBTXD 0xa117 802103020Siwasaki 803103020Siwasaki/* 804109095Ssanpei * Corega FEtherII CB-TXD device ID 805109095Ssanpei */ 806109095Ssanpei#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 807109095Ssanpei 808111381Sdan/* 809111381Sdan * Peppercon vendor ID 810111381Sdan */ 811111381Sdan#define PEPPERCON_VENDORID 0x1743 812109095Ssanpei 813111381Sdan/* 814111381Sdan * Peppercon ROL-F device ID 815111381Sdan */ 816111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 817109095Ssanpei 818109095Ssanpei/* 819112379Ssanpei * Planex Communications, Inc. vendor ID 820112379Ssanpei */ 821117388Swpaul#define PLANEX_VENDORID 0x14ea 822112379Ssanpei 823112379Ssanpei/* 824112379Ssanpei * Planex FNW-3800-TX device ID 825112379Ssanpei */ 826117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 827112379Ssanpei 828112379Ssanpei/* 829117388Swpaul * LevelOne vendor ID 830117388Swpaul */ 831117388Swpaul#define LEVEL1_VENDORID 0x018A 832117388Swpaul 833117388Swpaul/* 834117388Swpaul * LevelOne FPC-0106TX devide ID 835117388Swpaul */ 836117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 837117388Swpaul 838117388Swpaul/* 839117388Swpaul * Compaq vendor ID 840117388Swpaul */ 841117388Swpaul#define CP_VENDORID 0x021B 842117388Swpaul 843117388Swpaul/* 844117388Swpaul * Edimax vendor ID 845117388Swpaul */ 846117388Swpaul#define EDIMAX_VENDORID 0x13D1 847117388Swpaul 848117388Swpaul/* 849117388Swpaul * Edimax EP-4103DL cardbus device ID 850117388Swpaul */ 851117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 852117388Swpaul 853117388Swpaul/* 85440516Swpaul * PCI low memory base and low I/O base register, and 85550703Swpaul * other PCI registers. 85640516Swpaul */ 85740516Swpaul 85840516Swpaul#define RL_PCI_VENDOR_ID 0x00 85940516Swpaul#define RL_PCI_DEVICE_ID 0x02 86040516Swpaul#define RL_PCI_COMMAND 0x04 86140516Swpaul#define RL_PCI_STATUS 0x06 86240516Swpaul#define RL_PCI_CLASSCODE 0x09 86340516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 86440516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 86540516Swpaul#define RL_PCI_LOIO 0x10 86640516Swpaul#define RL_PCI_LOMEM 0x14 86740516Swpaul#define RL_PCI_BIOSROM 0x30 86840516Swpaul#define RL_PCI_INTLINE 0x3C 86940516Swpaul#define RL_PCI_INTPIN 0x3D 87040516Swpaul#define RL_PCI_MINGNT 0x3E 87140516Swpaul#define RL_PCI_MINLAT 0x0F 87240516Swpaul#define RL_PCI_RESETOPT 0x48 87340516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 87440516Swpaul 87550097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 87650097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 87750097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 87850097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 87940516Swpaul 88040516Swpaul#define RL_PSTATE_MASK 0x0003 88140516Swpaul#define RL_PSTATE_D0 0x0000 88240516Swpaul#define RL_PSTATE_D1 0x0002 88340516Swpaul#define RL_PSTATE_D2 0x0002 88440516Swpaul#define RL_PSTATE_D3 0x0003 88540516Swpaul#define RL_PME_EN 0x0010 88640516Swpaul#define RL_PME_STATUS 0x8000 887