if_rlreg.h revision 119868
140516Swpaul/* 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 119868 2003-09-08 02:11:25Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 7940516Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 115117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 11940516Swpaul 12040516Swpaul/* 121117388Swpaul * Registers specific to the 8169 gigE chip 122117388Swpaul */ 123118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 124117388Swpaul#define RL_PHYAR 0x0060 125117388Swpaul#define RL_TBICSR 0x0064 126117388Swpaul#define RL_TBI_ANAR 0x0068 127117388Swpaul#define RL_TBI_LPAR 0x006A 128117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 129117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 130117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 131117388Swpaul 132117388Swpaul/* 13340516Swpaul * TX config register bits 13440516Swpaul */ 13540516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13645633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13740516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13845633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 139119868Swpaul#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */ 14045633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 141117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14240516Swpaul 143119868Swpaul#define RL_LOOPTEST_OFF 0x00000000 144119868Swpaul#define RL_LOOPTEST_ON 0x00020000 145119868Swpaul 146118586Swpaul#define RL_HWREV_8169 0x00000000 147118586Swpaul#define RL_HWREV_8110 0x00800000 148117388Swpaul#define RL_HWREV_8139 0x60000000 149117388Swpaul#define RL_HWREV_8139A 0x70000000 150117388Swpaul#define RL_HWREV_8139AG 0x70800000 151117388Swpaul#define RL_HWREV_8139B 0x78000000 152117388Swpaul#define RL_HWREV_8130 0x7C000000 153117388Swpaul#define RL_HWREV_8139C 0x74000000 154117388Swpaul#define RL_HWREV_8139D 0x74400000 155117388Swpaul#define RL_HWREV_8139CPLUS 0x74800000 156118586Swpaul#define RL_HWREV_8101 0x74c00000 157118586Swpaul#define RL_HWREV_8100 0x78800000 158117388Swpaul 15945633Swpaul#define RL_TXDMA_16BYTES 0x00000000 16045633Swpaul#define RL_TXDMA_32BYTES 0x00000100 16145633Swpaul#define RL_TXDMA_64BYTES 0x00000200 16245633Swpaul#define RL_TXDMA_128BYTES 0x00000300 16345633Swpaul#define RL_TXDMA_256BYTES 0x00000400 16445633Swpaul#define RL_TXDMA_512BYTES 0x00000500 16545633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 16645633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 16745633Swpaul 16840516Swpaul/* 16940516Swpaul * Transmit descriptor status register bits. 17040516Swpaul */ 17140516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 17240516Swpaul#define RL_TXSTAT_OWN 0x00002000 17340516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 17440516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 17540516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 17640516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 17740516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 17840516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 17940516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 18040516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 18140516Swpaul 18240516Swpaul/* 18340516Swpaul * Interrupt status register bits. 18440516Swpaul */ 18540516Swpaul#define RL_ISR_RX_OK 0x0001 18640516Swpaul#define RL_ISR_RX_ERR 0x0002 18740516Swpaul#define RL_ISR_TX_OK 0x0004 18840516Swpaul#define RL_ISR_TX_ERR 0x0008 18940516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 19040516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 191119868Swpaul#define RL_ISR_LINKCHG 0x0020 /* 8169 only */ 19240516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 193117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 194117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 195117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 19640516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 197117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 19840516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 19940516Swpaul 20040516Swpaul#define RL_INTRS \ 20140516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 20240516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 20340516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 20440516Swpaul 205117388Swpaul#define RL_INTRS_CPLUS \ 206119868Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 207117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 208117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 209117388Swpaul 21040516Swpaul/* 21140516Swpaul * Media status register. (8139 only) 21240516Swpaul */ 21340516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 21440516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 21540516Swpaul#define RL_MEDIASTAT_LINK 0x04 21640516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 21740516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 21840516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 21940516Swpaul 22040516Swpaul/* 22140516Swpaul * Receive config register. 22240516Swpaul */ 22340516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 22440516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 22540516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 22640516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 22740516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 22840516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 22940516Swpaul#define RL_RXCFG_WRAP 0x00000080 23045633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 23145633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 23245633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 23345633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 23440516Swpaul 23545633Swpaul#define RL_RXDMA_16BYTES 0x00000000 23645633Swpaul#define RL_RXDMA_32BYTES 0x00000100 23745633Swpaul#define RL_RXDMA_64BYTES 0x00000200 23845633Swpaul#define RL_RXDMA_128BYTES 0x00000300 23945633Swpaul#define RL_RXDMA_256BYTES 0x00000400 24045633Swpaul#define RL_RXDMA_512BYTES 0x00000500 24145633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 24245633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 24345633Swpaul 24440516Swpaul#define RL_RXBUF_8 0x00000000 24540516Swpaul#define RL_RXBUF_16 0x00000800 24640516Swpaul#define RL_RXBUF_32 0x00001000 24745633Swpaul#define RL_RXBUF_64 0x00001800 24840516Swpaul 24945633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 25045633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 25145633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 25245633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 25345633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 25445633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 25545633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 25645633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 25745633Swpaul 25840516Swpaul/* 25940516Swpaul * Bits in RX status header (included with RX'ed packet 26040516Swpaul * in ring buffer). 26140516Swpaul */ 26240516Swpaul#define RL_RXSTAT_RXOK 0x00000001 26340516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 26440516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 26540516Swpaul#define RL_RXSTAT_GIANT 0x00000008 26640516Swpaul#define RL_RXSTAT_RUNT 0x00000010 26740516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 26840516Swpaul#define RL_RXSTAT_BROAD 0x00002000 26940516Swpaul#define RL_RXSTAT_INDIV 0x00004000 27040516Swpaul#define RL_RXSTAT_MULTI 0x00008000 27140516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 27240516Swpaul 27340516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 27440516Swpaul/* 27540516Swpaul * Command register. 27640516Swpaul */ 27740516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 27840516Swpaul#define RL_CMD_TX_ENB 0x0004 27940516Swpaul#define RL_CMD_RX_ENB 0x0008 28040516Swpaul#define RL_CMD_RESET 0x0010 28140516Swpaul 28240516Swpaul/* 28340516Swpaul * EEPROM control register 28440516Swpaul */ 28540516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 28640516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 28740516Swpaul#define RL_EE_CLK 0x04 /* clock */ 28840516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 28940516Swpaul#define RL_EE_MODE (0x40|0x80) 29040516Swpaul 29140516Swpaul#define RL_EEMODE_OFF 0x00 29240516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 29340516Swpaul#define RL_EEMODE_PROGRAM 0x80 29440516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 29540516Swpaul 29640516Swpaul/* 9346 EEPROM commands */ 29740516Swpaul#define RL_EECMD_WRITE 0x140 29867931Swpaul#define RL_EECMD_READ_6BIT 0x180 29967931Swpaul#define RL_EECMD_READ_8BIT 0x600 30040516Swpaul#define RL_EECMD_ERASE 0x1c0 30140516Swpaul 30240516Swpaul#define RL_EE_ID 0x00 30340516Swpaul#define RL_EE_PCI_VID 0x01 30440516Swpaul#define RL_EE_PCI_DID 0x02 30540516Swpaul/* Location of station address inside EEPROM */ 30640516Swpaul#define RL_EE_EADDR 0x07 30740516Swpaul 30840516Swpaul/* 30940516Swpaul * MII register (8129 only) 31040516Swpaul */ 31140516Swpaul#define RL_MII_CLK 0x01 31240516Swpaul#define RL_MII_DATAIN 0x02 31340516Swpaul#define RL_MII_DATAOUT 0x04 31440516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 31540516Swpaul 31640516Swpaul/* 31740516Swpaul * Config 0 register 31840516Swpaul */ 31940516Swpaul#define RL_CFG0_ROM0 0x01 32040516Swpaul#define RL_CFG0_ROM1 0x02 32140516Swpaul#define RL_CFG0_ROM2 0x04 32240516Swpaul#define RL_CFG0_PL0 0x08 32340516Swpaul#define RL_CFG0_PL1 0x10 32440516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 32540516Swpaul#define RL_CFG0_PCS 0x40 32640516Swpaul#define RL_CFG0_SCR 0x80 32740516Swpaul 32840516Swpaul/* 32940516Swpaul * Config 1 register 33040516Swpaul */ 33140516Swpaul#define RL_CFG1_PWRDWN 0x01 33240516Swpaul#define RL_CFG1_SLEEP 0x02 33340516Swpaul#define RL_CFG1_IOMAP 0x04 33440516Swpaul#define RL_CFG1_MEMMAP 0x08 33540516Swpaul#define RL_CFG1_RSVD 0x10 33640516Swpaul#define RL_CFG1_DRVLOAD 0x20 33740516Swpaul#define RL_CFG1_LED0 0x40 33840516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 33940516Swpaul#define RL_CFG1_LED1 0x80 34040516Swpaul 34140516Swpaul/* 342117388Swpaul * 8139C+ register definitions 343117388Swpaul */ 344117388Swpaul 345117388Swpaul/* RL_DUMPSTATS_LO register */ 346117388Swpaul 347117388Swpaul#define RL_DUMPSTATS_START 0x00000008 348117388Swpaul 349117388Swpaul/* Transmit start register */ 350117388Swpaul 351117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 352117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 353117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 354117388Swpaul 355117388Swpaul/* C+ mode command register */ 356117388Swpaul 357117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 358117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 359117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 360117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 361117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 362117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 363117388Swpaul 364117388Swpaul/* C+ early transmit threshold */ 365117388Swpaul 366117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 367117388Swpaul 368117388Swpaul/* 369117388Swpaul * Gigabit PHY access register (8169 only) 370117388Swpaul */ 371117388Swpaul 372117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 373117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 374117388Swpaul#define RL_PHYAR_BUSY 0x80000000 375117388Swpaul 376117388Swpaul/* 377117388Swpaul * Gigabit media status (8169 only) 378117388Swpaul */ 379117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 380117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 381117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 382117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 383117388Swpaul#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */ 384117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 385117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 386117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 387117388Swpaul 388117388Swpaul/* 38940516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 39040516Swpaul * Instead, there are only four register sets, each or which represents 39140516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 39240516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 39340516Swpaul * the registers so the chip knows where they are. 39440516Swpaul * 39540516Swpaul * We can sort of kludge together the same kind of buffer management 39640516Swpaul * used in previous drivers, but we have to do buffer copies almost all 39740516Swpaul * the time, so it doesn't really buy us much. 39840516Swpaul * 39940516Swpaul * For reception, there's just one large buffer where the chip stores 40040516Swpaul * all received packets. 40140516Swpaul */ 40240516Swpaul 40340516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 40440516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 40540516Swpaul#define RL_TX_LIST_CNT 4 40640516Swpaul#define RL_MIN_FRAMELEN 60 40752426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 40852426Swpaul#define RL_TX_THRESH_INIT 96 409119868Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH 410119868Swpaul#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED 41150703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 41240516Swpaul 41345633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 41445633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 41540516Swpaul 41648028Swpaul#define RL_ETHER_ALIGN 2 41748028Swpaul 41840516Swpaulstruct rl_chain_data { 41940516Swpaul u_int16_t cur_rx; 42040516Swpaul caddr_t rl_rx_buf; 42148028Swpaul caddr_t rl_rx_buf_ptr; 42281713Swpaul bus_dmamap_t rl_rx_dmamap; 42340516Swpaul 42445633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 42581713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 42645633Swpaul u_int8_t last_tx; 42745633Swpaul u_int8_t cur_tx; 42840516Swpaul}; 42940516Swpaul 43045633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 43145633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 43245633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 43345633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 43481713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 43545633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 43645633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 43745633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 43881713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 43945633Swpaul 44040516Swpaulstruct rl_type { 44140516Swpaul u_int16_t rl_vid; 44240516Swpaul u_int16_t rl_did; 443117388Swpaul int rl_basetype; 44440516Swpaul char *rl_name; 44540516Swpaul}; 44640516Swpaul 447117388Swpaulstruct rl_hwrev { 448117388Swpaul u_int32_t rl_rev; 449117388Swpaul int rl_type; 450117388Swpaul char *rl_desc; 451117388Swpaul}; 452117388Swpaul 45340516Swpaulstruct rl_mii_frame { 45440516Swpaul u_int8_t mii_stdelim; 45540516Swpaul u_int8_t mii_opcode; 45640516Swpaul u_int8_t mii_phyaddr; 45740516Swpaul u_int8_t mii_regaddr; 45840516Swpaul u_int8_t mii_turnaround; 45940516Swpaul u_int16_t mii_data; 46040516Swpaul}; 46140516Swpaul 46240516Swpaul/* 46340516Swpaul * MII constants 46440516Swpaul */ 46540516Swpaul#define RL_MII_STARTDELIM 0x01 46640516Swpaul#define RL_MII_READOP 0x02 46740516Swpaul#define RL_MII_WRITEOP 0x01 46840516Swpaul#define RL_MII_TURNAROUND 0x02 46940516Swpaul 47040516Swpaul#define RL_8129 1 47140516Swpaul#define RL_8139 2 472117388Swpaul#define RL_8139CPLUS 3 473117388Swpaul#define RL_8169 4 47440516Swpaul 475117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 476117388Swpaul (x)->rl_type == RL_8169) 477117388Swpaul 478117388Swpaul/* 479117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 480117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 481117388Swpaul * must be allocated in contiguous blocks that are aligned on a 482117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 483117388Swpaul */ 484117388Swpaul 485117388Swpaul/* 486117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 487117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 488117388Swpaul * the checksum offload bits are disabled. The structure layout is 489117388Swpaul * the same for RX and TX descriptors 490117388Swpaul */ 491117388Swpaul 492117388Swpaulstruct rl_desc { 493117388Swpaul u_int32_t rl_cmdstat; 494117388Swpaul u_int32_t rl_vlanctl; 495117388Swpaul u_int32_t rl_bufaddr_lo; 496117388Swpaul u_int32_t rl_bufaddr_hi; 497117388Swpaul}; 498117388Swpaul 499117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 500117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 501117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 502117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 503117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 504117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 505117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 506117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 507117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 508117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 509117388Swpaul 510117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 511117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 512117388Swpaul 513117388Swpaul/* 514117388Swpaul * Error bits are valid only on the last descriptor of a frame 515117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 516117388Swpaul */ 517117388Swpaul 518117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 519117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 520117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 521117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 522117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 523117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 524117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 525117388Swpaul 526117388Swpaul/* 527117388Swpaul * RX descriptor cmd/vlan definitions 528117388Swpaul */ 529117388Swpaul 530117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 531117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 532119868Swpaul#define RL_RDESC_CMD_BUFLEN 0x00003FFF 533117388Swpaul 534117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 535117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 536117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 537117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 538117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 539117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 540117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 541117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 542117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 543117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 544117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 545117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 546117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 547117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 548117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 549117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 550117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 551117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 552119868Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00003FFF /* RX'ed frame/frag len */ 553117388Swpaul 554117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 555117388Swpaul (rl_vlandata valid)*/ 556117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 557117388Swpaul 558117388Swpaul#define RL_PROTOID_NONIP 0x00000000 559117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 560117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 561117388Swpaul#define RL_PROTOID_IP 0x00030000 562117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 563117388Swpaul RL_PROTOID_TCPIP) 564117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 565117388Swpaul RL_PROTOID_UDPIP) 566117388Swpaul 567117388Swpaul/* 568117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 569117388Swpaul */ 570117388Swpaulstruct rl_stats { 571117388Swpaul u_int32_t rl_tx_pkts_lo; 572117388Swpaul u_int32_t rl_tx_pkts_hi; 573117388Swpaul u_int32_t rl_tx_errs_lo; 574117388Swpaul u_int32_t rl_tx_errs_hi; 575117388Swpaul u_int32_t rl_tx_errs; 576117388Swpaul u_int16_t rl_missed_pkts; 577117388Swpaul u_int16_t rl_rx_framealign_errs; 578117388Swpaul u_int32_t rl_tx_onecoll; 579117388Swpaul u_int32_t rl_tx_multicolls; 580117388Swpaul u_int32_t rl_rx_ucasts_hi; 581117388Swpaul u_int32_t rl_rx_ucasts_lo; 582117388Swpaul u_int32_t rl_rx_bcasts_lo; 583117388Swpaul u_int32_t rl_rx_bcasts_hi; 584117388Swpaul u_int32_t rl_rx_mcasts; 585117388Swpaul u_int16_t rl_tx_aborts; 586117388Swpaul u_int16_t rl_rx_underruns; 587117388Swpaul}; 588117388Swpaul 589117388Swpaul#define RL_RX_DESC_CNT 64 590117388Swpaul#define RL_TX_DESC_CNT 64 591117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 592117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 593117388Swpaul#define RL_RING_ALIGN 256 594117388Swpaul#define RL_IFQ_MAXLEN 512 595117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 596117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 597117388Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 598117388Swpaul RL_RDESC_STAT_FRAGLEN) 599119868Swpaul#define RL_PKTSZ(x) ((x)/* >> 3*/) 600117388Swpaul 601118712Swpaul#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 602118712Swpaul#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 603118712Swpaul 604119868Swpaul#define RL_JUMBO_FRAMELEN 9018 605119868Swpaul#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 606119868Swpaul#define RL_JSLOTS 128 607119868Swpaul 608119868Swpaul#define RL_JRAWLEN (RL_JUMBO_FRAMELEN + ETHER_ALIGN + sizeof(u_int64_t)) 609119868Swpaul#define RL_JLEN (RL_JRAWLEN + (sizeof(u_int64_t) - \ 610119868Swpaul (RL_JRAWLEN % sizeof(u_int64_t)))) 611119868Swpaul#define RL_JPAGESZ PAGE_SIZE 612119868Swpaul#define RL_RESID (RL_JPAGESZ - (RL_JLEN * RL_JSLOTS) % RL_JPAGESZ) 613119868Swpaul#define RL_JMEM ((RL_JLEN * RL_JSLOTS) + RL_RESID) 614119868Swpaul 615117388Swpaulstruct rl_softc; 616117388Swpaul 617117388Swpaulstruct rl_dmaload_arg { 618117388Swpaul struct rl_softc *sc; 619117388Swpaul int rl_idx; 620117388Swpaul int rl_maxsegs; 621118889Swpaul u_int32_t rl_flags; 622117388Swpaul struct rl_desc *rl_ring; 623117388Swpaul}; 624117388Swpaul 625117388Swpaulstruct rl_list_data { 626117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 627117388Swpaul struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 628117388Swpaul int rl_tx_prodidx; 629117388Swpaul int rl_rx_prodidx; 630117388Swpaul int rl_tx_considx; 631117388Swpaul int rl_tx_free; 632117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 633117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 634117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 635117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 636117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 637117388Swpaul struct rl_stats *rl_stats; 638118712Swpaul bus_addr_t rl_stats_addr; 639117388Swpaul bus_dma_tag_t rl_rx_list_tag; 640117388Swpaul bus_dmamap_t rl_rx_list_map; 641117388Swpaul struct rl_desc *rl_rx_list; 642118712Swpaul bus_addr_t rl_rx_list_addr; 643117388Swpaul bus_dma_tag_t rl_tx_list_tag; 644117388Swpaul bus_dmamap_t rl_tx_list_map; 645117388Swpaul struct rl_desc *rl_tx_list; 646118712Swpaul bus_addr_t rl_tx_list_addr; 647117388Swpaul}; 648117388Swpaul 64940516Swpaulstruct rl_softc { 65040516Swpaul struct arpcom arpcom; /* interface info */ 65141569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 65241569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 65350703Swpaul struct resource *rl_res; 65450703Swpaul struct resource *rl_irq; 65550703Swpaul void *rl_intrhand; 65650703Swpaul device_t rl_miibus; 65781713Swpaul bus_dma_tag_t rl_parent_tag; 65881713Swpaul bus_dma_tag_t rl_tag; 65940516Swpaul u_int8_t rl_unit; /* interface number */ 66040516Swpaul u_int8_t rl_type; 66167931Swpaul int rl_eecmd_read; 66240516Swpaul u_int8_t rl_stats_no_timeout; 66352426Swpaul int rl_txthresh; 66440516Swpaul struct rl_chain_data rl_cdata; 665117388Swpaul struct rl_list_data rl_ldata; 66650703Swpaul struct callout_handle rl_stat_ch; 66767087Swpaul struct mtx rl_mtx; 668119868Swpaul struct mbuf *rl_head; 669119868Swpaul struct mbuf *rl_tail; 670119868Swpaul u_int32_t rl_hwrev; 671119868Swpaul int rl_testmode; 67286822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 67394883Sluigi#ifdef DEVICE_POLLING 67494883Sluigi int rxcycles; 67594883Sluigi#endif 67686822Siwasaki 67786822Siwasaki u_int32_t saved_maps[5]; /* pci data */ 67886822Siwasaki u_int32_t saved_biosaddr; 67986822Siwasaki u_int8_t saved_intline; 68086822Siwasaki u_int8_t saved_cachelnsz; 68186822Siwasaki u_int8_t saved_lattimer; 68240516Swpaul}; 68340516Swpaul 68472200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 68572200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 68667087Swpaul 68740516Swpaul/* 68840516Swpaul * register space access macros 68940516Swpaul */ 690119868Swpaul#define CSR_WRITE_STREAM_4(sc, reg, val) \ 691119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 69240516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 69341569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 69440516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 69541569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 69640516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 69741569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 69840516Swpaul 69941569Swpaul#define CSR_READ_4(sc, reg) \ 70041569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 70141569Swpaul#define CSR_READ_2(sc, reg) \ 70241569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 70341569Swpaul#define CSR_READ_1(sc, reg) \ 70441569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 70540516Swpaul 70640516Swpaul#define RL_TIMEOUT 1000 70740516Swpaul 70840516Swpaul/* 70940516Swpaul * General constants that are fun to know. 71040516Swpaul * 71140516Swpaul * RealTek PCI vendor ID 71240516Swpaul */ 71340516Swpaul#define RT_VENDORID 0x10EC 71440516Swpaul 71540516Swpaul/* 71640516Swpaul * RealTek chip device IDs. 71740516Swpaul */ 71840516Swpaul#define RT_DEVICEID_8129 0x8129 71967771Swpaul#define RT_DEVICEID_8138 0x8138 72040516Swpaul#define RT_DEVICEID_8139 0x8139 721117388Swpaul#define RT_DEVICEID_8169 0x8169 722118978Swpaul#define RT_DEVICEID_8100 0x8100 72340516Swpaul 724117388Swpaul#define RT_REVID_8139CPLUS 0x20 725117388Swpaul 72640516Swpaul/* 72744238Swpaul * Accton PCI vendor ID 72844238Swpaul */ 72944238Swpaul#define ACCTON_VENDORID 0x1113 73044238Swpaul 73144238Swpaul/* 73241243Swpaul * Accton MPX 5030/5038 device ID. 73341243Swpaul */ 73441243Swpaul#define ACCTON_DEVICEID_5030 0x1211 73541243Swpaul 73641243Swpaul/* 73794400Swpaul * Nortel PCI vendor ID 73894400Swpaul */ 73994400Swpaul#define NORTEL_VENDORID 0x126C 74094400Swpaul 74194400Swpaul/* 74244238Swpaul * Delta Electronics Vendor ID. 74344238Swpaul */ 74444238Swpaul#define DELTA_VENDORID 0x1500 74544238Swpaul 74644238Swpaul/* 74744238Swpaul * Delta device IDs. 74844238Swpaul */ 74944238Swpaul#define DELTA_DEVICEID_8139 0x1360 75044238Swpaul 75144238Swpaul/* 75244238Swpaul * Addtron vendor ID. 75344238Swpaul */ 75444238Swpaul#define ADDTRON_VENDORID 0x4033 75544238Swpaul 75644238Swpaul/* 75744238Swpaul * Addtron device IDs. 75844238Swpaul */ 75944238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 76044238Swpaul 76144238Swpaul/* 76272813Swpaul * D-Link vendor ID. 76372813Swpaul */ 76472813Swpaul#define DLINK_VENDORID 0x1186 76572813Swpaul 76672813Swpaul/* 76772813Swpaul * D-Link DFE-530TX+ device ID 76872813Swpaul */ 76972813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 77072813Swpaul 77172813Swpaul/* 77296112Sjhb * D-Link DFE-690TXD device ID 77396112Sjhb */ 77496112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 77596112Sjhb 77696112Sjhb/* 777103020Siwasaki * Corega K.K vendor ID 778103020Siwasaki */ 779103020Siwasaki#define COREGA_VENDORID 0x1259 780103020Siwasaki 781103020Siwasaki/* 782109095Ssanpei * Corega FEther CB-TXD device ID 783103020Siwasaki */ 784109095Ssanpei#define COREGA_DEVICEID_FETHERCBTXD 0xa117 785103020Siwasaki 786103020Siwasaki/* 787109095Ssanpei * Corega FEtherII CB-TXD device ID 788109095Ssanpei */ 789109095Ssanpei#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 790109095Ssanpei 791111381Sdan/* 792111381Sdan * Peppercon vendor ID 793111381Sdan */ 794111381Sdan#define PEPPERCON_VENDORID 0x1743 795109095Ssanpei 796111381Sdan/* 797111381Sdan * Peppercon ROL-F device ID 798111381Sdan */ 799111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 800109095Ssanpei 801109095Ssanpei/* 802112379Ssanpei * Planex Communications, Inc. vendor ID 803112379Ssanpei */ 804117388Swpaul#define PLANEX_VENDORID 0x14ea 805112379Ssanpei 806112379Ssanpei/* 807112379Ssanpei * Planex FNW-3800-TX device ID 808112379Ssanpei */ 809117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 810112379Ssanpei 811112379Ssanpei/* 812117388Swpaul * LevelOne vendor ID 813117388Swpaul */ 814117388Swpaul#define LEVEL1_VENDORID 0x018A 815117388Swpaul 816117388Swpaul/* 817117388Swpaul * LevelOne FPC-0106TX devide ID 818117388Swpaul */ 819117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 820117388Swpaul 821117388Swpaul/* 822117388Swpaul * Compaq vendor ID 823117388Swpaul */ 824117388Swpaul#define CP_VENDORID 0x021B 825117388Swpaul 826117388Swpaul/* 827117388Swpaul * Edimax vendor ID 828117388Swpaul */ 829117388Swpaul#define EDIMAX_VENDORID 0x13D1 830117388Swpaul 831117388Swpaul/* 832117388Swpaul * Edimax EP-4103DL cardbus device ID 833117388Swpaul */ 834117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 835117388Swpaul 836117388Swpaul/* 83740516Swpaul * PCI low memory base and low I/O base register, and 83850703Swpaul * other PCI registers. 83940516Swpaul */ 84040516Swpaul 84140516Swpaul#define RL_PCI_VENDOR_ID 0x00 84240516Swpaul#define RL_PCI_DEVICE_ID 0x02 84340516Swpaul#define RL_PCI_COMMAND 0x04 84440516Swpaul#define RL_PCI_STATUS 0x06 84540516Swpaul#define RL_PCI_CLASSCODE 0x09 84640516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 84740516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 84840516Swpaul#define RL_PCI_LOIO 0x10 84940516Swpaul#define RL_PCI_LOMEM 0x14 85040516Swpaul#define RL_PCI_BIOSROM 0x30 85140516Swpaul#define RL_PCI_INTLINE 0x3C 85240516Swpaul#define RL_PCI_INTPIN 0x3D 85340516Swpaul#define RL_PCI_MINGNT 0x3E 85440516Swpaul#define RL_PCI_MINLAT 0x0F 85540516Swpaul#define RL_PCI_RESETOPT 0x48 85640516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 85740516Swpaul 85850097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 85950097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 86050097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 86150097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 86240516Swpaul 86340516Swpaul#define RL_PSTATE_MASK 0x0003 86440516Swpaul#define RL_PSTATE_D0 0x0000 86540516Swpaul#define RL_PSTATE_D1 0x0002 86640516Swpaul#define RL_PSTATE_D2 0x0002 86740516Swpaul#define RL_PSTATE_D3 0x0003 86840516Swpaul#define RL_PME_EN 0x0010 86940516Swpaul#define RL_PME_STATUS 0x8000 870