if_rlreg.h revision 119738
140516Swpaul/* 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 119738 2003-09-04 15:39:44Z tmm $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 7940516Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 115117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 11940516Swpaul 12040516Swpaul/* 121117388Swpaul * Registers specific to the 8169 gigE chip 122117388Swpaul */ 123118586Swpaul#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 124117388Swpaul#define RL_PHYAR 0x0060 125117388Swpaul#define RL_TBICSR 0x0064 126117388Swpaul#define RL_TBI_ANAR 0x0068 127117388Swpaul#define RL_TBI_LPAR 0x006A 128117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 129117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 130117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 131117388Swpaul 132117388Swpaul/* 13340516Swpaul * TX config register bits 13440516Swpaul */ 13540516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13645633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13740516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13845633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 13945633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 140117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14140516Swpaul 142118586Swpaul#define RL_HWREV_8169 0x00000000 143118586Swpaul#define RL_HWREV_8110 0x00800000 144117388Swpaul#define RL_HWREV_8139 0x60000000 145117388Swpaul#define RL_HWREV_8139A 0x70000000 146117388Swpaul#define RL_HWREV_8139AG 0x70800000 147117388Swpaul#define RL_HWREV_8139B 0x78000000 148117388Swpaul#define RL_HWREV_8130 0x7C000000 149117388Swpaul#define RL_HWREV_8139C 0x74000000 150117388Swpaul#define RL_HWREV_8139D 0x74400000 151117388Swpaul#define RL_HWREV_8139CPLUS 0x74800000 152118586Swpaul#define RL_HWREV_8101 0x74c00000 153118586Swpaul#define RL_HWREV_8100 0x78800000 154117388Swpaul 15545633Swpaul#define RL_TXDMA_16BYTES 0x00000000 15645633Swpaul#define RL_TXDMA_32BYTES 0x00000100 15745633Swpaul#define RL_TXDMA_64BYTES 0x00000200 15845633Swpaul#define RL_TXDMA_128BYTES 0x00000300 15945633Swpaul#define RL_TXDMA_256BYTES 0x00000400 16045633Swpaul#define RL_TXDMA_512BYTES 0x00000500 16145633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 16245633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 16345633Swpaul 16440516Swpaul/* 16540516Swpaul * Transmit descriptor status register bits. 16640516Swpaul */ 16740516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 16840516Swpaul#define RL_TXSTAT_OWN 0x00002000 16940516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 17040516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 17140516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 17240516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 17340516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 17440516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 17540516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 17640516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 17740516Swpaul 17840516Swpaul/* 17940516Swpaul * Interrupt status register bits. 18040516Swpaul */ 18140516Swpaul#define RL_ISR_RX_OK 0x0001 18240516Swpaul#define RL_ISR_RX_ERR 0x0002 18340516Swpaul#define RL_ISR_TX_OK 0x0004 18440516Swpaul#define RL_ISR_TX_ERR 0x0008 18540516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 18640516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 18740516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 188117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 189117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 190117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 19140516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 192117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 19340516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 19440516Swpaul 19540516Swpaul#define RL_INTRS \ 19640516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 19740516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 19840516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 19940516Swpaul 200117388Swpaul#define RL_INTRS_CPLUS \ 201117388Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 202117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 203117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 204117388Swpaul 20540516Swpaul/* 20640516Swpaul * Media status register. (8139 only) 20740516Swpaul */ 20840516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 20940516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 21040516Swpaul#define RL_MEDIASTAT_LINK 0x04 21140516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 21240516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 21340516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 21440516Swpaul 21540516Swpaul/* 21640516Swpaul * Receive config register. 21740516Swpaul */ 21840516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 21940516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 22040516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 22140516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 22240516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 22340516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 22440516Swpaul#define RL_RXCFG_WRAP 0x00000080 22545633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 22645633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 22745633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 22845633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 22940516Swpaul 23045633Swpaul#define RL_RXDMA_16BYTES 0x00000000 23145633Swpaul#define RL_RXDMA_32BYTES 0x00000100 23245633Swpaul#define RL_RXDMA_64BYTES 0x00000200 23345633Swpaul#define RL_RXDMA_128BYTES 0x00000300 23445633Swpaul#define RL_RXDMA_256BYTES 0x00000400 23545633Swpaul#define RL_RXDMA_512BYTES 0x00000500 23645633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 23745633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 23845633Swpaul 23940516Swpaul#define RL_RXBUF_8 0x00000000 24040516Swpaul#define RL_RXBUF_16 0x00000800 24140516Swpaul#define RL_RXBUF_32 0x00001000 24245633Swpaul#define RL_RXBUF_64 0x00001800 24340516Swpaul 24445633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 24545633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 24645633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 24745633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 24845633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 24945633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 25045633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 25145633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 25245633Swpaul 25340516Swpaul/* 25440516Swpaul * Bits in RX status header (included with RX'ed packet 25540516Swpaul * in ring buffer). 25640516Swpaul */ 25740516Swpaul#define RL_RXSTAT_RXOK 0x00000001 25840516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 25940516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 26040516Swpaul#define RL_RXSTAT_GIANT 0x00000008 26140516Swpaul#define RL_RXSTAT_RUNT 0x00000010 26240516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 26340516Swpaul#define RL_RXSTAT_BROAD 0x00002000 26440516Swpaul#define RL_RXSTAT_INDIV 0x00004000 26540516Swpaul#define RL_RXSTAT_MULTI 0x00008000 26640516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 26740516Swpaul 26840516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 26940516Swpaul/* 27040516Swpaul * Command register. 27140516Swpaul */ 27240516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 27340516Swpaul#define RL_CMD_TX_ENB 0x0004 27440516Swpaul#define RL_CMD_RX_ENB 0x0008 27540516Swpaul#define RL_CMD_RESET 0x0010 27640516Swpaul 27740516Swpaul/* 27840516Swpaul * EEPROM control register 27940516Swpaul */ 28040516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 28140516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 28240516Swpaul#define RL_EE_CLK 0x04 /* clock */ 28340516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 28440516Swpaul#define RL_EE_MODE (0x40|0x80) 28540516Swpaul 28640516Swpaul#define RL_EEMODE_OFF 0x00 28740516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 28840516Swpaul#define RL_EEMODE_PROGRAM 0x80 28940516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 29040516Swpaul 29140516Swpaul/* 9346 EEPROM commands */ 29240516Swpaul#define RL_EECMD_WRITE 0x140 29367931Swpaul#define RL_EECMD_READ_6BIT 0x180 29467931Swpaul#define RL_EECMD_READ_8BIT 0x600 29540516Swpaul#define RL_EECMD_ERASE 0x1c0 29640516Swpaul 29740516Swpaul#define RL_EE_ID 0x00 29840516Swpaul#define RL_EE_PCI_VID 0x01 29940516Swpaul#define RL_EE_PCI_DID 0x02 30040516Swpaul/* Location of station address inside EEPROM */ 30140516Swpaul#define RL_EE_EADDR 0x07 30240516Swpaul 30340516Swpaul/* 30440516Swpaul * MII register (8129 only) 30540516Swpaul */ 30640516Swpaul#define RL_MII_CLK 0x01 30740516Swpaul#define RL_MII_DATAIN 0x02 30840516Swpaul#define RL_MII_DATAOUT 0x04 30940516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 31040516Swpaul 31140516Swpaul/* 31240516Swpaul * Config 0 register 31340516Swpaul */ 31440516Swpaul#define RL_CFG0_ROM0 0x01 31540516Swpaul#define RL_CFG0_ROM1 0x02 31640516Swpaul#define RL_CFG0_ROM2 0x04 31740516Swpaul#define RL_CFG0_PL0 0x08 31840516Swpaul#define RL_CFG0_PL1 0x10 31940516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 32040516Swpaul#define RL_CFG0_PCS 0x40 32140516Swpaul#define RL_CFG0_SCR 0x80 32240516Swpaul 32340516Swpaul/* 32440516Swpaul * Config 1 register 32540516Swpaul */ 32640516Swpaul#define RL_CFG1_PWRDWN 0x01 32740516Swpaul#define RL_CFG1_SLEEP 0x02 32840516Swpaul#define RL_CFG1_IOMAP 0x04 32940516Swpaul#define RL_CFG1_MEMMAP 0x08 33040516Swpaul#define RL_CFG1_RSVD 0x10 33140516Swpaul#define RL_CFG1_DRVLOAD 0x20 33240516Swpaul#define RL_CFG1_LED0 0x40 33340516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 33440516Swpaul#define RL_CFG1_LED1 0x80 33540516Swpaul 33640516Swpaul/* 337117388Swpaul * 8139C+ register definitions 338117388Swpaul */ 339117388Swpaul 340117388Swpaul/* RL_DUMPSTATS_LO register */ 341117388Swpaul 342117388Swpaul#define RL_DUMPSTATS_START 0x00000008 343117388Swpaul 344117388Swpaul/* Transmit start register */ 345117388Swpaul 346117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 347117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 348117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 349117388Swpaul 350117388Swpaul/* C+ mode command register */ 351117388Swpaul 352117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 353117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 354117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 355117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 356117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 357117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 358117388Swpaul 359117388Swpaul/* C+ early transmit threshold */ 360117388Swpaul 361117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 362117388Swpaul 363117388Swpaul/* 364117388Swpaul * Gigabit PHY access register (8169 only) 365117388Swpaul */ 366117388Swpaul 367117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 368117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 369117388Swpaul#define RL_PHYAR_BUSY 0x80000000 370117388Swpaul 371117388Swpaul/* 372117388Swpaul * Gigabit media status (8169 only) 373117388Swpaul */ 374117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 375117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 376117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 377117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 378117388Swpaul#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */ 379117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 380117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 381117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 382117388Swpaul 383117388Swpaul/* 38440516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 38540516Swpaul * Instead, there are only four register sets, each or which represents 38640516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 38740516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 38840516Swpaul * the registers so the chip knows where they are. 38940516Swpaul * 39040516Swpaul * We can sort of kludge together the same kind of buffer management 39140516Swpaul * used in previous drivers, but we have to do buffer copies almost all 39240516Swpaul * the time, so it doesn't really buy us much. 39340516Swpaul * 39440516Swpaul * For reception, there's just one large buffer where the chip stores 39540516Swpaul * all received packets. 39640516Swpaul */ 39740516Swpaul 39840516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 39940516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 40040516Swpaul#define RL_TX_LIST_CNT 4 40140516Swpaul#define RL_MIN_FRAMELEN 60 40252426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 40352426Swpaul#define RL_TX_THRESH_INIT 96 40448056Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 40581713Swpaul#define RL_RX_MAXDMA RL_RXDMA_1024BYTES /*RL_RXDMA_UNLIMITED*/ 40650703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 40740516Swpaul 40845633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 40945633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 41040516Swpaul 41148028Swpaul#define RL_ETHER_ALIGN 2 41248028Swpaul 41340516Swpaulstruct rl_chain_data { 41440516Swpaul u_int16_t cur_rx; 41540516Swpaul caddr_t rl_rx_buf; 41648028Swpaul caddr_t rl_rx_buf_ptr; 41781713Swpaul bus_dmamap_t rl_rx_dmamap; 41840516Swpaul 41945633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 42081713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 42145633Swpaul u_int8_t last_tx; 42245633Swpaul u_int8_t cur_tx; 42340516Swpaul}; 42440516Swpaul 42545633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 42645633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 42745633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 42845633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 42981713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 43045633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 43145633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 43245633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 43381713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 43445633Swpaul 43540516Swpaulstruct rl_type { 43640516Swpaul u_int16_t rl_vid; 43740516Swpaul u_int16_t rl_did; 438117388Swpaul int rl_basetype; 43940516Swpaul char *rl_name; 44040516Swpaul}; 44140516Swpaul 442117388Swpaulstruct rl_hwrev { 443117388Swpaul u_int32_t rl_rev; 444117388Swpaul int rl_type; 445117388Swpaul char *rl_desc; 446117388Swpaul}; 447117388Swpaul 44840516Swpaulstruct rl_mii_frame { 44940516Swpaul u_int8_t mii_stdelim; 45040516Swpaul u_int8_t mii_opcode; 45140516Swpaul u_int8_t mii_phyaddr; 45240516Swpaul u_int8_t mii_regaddr; 45340516Swpaul u_int8_t mii_turnaround; 45440516Swpaul u_int16_t mii_data; 45540516Swpaul}; 45640516Swpaul 45740516Swpaul/* 45840516Swpaul * MII constants 45940516Swpaul */ 46040516Swpaul#define RL_MII_STARTDELIM 0x01 46140516Swpaul#define RL_MII_READOP 0x02 46240516Swpaul#define RL_MII_WRITEOP 0x01 46340516Swpaul#define RL_MII_TURNAROUND 0x02 46440516Swpaul 46540516Swpaul#define RL_8129 1 46640516Swpaul#define RL_8139 2 467117388Swpaul#define RL_8139CPLUS 3 468117388Swpaul#define RL_8169 4 46940516Swpaul 470117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 471117388Swpaul (x)->rl_type == RL_8169) 472117388Swpaul 473117388Swpaul/* 474117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 475117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 476117388Swpaul * must be allocated in contiguous blocks that are aligned on a 477117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 478117388Swpaul */ 479117388Swpaul 480117388Swpaul/* 481117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 482117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 483117388Swpaul * the checksum offload bits are disabled. The structure layout is 484117388Swpaul * the same for RX and TX descriptors 485117388Swpaul */ 486117388Swpaul 487117388Swpaulstruct rl_desc { 488117388Swpaul u_int32_t rl_cmdstat; 489117388Swpaul u_int32_t rl_vlanctl; 490117388Swpaul u_int32_t rl_bufaddr_lo; 491117388Swpaul u_int32_t rl_bufaddr_hi; 492117388Swpaul}; 493117388Swpaul 494117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 495117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 496117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 497117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 498117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 499117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 500117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 501117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 502117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 503117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 504117388Swpaul 505117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 506117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 507117388Swpaul 508117388Swpaul/* 509117388Swpaul * Error bits are valid only on the last descriptor of a frame 510117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 511117388Swpaul */ 512117388Swpaul 513117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 514117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 515117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 516117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 517117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 518117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 519117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 520117388Swpaul 521117388Swpaul/* 522117388Swpaul * RX descriptor cmd/vlan definitions 523117388Swpaul */ 524117388Swpaul 525117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 526117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 527117388Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 528117388Swpaul 529117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 530117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 531117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 532117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 533117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 534117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 535117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 536117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 537117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 538117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 539117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 540117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 541117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 542117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 543117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 544117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 545117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 546117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 547117388Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 548117388Swpaul 549117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 550117388Swpaul (rl_vlandata valid)*/ 551117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 552117388Swpaul 553117388Swpaul#define RL_PROTOID_NONIP 0x00000000 554117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 555117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 556117388Swpaul#define RL_PROTOID_IP 0x00030000 557117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 558117388Swpaul RL_PROTOID_TCPIP) 559117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 560117388Swpaul RL_PROTOID_UDPIP) 561117388Swpaul 562117388Swpaul/* 563117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 564117388Swpaul */ 565117388Swpaulstruct rl_stats { 566117388Swpaul u_int32_t rl_tx_pkts_lo; 567117388Swpaul u_int32_t rl_tx_pkts_hi; 568117388Swpaul u_int32_t rl_tx_errs_lo; 569117388Swpaul u_int32_t rl_tx_errs_hi; 570117388Swpaul u_int32_t rl_tx_errs; 571117388Swpaul u_int16_t rl_missed_pkts; 572117388Swpaul u_int16_t rl_rx_framealign_errs; 573117388Swpaul u_int32_t rl_tx_onecoll; 574117388Swpaul u_int32_t rl_tx_multicolls; 575117388Swpaul u_int32_t rl_rx_ucasts_hi; 576117388Swpaul u_int32_t rl_rx_ucasts_lo; 577117388Swpaul u_int32_t rl_rx_bcasts_lo; 578117388Swpaul u_int32_t rl_rx_bcasts_hi; 579117388Swpaul u_int32_t rl_rx_mcasts; 580117388Swpaul u_int16_t rl_tx_aborts; 581117388Swpaul u_int16_t rl_rx_underruns; 582117388Swpaul}; 583117388Swpaul 584117388Swpaul#define RL_RX_DESC_CNT 64 585117388Swpaul#define RL_TX_DESC_CNT 64 586117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 587117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 588117388Swpaul#define RL_RING_ALIGN 256 589117388Swpaul#define RL_IFQ_MAXLEN 512 590117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 591117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 592117388Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 593117388Swpaul RL_RDESC_STAT_FRAGLEN) 594117388Swpaul#define RL_PKTSZ(x) ((x) >> 3) 595117388Swpaul 596118712Swpaul#define RL_ADDR_LO(y) ((u_int64_t) (y) & 0xFFFFFFFF) 597118712Swpaul#define RL_ADDR_HI(y) ((u_int64_t) (y) >> 32) 598118712Swpaul 599117388Swpaulstruct rl_softc; 600117388Swpaul 601117388Swpaulstruct rl_dmaload_arg { 602117388Swpaul struct rl_softc *sc; 603117388Swpaul int rl_idx; 604117388Swpaul int rl_maxsegs; 605118889Swpaul u_int32_t rl_flags; 606117388Swpaul struct rl_desc *rl_ring; 607117388Swpaul}; 608117388Swpaul 609117388Swpaulstruct rl_list_data { 610117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 611117388Swpaul struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 612117388Swpaul int rl_tx_prodidx; 613117388Swpaul int rl_rx_prodidx; 614117388Swpaul int rl_tx_considx; 615117388Swpaul int rl_tx_free; 616117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 617117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 618117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 619117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 620117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 621117388Swpaul struct rl_stats *rl_stats; 622118712Swpaul bus_addr_t rl_stats_addr; 623117388Swpaul bus_dma_tag_t rl_rx_list_tag; 624117388Swpaul bus_dmamap_t rl_rx_list_map; 625117388Swpaul struct rl_desc *rl_rx_list; 626118712Swpaul bus_addr_t rl_rx_list_addr; 627117388Swpaul bus_dma_tag_t rl_tx_list_tag; 628117388Swpaul bus_dmamap_t rl_tx_list_map; 629117388Swpaul struct rl_desc *rl_tx_list; 630118712Swpaul bus_addr_t rl_tx_list_addr; 631117388Swpaul}; 632117388Swpaul 63340516Swpaulstruct rl_softc { 63440516Swpaul struct arpcom arpcom; /* interface info */ 63541569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 63641569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 63750703Swpaul struct resource *rl_res; 63850703Swpaul struct resource *rl_irq; 63950703Swpaul void *rl_intrhand; 64050703Swpaul device_t rl_miibus; 64181713Swpaul bus_dma_tag_t rl_parent_tag; 64281713Swpaul bus_dma_tag_t rl_tag; 64340516Swpaul u_int8_t rl_unit; /* interface number */ 64440516Swpaul u_int8_t rl_type; 64567931Swpaul int rl_eecmd_read; 64640516Swpaul u_int8_t rl_stats_no_timeout; 64752426Swpaul int rl_txthresh; 64840516Swpaul struct rl_chain_data rl_cdata; 649117388Swpaul struct rl_list_data rl_ldata; 65050703Swpaul struct callout_handle rl_stat_ch; 65167087Swpaul struct mtx rl_mtx; 65286822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 65394883Sluigi#ifdef DEVICE_POLLING 65494883Sluigi int rxcycles; 65594883Sluigi#endif 65686822Siwasaki 65786822Siwasaki u_int32_t saved_maps[5]; /* pci data */ 65886822Siwasaki u_int32_t saved_biosaddr; 65986822Siwasaki u_int8_t saved_intline; 66086822Siwasaki u_int8_t saved_cachelnsz; 66186822Siwasaki u_int8_t saved_lattimer; 66240516Swpaul}; 66340516Swpaul 66472200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 66572200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 66667087Swpaul 66740516Swpaul/* 66840516Swpaul * register space access macros 66940516Swpaul */ 670119738Stmm#define CSR_WRITE_STREAM_4(sc, reg, val) \ 671119738Stmm bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val) 67240516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 67341569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 67440516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 67541569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 67640516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 67741569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 67840516Swpaul 67941569Swpaul#define CSR_READ_4(sc, reg) \ 68041569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 68141569Swpaul#define CSR_READ_2(sc, reg) \ 68241569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 68341569Swpaul#define CSR_READ_1(sc, reg) \ 68441569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 68540516Swpaul 68640516Swpaul#define RL_TIMEOUT 1000 68740516Swpaul 68840516Swpaul/* 68940516Swpaul * General constants that are fun to know. 69040516Swpaul * 69140516Swpaul * RealTek PCI vendor ID 69240516Swpaul */ 69340516Swpaul#define RT_VENDORID 0x10EC 69440516Swpaul 69540516Swpaul/* 69640516Swpaul * RealTek chip device IDs. 69740516Swpaul */ 69840516Swpaul#define RT_DEVICEID_8129 0x8129 69967771Swpaul#define RT_DEVICEID_8138 0x8138 70040516Swpaul#define RT_DEVICEID_8139 0x8139 701117388Swpaul#define RT_DEVICEID_8169 0x8169 702118978Swpaul#define RT_DEVICEID_8100 0x8100 70340516Swpaul 704117388Swpaul#define RT_REVID_8139CPLUS 0x20 705117388Swpaul 70640516Swpaul/* 70744238Swpaul * Accton PCI vendor ID 70844238Swpaul */ 70944238Swpaul#define ACCTON_VENDORID 0x1113 71044238Swpaul 71144238Swpaul/* 71241243Swpaul * Accton MPX 5030/5038 device ID. 71341243Swpaul */ 71441243Swpaul#define ACCTON_DEVICEID_5030 0x1211 71541243Swpaul 71641243Swpaul/* 71794400Swpaul * Nortel PCI vendor ID 71894400Swpaul */ 71994400Swpaul#define NORTEL_VENDORID 0x126C 72094400Swpaul 72194400Swpaul/* 72244238Swpaul * Delta Electronics Vendor ID. 72344238Swpaul */ 72444238Swpaul#define DELTA_VENDORID 0x1500 72544238Swpaul 72644238Swpaul/* 72744238Swpaul * Delta device IDs. 72844238Swpaul */ 72944238Swpaul#define DELTA_DEVICEID_8139 0x1360 73044238Swpaul 73144238Swpaul/* 73244238Swpaul * Addtron vendor ID. 73344238Swpaul */ 73444238Swpaul#define ADDTRON_VENDORID 0x4033 73544238Swpaul 73644238Swpaul/* 73744238Swpaul * Addtron device IDs. 73844238Swpaul */ 73944238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 74044238Swpaul 74144238Swpaul/* 74272813Swpaul * D-Link vendor ID. 74372813Swpaul */ 74472813Swpaul#define DLINK_VENDORID 0x1186 74572813Swpaul 74672813Swpaul/* 74772813Swpaul * D-Link DFE-530TX+ device ID 74872813Swpaul */ 74972813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 75072813Swpaul 75172813Swpaul/* 75296112Sjhb * D-Link DFE-690TXD device ID 75396112Sjhb */ 75496112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 75596112Sjhb 75696112Sjhb/* 757103020Siwasaki * Corega K.K vendor ID 758103020Siwasaki */ 759103020Siwasaki#define COREGA_VENDORID 0x1259 760103020Siwasaki 761103020Siwasaki/* 762109095Ssanpei * Corega FEther CB-TXD device ID 763103020Siwasaki */ 764109095Ssanpei#define COREGA_DEVICEID_FETHERCBTXD 0xa117 765103020Siwasaki 766103020Siwasaki/* 767109095Ssanpei * Corega FEtherII CB-TXD device ID 768109095Ssanpei */ 769109095Ssanpei#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 770109095Ssanpei 771111381Sdan/* 772111381Sdan * Peppercon vendor ID 773111381Sdan */ 774111381Sdan#define PEPPERCON_VENDORID 0x1743 775109095Ssanpei 776111381Sdan/* 777111381Sdan * Peppercon ROL-F device ID 778111381Sdan */ 779111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 780109095Ssanpei 781109095Ssanpei/* 782112379Ssanpei * Planex Communications, Inc. vendor ID 783112379Ssanpei */ 784117388Swpaul#define PLANEX_VENDORID 0x14ea 785112379Ssanpei 786112379Ssanpei/* 787112379Ssanpei * Planex FNW-3800-TX device ID 788112379Ssanpei */ 789117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 790112379Ssanpei 791112379Ssanpei/* 792117388Swpaul * LevelOne vendor ID 793117388Swpaul */ 794117388Swpaul#define LEVEL1_VENDORID 0x018A 795117388Swpaul 796117388Swpaul/* 797117388Swpaul * LevelOne FPC-0106TX devide ID 798117388Swpaul */ 799117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 800117388Swpaul 801117388Swpaul/* 802117388Swpaul * Compaq vendor ID 803117388Swpaul */ 804117388Swpaul#define CP_VENDORID 0x021B 805117388Swpaul 806117388Swpaul/* 807117388Swpaul * Edimax vendor ID 808117388Swpaul */ 809117388Swpaul#define EDIMAX_VENDORID 0x13D1 810117388Swpaul 811117388Swpaul/* 812117388Swpaul * Edimax EP-4103DL cardbus device ID 813117388Swpaul */ 814117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 815117388Swpaul 816117388Swpaul/* 81740516Swpaul * PCI low memory base and low I/O base register, and 81850703Swpaul * other PCI registers. 81940516Swpaul */ 82040516Swpaul 82140516Swpaul#define RL_PCI_VENDOR_ID 0x00 82240516Swpaul#define RL_PCI_DEVICE_ID 0x02 82340516Swpaul#define RL_PCI_COMMAND 0x04 82440516Swpaul#define RL_PCI_STATUS 0x06 82540516Swpaul#define RL_PCI_CLASSCODE 0x09 82640516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 82740516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 82840516Swpaul#define RL_PCI_LOIO 0x10 82940516Swpaul#define RL_PCI_LOMEM 0x14 83040516Swpaul#define RL_PCI_BIOSROM 0x30 83140516Swpaul#define RL_PCI_INTLINE 0x3C 83240516Swpaul#define RL_PCI_INTPIN 0x3D 83340516Swpaul#define RL_PCI_MINGNT 0x3E 83440516Swpaul#define RL_PCI_MINLAT 0x0F 83540516Swpaul#define RL_PCI_RESETOPT 0x48 83640516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 83740516Swpaul 83850097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 83950097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 84050097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 84150097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 84240516Swpaul 84340516Swpaul#define RL_PSTATE_MASK 0x0003 84440516Swpaul#define RL_PSTATE_D0 0x0000 84540516Swpaul#define RL_PSTATE_D1 0x0002 84640516Swpaul#define RL_PSTATE_D2 0x0002 84740516Swpaul#define RL_PSTATE_D3 0x0003 84840516Swpaul#define RL_PME_EN 0x0010 84940516Swpaul#define RL_PME_STATUS 0x8000 850