if_rlreg.h revision 117388
140516Swpaul/* 2117388Swpaul * Copyright (c) 1997, 1998-2003 340516Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 440516Swpaul * 540516Swpaul * Redistribution and use in source and binary forms, with or without 640516Swpaul * modification, are permitted provided that the following conditions 740516Swpaul * are met: 840516Swpaul * 1. Redistributions of source code must retain the above copyright 940516Swpaul * notice, this list of conditions and the following disclaimer. 1040516Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1140516Swpaul * notice, this list of conditions and the following disclaimer in the 1240516Swpaul * documentation and/or other materials provided with the distribution. 1340516Swpaul * 3. All advertising materials mentioning features or use of this software 1440516Swpaul * must display the following acknowledgement: 1540516Swpaul * This product includes software developed by Bill Paul. 1640516Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1740516Swpaul * may be used to endorse or promote products derived from this software 1840516Swpaul * without specific prior written permission. 1940516Swpaul * 2040516Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2140516Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2240516Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2340516Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2440516Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2540516Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2640516Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2740516Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2840516Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2940516Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3040516Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3140516Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_rlreg.h 117388 2003-07-10 20:38:48Z wpaul $ 3340516Swpaul */ 3440516Swpaul 3540516Swpaul/* 3640516Swpaul * RealTek 8129/8139 register offsets 3740516Swpaul */ 3840516Swpaul#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 3940516Swpaul#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 4040516Swpaul#define RL_IDR2 0x0002 4140516Swpaul#define RL_IDR3 0x0003 4240516Swpaul#define RL_IDR4 0x0004 4340516Swpaul#define RL_IDR5 0x0005 4440516Swpaul /* 0006-0007 reserved */ 4540516Swpaul#define RL_MAR0 0x0008 /* Multicast hash table */ 4640516Swpaul#define RL_MAR1 0x0009 4740516Swpaul#define RL_MAR2 0x000A 4840516Swpaul#define RL_MAR3 0x000B 4940516Swpaul#define RL_MAR4 0x000C 5040516Swpaul#define RL_MAR5 0x000D 5140516Swpaul#define RL_MAR6 0x000E 5240516Swpaul#define RL_MAR7 0x000F 5340516Swpaul 5440516Swpaul#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */ 5540516Swpaul#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */ 5640516Swpaul#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */ 5740516Swpaul#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */ 5840516Swpaul 5940516Swpaul#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */ 6040516Swpaul#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */ 6140516Swpaul#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */ 6240516Swpaul#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */ 6340516Swpaul 6440516Swpaul#define RL_RXADDR 0x0030 /* RX ring start address */ 6540516Swpaul#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */ 6640516Swpaul#define RL_RX_EARLY_STAT 0x0036 /* RX early status */ 6740516Swpaul#define RL_COMMAND 0x0037 /* command register */ 6840516Swpaul#define RL_CURRXADDR 0x0038 /* current address of packet read */ 6940516Swpaul#define RL_CURRXBUF 0x003A /* current RX buffer address */ 7040516Swpaul#define RL_IMR 0x003C /* interrupt mask register */ 7140516Swpaul#define RL_ISR 0x003E /* interrupt status register */ 7240516Swpaul#define RL_TXCFG 0x0040 /* transmit config */ 7340516Swpaul#define RL_RXCFG 0x0044 /* receive config */ 7440516Swpaul#define RL_TIMERCNT 0x0048 /* timer count register */ 7540516Swpaul#define RL_MISSEDPKT 0x004C /* missed packet counter */ 7640516Swpaul#define RL_EECMD 0x0050 /* EEPROM command register */ 7740516Swpaul#define RL_CFG0 0x0051 /* config register #0 */ 7840516Swpaul#define RL_CFG1 0x0052 /* config register #1 */ 7940516Swpaul /* 0053-0057 reserved */ 8040516Swpaul#define RL_MEDIASTAT 0x0058 /* media status register (8139) */ 8140516Swpaul /* 0059-005A reserved */ 8240516Swpaul#define RL_MII 0x005A /* 8129 chip only */ 8340516Swpaul#define RL_HALTCLK 0x005B 8440516Swpaul#define RL_MULTIINTR 0x005C /* multiple interrupt */ 8540516Swpaul#define RL_PCIREV 0x005E /* PCI revision value */ 8640516Swpaul /* 005F reserved */ 8740516Swpaul#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */ 8840516Swpaul 8940516Swpaul/* Direct PHY access registers only available on 8139 */ 9040516Swpaul#define RL_BMCR 0x0062 /* PHY basic mode control */ 9140516Swpaul#define RL_BMSR 0x0064 /* PHY basic mode status */ 9240516Swpaul#define RL_ANAR 0x0066 /* PHY autoneg advert */ 9340516Swpaul#define RL_LPAR 0x0068 /* PHY link partner ability */ 9440516Swpaul#define RL_ANER 0x006A /* PHY autoneg expansion */ 9540516Swpaul 9640516Swpaul#define RL_DISCCNT 0x006C /* disconnect counter */ 9740516Swpaul#define RL_FALSECAR 0x006E /* false carrier counter */ 9840516Swpaul#define RL_NWAYTST 0x0070 /* NWAY test register */ 9940516Swpaul#define RL_RX_ER 0x0072 /* RX_ER counter */ 10040516Swpaul#define RL_CSCFG 0x0074 /* CS configuration register */ 10140516Swpaul 102117388Swpaul/* 103117388Swpaul * When operating in special C+ mode, some of the registers in an 104117388Swpaul * 8139C+ chip have different definitions. These are also used for 105117388Swpaul * the 8169 gigE chip. 106117388Swpaul */ 107117388Swpaul#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */ 108117388Swpaul#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */ 109117388Swpaul#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */ 110117388Swpaul#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */ 111117388Swpaul#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */ 112117388Swpaul#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */ 113117388Swpaul#define RL_TIMERINT 0x0054 /* interrupt on timer expire */ 114117388Swpaul#define RL_TXSTART 0x00D9 /* 8 bits */ 115117388Swpaul#define RL_CPLUS_CMD 0x00E0 /* 16 bits */ 116117388Swpaul#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */ 117117388Swpaul#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */ 118117388Swpaul#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */ 11940516Swpaul 12040516Swpaul/* 121117388Swpaul * Registers specific to the 8169 gigE chip 122117388Swpaul */ 123117388Swpaul#define RL_PHYAR 0x0060 124117388Swpaul#define RL_TBICSR 0x0064 125117388Swpaul#define RL_TBI_ANAR 0x0068 126117388Swpaul#define RL_TBI_LPAR 0x006A 127117388Swpaul#define RL_GMEDIASTAT 0x006C /* 8 bits */ 128117388Swpaul#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 129117388Swpaul#define RL_GTXSTART 0x0038 /* 16 bits */ 130117388Swpaul 131117388Swpaul/* 13240516Swpaul * TX config register bits 13340516Swpaul */ 13440516Swpaul#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 13545633Swpaul#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ 13640516Swpaul#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */ 13745633Swpaul#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */ 13845633Swpaul#define RL_TXCFG_IFG 0x03000000 /* interframe gap */ 139117388Swpaul#define RL_TXCFG_HWREV 0x7CC00000 14040516Swpaul 141117388Swpaul#define RL_HWREV_8139 0x60000000 142117388Swpaul#define RL_HWREV_8139A 0x70000000 143117388Swpaul#define RL_HWREV_8139AG 0x70800000 144117388Swpaul#define RL_HWREV_8139B 0x78000000 145117388Swpaul#define RL_HWREV_8130 0x7C000000 146117388Swpaul#define RL_HWREV_8139C 0x74000000 147117388Swpaul#define RL_HWREV_8139D 0x74400000 148117388Swpaul#define RL_HWREV_8139CPLUS 0x74800000 149117388Swpaul 15045633Swpaul#define RL_TXDMA_16BYTES 0x00000000 15145633Swpaul#define RL_TXDMA_32BYTES 0x00000100 15245633Swpaul#define RL_TXDMA_64BYTES 0x00000200 15345633Swpaul#define RL_TXDMA_128BYTES 0x00000300 15445633Swpaul#define RL_TXDMA_256BYTES 0x00000400 15545633Swpaul#define RL_TXDMA_512BYTES 0x00000500 15645633Swpaul#define RL_TXDMA_1024BYTES 0x00000600 15745633Swpaul#define RL_TXDMA_2048BYTES 0x00000700 15845633Swpaul 15940516Swpaul/* 16040516Swpaul * Transmit descriptor status register bits. 16140516Swpaul */ 16240516Swpaul#define RL_TXSTAT_LENMASK 0x00001FFF 16340516Swpaul#define RL_TXSTAT_OWN 0x00002000 16440516Swpaul#define RL_TXSTAT_TX_UNDERRUN 0x00004000 16540516Swpaul#define RL_TXSTAT_TX_OK 0x00008000 16640516Swpaul#define RL_TXSTAT_EARLY_THRESH 0x003F0000 16740516Swpaul#define RL_TXSTAT_COLLCNT 0x0F000000 16840516Swpaul#define RL_TXSTAT_CARR_HBEAT 0x10000000 16940516Swpaul#define RL_TXSTAT_OUTOFWIN 0x20000000 17040516Swpaul#define RL_TXSTAT_TXABRT 0x40000000 17140516Swpaul#define RL_TXSTAT_CARRLOSS 0x80000000 17240516Swpaul 17340516Swpaul/* 17440516Swpaul * Interrupt status register bits. 17540516Swpaul */ 17640516Swpaul#define RL_ISR_RX_OK 0x0001 17740516Swpaul#define RL_ISR_RX_ERR 0x0002 17840516Swpaul#define RL_ISR_TX_OK 0x0004 17940516Swpaul#define RL_ISR_TX_ERR 0x0008 18040516Swpaul#define RL_ISR_RX_OVERRUN 0x0010 18140516Swpaul#define RL_ISR_PKT_UNDERRUN 0x0020 18240516Swpaul#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */ 183117388Swpaul#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */ 184117388Swpaul#define RL_ISR_SWI 0x0100 /* C+ only */ 185117388Swpaul#define RL_ISR_CABLE_LEN_CHGD 0x2000 18640516Swpaul#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */ 187117388Swpaul#define RL_ISR_TIMEOUT_EXPIRED 0x4000 18840516Swpaul#define RL_ISR_SYSTEM_ERR 0x8000 18940516Swpaul 19040516Swpaul#define RL_INTRS \ 19140516Swpaul (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 19240516Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 19340516Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR) 19440516Swpaul 195117388Swpaul#define RL_INTRS_CPLUS \ 196117388Swpaul (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \ 197117388Swpaul RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \ 198117388Swpaul RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED) 199117388Swpaul 20040516Swpaul/* 20140516Swpaul * Media status register. (8139 only) 20240516Swpaul */ 20340516Swpaul#define RL_MEDIASTAT_RXPAUSE 0x01 20440516Swpaul#define RL_MEDIASTAT_TXPAUSE 0x02 20540516Swpaul#define RL_MEDIASTAT_LINK 0x04 20640516Swpaul#define RL_MEDIASTAT_SPEED10 0x08 20740516Swpaul#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */ 20840516Swpaul#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */ 20940516Swpaul 21040516Swpaul/* 21140516Swpaul * Receive config register. 21240516Swpaul */ 21340516Swpaul#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */ 21440516Swpaul#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */ 21540516Swpaul#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */ 21640516Swpaul#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */ 21740516Swpaul#define RL_RXCFG_RX_RUNT 0x00000010 21840516Swpaul#define RL_RXCFG_RX_ERRPKT 0x00000020 21940516Swpaul#define RL_RXCFG_WRAP 0x00000080 22045633Swpaul#define RL_RXCFG_MAXDMA 0x00000700 22145633Swpaul#define RL_RXCFG_BUFSZ 0x00001800 22245633Swpaul#define RL_RXCFG_FIFOTHRESH 0x0000E000 22345633Swpaul#define RL_RXCFG_EARLYTHRESH 0x07000000 22440516Swpaul 22545633Swpaul#define RL_RXDMA_16BYTES 0x00000000 22645633Swpaul#define RL_RXDMA_32BYTES 0x00000100 22745633Swpaul#define RL_RXDMA_64BYTES 0x00000200 22845633Swpaul#define RL_RXDMA_128BYTES 0x00000300 22945633Swpaul#define RL_RXDMA_256BYTES 0x00000400 23045633Swpaul#define RL_RXDMA_512BYTES 0x00000500 23145633Swpaul#define RL_RXDMA_1024BYTES 0x00000600 23245633Swpaul#define RL_RXDMA_UNLIMITED 0x00000700 23345633Swpaul 23440516Swpaul#define RL_RXBUF_8 0x00000000 23540516Swpaul#define RL_RXBUF_16 0x00000800 23640516Swpaul#define RL_RXBUF_32 0x00001000 23745633Swpaul#define RL_RXBUF_64 0x00001800 23840516Swpaul 23945633Swpaul#define RL_RXFIFO_16BYTES 0x00000000 24045633Swpaul#define RL_RXFIFO_32BYTES 0x00002000 24145633Swpaul#define RL_RXFIFO_64BYTES 0x00004000 24245633Swpaul#define RL_RXFIFO_128BYTES 0x00006000 24345633Swpaul#define RL_RXFIFO_256BYTES 0x00008000 24445633Swpaul#define RL_RXFIFO_512BYTES 0x0000A000 24545633Swpaul#define RL_RXFIFO_1024BYTES 0x0000C000 24645633Swpaul#define RL_RXFIFO_NOTHRESH 0x0000E000 24745633Swpaul 24840516Swpaul/* 24940516Swpaul * Bits in RX status header (included with RX'ed packet 25040516Swpaul * in ring buffer). 25140516Swpaul */ 25240516Swpaul#define RL_RXSTAT_RXOK 0x00000001 25340516Swpaul#define RL_RXSTAT_ALIGNERR 0x00000002 25440516Swpaul#define RL_RXSTAT_CRCERR 0x00000004 25540516Swpaul#define RL_RXSTAT_GIANT 0x00000008 25640516Swpaul#define RL_RXSTAT_RUNT 0x00000010 25740516Swpaul#define RL_RXSTAT_BADSYM 0x00000020 25840516Swpaul#define RL_RXSTAT_BROAD 0x00002000 25940516Swpaul#define RL_RXSTAT_INDIV 0x00004000 26040516Swpaul#define RL_RXSTAT_MULTI 0x00008000 26140516Swpaul#define RL_RXSTAT_LENMASK 0xFFFF0000 26240516Swpaul 26340516Swpaul#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */ 26440516Swpaul/* 26540516Swpaul * Command register. 26640516Swpaul */ 26740516Swpaul#define RL_CMD_EMPTY_RXBUF 0x0001 26840516Swpaul#define RL_CMD_TX_ENB 0x0004 26940516Swpaul#define RL_CMD_RX_ENB 0x0008 27040516Swpaul#define RL_CMD_RESET 0x0010 27140516Swpaul 27240516Swpaul/* 27340516Swpaul * EEPROM control register 27440516Swpaul */ 27540516Swpaul#define RL_EE_DATAOUT 0x01 /* Data out */ 27640516Swpaul#define RL_EE_DATAIN 0x02 /* Data in */ 27740516Swpaul#define RL_EE_CLK 0x04 /* clock */ 27840516Swpaul#define RL_EE_SEL 0x08 /* chip select */ 27940516Swpaul#define RL_EE_MODE (0x40|0x80) 28040516Swpaul 28140516Swpaul#define RL_EEMODE_OFF 0x00 28240516Swpaul#define RL_EEMODE_AUTOLOAD 0x40 28340516Swpaul#define RL_EEMODE_PROGRAM 0x80 28440516Swpaul#define RL_EEMODE_WRITECFG (0x80|0x40) 28540516Swpaul 28640516Swpaul/* 9346 EEPROM commands */ 28740516Swpaul#define RL_EECMD_WRITE 0x140 28867931Swpaul#define RL_EECMD_READ_6BIT 0x180 28967931Swpaul#define RL_EECMD_READ_8BIT 0x600 29040516Swpaul#define RL_EECMD_ERASE 0x1c0 29140516Swpaul 29240516Swpaul#define RL_EE_ID 0x00 29340516Swpaul#define RL_EE_PCI_VID 0x01 29440516Swpaul#define RL_EE_PCI_DID 0x02 29540516Swpaul/* Location of station address inside EEPROM */ 29640516Swpaul#define RL_EE_EADDR 0x07 29740516Swpaul 29840516Swpaul/* 29940516Swpaul * MII register (8129 only) 30040516Swpaul */ 30140516Swpaul#define RL_MII_CLK 0x01 30240516Swpaul#define RL_MII_DATAIN 0x02 30340516Swpaul#define RL_MII_DATAOUT 0x04 30440516Swpaul#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */ 30540516Swpaul 30640516Swpaul/* 30740516Swpaul * Config 0 register 30840516Swpaul */ 30940516Swpaul#define RL_CFG0_ROM0 0x01 31040516Swpaul#define RL_CFG0_ROM1 0x02 31140516Swpaul#define RL_CFG0_ROM2 0x04 31240516Swpaul#define RL_CFG0_PL0 0x08 31340516Swpaul#define RL_CFG0_PL1 0x10 31440516Swpaul#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */ 31540516Swpaul#define RL_CFG0_PCS 0x40 31640516Swpaul#define RL_CFG0_SCR 0x80 31740516Swpaul 31840516Swpaul/* 31940516Swpaul * Config 1 register 32040516Swpaul */ 32140516Swpaul#define RL_CFG1_PWRDWN 0x01 32240516Swpaul#define RL_CFG1_SLEEP 0x02 32340516Swpaul#define RL_CFG1_IOMAP 0x04 32440516Swpaul#define RL_CFG1_MEMMAP 0x08 32540516Swpaul#define RL_CFG1_RSVD 0x10 32640516Swpaul#define RL_CFG1_DRVLOAD 0x20 32740516Swpaul#define RL_CFG1_LED0 0x40 32840516Swpaul#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */ 32940516Swpaul#define RL_CFG1_LED1 0x80 33040516Swpaul 33140516Swpaul/* 332117388Swpaul * 8139C+ register definitions 333117388Swpaul */ 334117388Swpaul 335117388Swpaul/* RL_DUMPSTATS_LO register */ 336117388Swpaul 337117388Swpaul#define RL_DUMPSTATS_START 0x00000008 338117388Swpaul 339117388Swpaul/* Transmit start register */ 340117388Swpaul 341117388Swpaul#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */ 342117388Swpaul#define RL_TXSTART_START 0x40 /* start normal queue transmit */ 343117388Swpaul#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */ 344117388Swpaul 345117388Swpaul/* C+ mode command register */ 346117388Swpaul 347117388Swpaul#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */ 348117388Swpaul#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */ 349117388Swpaul#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */ 350117388Swpaul#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */ 351117388Swpaul#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */ 352117388Swpaul#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */ 353117388Swpaul 354117388Swpaul/* C+ early transmit threshold */ 355117388Swpaul 356117388Swpaul#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */ 357117388Swpaul 358117388Swpaul/* 359117388Swpaul * Gigabit PHY access register (8169 only) 360117388Swpaul */ 361117388Swpaul 362117388Swpaul#define RL_PHYAR_PHYDATA 0x0000FFFF 363117388Swpaul#define RL_PHYAR_PHYREG 0x001F0000 364117388Swpaul#define RL_PHYAR_BUSY 0x80000000 365117388Swpaul 366117388Swpaul/* 367117388Swpaul * Gigabit media status (8169 only) 368117388Swpaul */ 369117388Swpaul#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */ 370117388Swpaul#define RL_GMEDIASTAT_LINK 0x02 /* link up */ 371117388Swpaul#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */ 372117388Swpaul#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */ 373117388Swpaul#define RL_GMEDIASTAT_1000MPS 0x10 /* gigE link */ 374117388Swpaul#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */ 375117388Swpaul#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */ 376117388Swpaul#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */ 377117388Swpaul 378117388Swpaul/* 37940516Swpaul * The RealTek doesn't use a fragment-based descriptor mechanism. 38040516Swpaul * Instead, there are only four register sets, each or which represents 38140516Swpaul * one 'descriptor.' Basically, each TX descriptor is just a contiguous 38240516Swpaul * packet buffer (32-bit aligned!) and we place the buffer addresses in 38340516Swpaul * the registers so the chip knows where they are. 38440516Swpaul * 38540516Swpaul * We can sort of kludge together the same kind of buffer management 38640516Swpaul * used in previous drivers, but we have to do buffer copies almost all 38740516Swpaul * the time, so it doesn't really buy us much. 38840516Swpaul * 38940516Swpaul * For reception, there's just one large buffer where the chip stores 39040516Swpaul * all received packets. 39140516Swpaul */ 39240516Swpaul 39340516Swpaul#define RL_RX_BUF_SZ RL_RXBUF_64 39440516Swpaul#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13)) 39540516Swpaul#define RL_TX_LIST_CNT 4 39640516Swpaul#define RL_MIN_FRAMELEN 60 39752426Swpaul#define RL_TXTHRESH(x) ((x) << 11) 39852426Swpaul#define RL_TX_THRESH_INIT 96 39948056Swpaul#define RL_RX_FIFOTHRESH RL_RXFIFO_256BYTES 40081713Swpaul#define RL_RX_MAXDMA RL_RXDMA_1024BYTES /*RL_RXDMA_UNLIMITED*/ 40150703Swpaul#define RL_TX_MAXDMA RL_TXDMA_2048BYTES 40240516Swpaul 40345633Swpaul#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ) 40445633Swpaul#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA) 40540516Swpaul 40648028Swpaul#define RL_ETHER_ALIGN 2 40748028Swpaul 40840516Swpaulstruct rl_chain_data { 40940516Swpaul u_int16_t cur_rx; 41040516Swpaul caddr_t rl_rx_buf; 41148028Swpaul caddr_t rl_rx_buf_ptr; 41281713Swpaul bus_dmamap_t rl_rx_dmamap; 41340516Swpaul 41445633Swpaul struct mbuf *rl_tx_chain[RL_TX_LIST_CNT]; 41581713Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT]; 41645633Swpaul u_int8_t last_tx; 41745633Swpaul u_int8_t cur_tx; 41840516Swpaul}; 41940516Swpaul 42045633Swpaul#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT) 42145633Swpaul#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0) 42245633Swpaul#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0) 42345633Swpaul#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx]) 42481713Swpaul#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx]) 42545633Swpaul#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0) 42645633Swpaul#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0) 42745633Swpaul#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx]) 42881713Swpaul#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx]) 42945633Swpaul 43040516Swpaulstruct rl_type { 43140516Swpaul u_int16_t rl_vid; 43240516Swpaul u_int16_t rl_did; 433117388Swpaul int rl_basetype; 43440516Swpaul char *rl_name; 43540516Swpaul}; 43640516Swpaul 437117388Swpaulstruct rl_hwrev { 438117388Swpaul u_int32_t rl_rev; 439117388Swpaul int rl_type; 440117388Swpaul char *rl_desc; 441117388Swpaul}; 442117388Swpaul 44340516Swpaulstruct rl_mii_frame { 44440516Swpaul u_int8_t mii_stdelim; 44540516Swpaul u_int8_t mii_opcode; 44640516Swpaul u_int8_t mii_phyaddr; 44740516Swpaul u_int8_t mii_regaddr; 44840516Swpaul u_int8_t mii_turnaround; 44940516Swpaul u_int16_t mii_data; 45040516Swpaul}; 45140516Swpaul 45240516Swpaul/* 45340516Swpaul * MII constants 45440516Swpaul */ 45540516Swpaul#define RL_MII_STARTDELIM 0x01 45640516Swpaul#define RL_MII_READOP 0x02 45740516Swpaul#define RL_MII_WRITEOP 0x01 45840516Swpaul#define RL_MII_TURNAROUND 0x02 45940516Swpaul 46040516Swpaul#define RL_8129 1 46140516Swpaul#define RL_8139 2 462117388Swpaul#define RL_8139CPLUS 3 463117388Swpaul#define RL_8169 4 46440516Swpaul 465117388Swpaul#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \ 466117388Swpaul (x)->rl_type == RL_8169) 467117388Swpaul 468117388Swpaul/* 469117388Swpaul * The 8139C+ and 8160 gigE chips support descriptor-based TX 470117388Swpaul * and RX. In fact, they even support TCP large send. Descriptors 471117388Swpaul * must be allocated in contiguous blocks that are aligned on a 472117388Swpaul * 256-byte boundary. The rings can hold a maximum of 64 descriptors. 473117388Swpaul */ 474117388Swpaul 475117388Swpaul/* 476117388Swpaul * RX/TX descriptor definition. When large send mode is enabled, the 477117388Swpaul * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and 478117388Swpaul * the checksum offload bits are disabled. The structure layout is 479117388Swpaul * the same for RX and TX descriptors 480117388Swpaul */ 481117388Swpaul 482117388Swpaulstruct rl_desc { 483117388Swpaul u_int32_t rl_cmdstat; 484117388Swpaul u_int32_t rl_vlanctl; 485117388Swpaul u_int32_t rl_bufaddr_lo; 486117388Swpaul u_int32_t rl_bufaddr_hi; 487117388Swpaul}; 488117388Swpaul 489117388Swpaul#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF 490117388Swpaul#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */ 491117388Swpaul#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */ 492117388Swpaul#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */ 493117388Swpaul#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */ 494117388Swpaul#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */ 495117388Swpaul#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */ 496117388Swpaul#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */ 497117388Swpaul#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */ 498117388Swpaul#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */ 499117388Swpaul 500117388Swpaul#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */ 501117388Swpaul#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 502117388Swpaul 503117388Swpaul/* 504117388Swpaul * Error bits are valid only on the last descriptor of a frame 505117388Swpaul * (i.e. RL_TDESC_CMD_EOF == 1) 506117388Swpaul */ 507117388Swpaul 508117388Swpaul#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */ 509117388Swpaul#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */ 510117388Swpaul#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */ 511117388Swpaul#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */ 512117388Swpaul#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */ 513117388Swpaul#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */ 514117388Swpaul#define RL_TDESC_STAT_OWN 0x80000000 515117388Swpaul 516117388Swpaul/* 517117388Swpaul * RX descriptor cmd/vlan definitions 518117388Swpaul */ 519117388Swpaul 520117388Swpaul#define RL_RDESC_CMD_EOR 0x40000000 521117388Swpaul#define RL_RDESC_CMD_OWN 0x80000000 522117388Swpaul#define RL_RDESC_CMD_BUFLEN 0x00001FFF 523117388Swpaul 524117388Swpaul#define RL_RDESC_STAT_OWN 0x80000000 525117388Swpaul#define RL_RDESC_STAT_EOR 0x40000000 526117388Swpaul#define RL_RDESC_STAT_SOF 0x20000000 527117388Swpaul#define RL_RDESC_STAT_EOF 0x10000000 528117388Swpaul#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */ 529117388Swpaul#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */ 530117388Swpaul#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */ 531117388Swpaul#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */ 532117388Swpaul#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */ 533117388Swpaul#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */ 534117388Swpaul#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */ 535117388Swpaul#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */ 536117388Swpaul#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */ 537117388Swpaul#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */ 538117388Swpaul#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */ 539117388Swpaul#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */ 540117388Swpaul#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */ 541117388Swpaul#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */ 542117388Swpaul#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */ 543117388Swpaul 544117388Swpaul#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available 545117388Swpaul (rl_vlandata valid)*/ 546117388Swpaul#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */ 547117388Swpaul 548117388Swpaul#define RL_PROTOID_NONIP 0x00000000 549117388Swpaul#define RL_PROTOID_TCPIP 0x00010000 550117388Swpaul#define RL_PROTOID_UDPIP 0x00020000 551117388Swpaul#define RL_PROTOID_IP 0x00030000 552117388Swpaul#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 553117388Swpaul RL_PROTOID_TCPIP) 554117388Swpaul#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \ 555117388Swpaul RL_PROTOID_UDPIP) 556117388Swpaul 557117388Swpaul/* 558117388Swpaul * Statistics counter structure (8139C+ and 8169 only) 559117388Swpaul */ 560117388Swpaulstruct rl_stats { 561117388Swpaul u_int32_t rl_tx_pkts_lo; 562117388Swpaul u_int32_t rl_tx_pkts_hi; 563117388Swpaul u_int32_t rl_tx_errs_lo; 564117388Swpaul u_int32_t rl_tx_errs_hi; 565117388Swpaul u_int32_t rl_tx_errs; 566117388Swpaul u_int16_t rl_missed_pkts; 567117388Swpaul u_int16_t rl_rx_framealign_errs; 568117388Swpaul u_int32_t rl_tx_onecoll; 569117388Swpaul u_int32_t rl_tx_multicolls; 570117388Swpaul u_int32_t rl_rx_ucasts_hi; 571117388Swpaul u_int32_t rl_rx_ucasts_lo; 572117388Swpaul u_int32_t rl_rx_bcasts_lo; 573117388Swpaul u_int32_t rl_rx_bcasts_hi; 574117388Swpaul u_int32_t rl_rx_mcasts; 575117388Swpaul u_int16_t rl_tx_aborts; 576117388Swpaul u_int16_t rl_rx_underruns; 577117388Swpaul}; 578117388Swpaul 579117388Swpaul#define RL_RX_DESC_CNT 64 580117388Swpaul#define RL_TX_DESC_CNT 64 581117388Swpaul#define RL_RX_LIST_SZ (RL_RX_DESC_CNT * sizeof(struct rl_desc)) 582117388Swpaul#define RL_TX_LIST_SZ (RL_TX_DESC_CNT * sizeof(struct rl_desc)) 583117388Swpaul#define RL_RING_ALIGN 256 584117388Swpaul#define RL_IFQ_MAXLEN 512 585117388Swpaul#define RL_DESC_INC(x) (x = (x + 1) % RL_TX_DESC_CNT) 586117388Swpaul#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN) 587117388Swpaul#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & \ 588117388Swpaul RL_RDESC_STAT_FRAGLEN) 589117388Swpaul#define RL_PKTSZ(x) ((x) >> 3) 590117388Swpaul 591117388Swpaulstruct rl_softc; 592117388Swpaul 593117388Swpaulstruct rl_dmaload_arg { 594117388Swpaul struct rl_softc *sc; 595117388Swpaul int rl_idx; 596117388Swpaul int rl_maxsegs; 597117388Swpaul struct rl_desc *rl_ring; 598117388Swpaul}; 599117388Swpaul 600117388Swpaulstruct rl_list_data { 601117388Swpaul struct mbuf *rl_tx_mbuf[RL_TX_DESC_CNT]; 602117388Swpaul struct mbuf *rl_rx_mbuf[RL_TX_DESC_CNT]; 603117388Swpaul int rl_tx_prodidx; 604117388Swpaul int rl_rx_prodidx; 605117388Swpaul int rl_tx_considx; 606117388Swpaul int rl_tx_free; 607117388Swpaul bus_dmamap_t rl_tx_dmamap[RL_TX_DESC_CNT]; 608117388Swpaul bus_dmamap_t rl_rx_dmamap[RL_RX_DESC_CNT]; 609117388Swpaul bus_dma_tag_t rl_mtag; /* mbuf mapping tag */ 610117388Swpaul bus_dma_tag_t rl_stag; /* stats mapping tag */ 611117388Swpaul bus_dmamap_t rl_smap; /* stats map */ 612117388Swpaul struct rl_stats *rl_stats; 613117388Swpaul u_int32_t rl_stats_addr; 614117388Swpaul bus_dma_tag_t rl_rx_list_tag; 615117388Swpaul bus_dmamap_t rl_rx_list_map; 616117388Swpaul struct rl_desc *rl_rx_list; 617117388Swpaul u_int32_t rl_rx_list_addr; 618117388Swpaul bus_dma_tag_t rl_tx_list_tag; 619117388Swpaul bus_dmamap_t rl_tx_list_map; 620117388Swpaul struct rl_desc *rl_tx_list; 621117388Swpaul u_int32_t rl_tx_list_addr; 622117388Swpaul}; 623117388Swpaul 62440516Swpaulstruct rl_softc { 62540516Swpaul struct arpcom arpcom; /* interface info */ 62641569Swpaul bus_space_handle_t rl_bhandle; /* bus space handle */ 62741569Swpaul bus_space_tag_t rl_btag; /* bus space tag */ 62850703Swpaul struct resource *rl_res; 62950703Swpaul struct resource *rl_irq; 63050703Swpaul void *rl_intrhand; 63150703Swpaul device_t rl_miibus; 63281713Swpaul bus_dma_tag_t rl_parent_tag; 63381713Swpaul bus_dma_tag_t rl_tag; 63440516Swpaul u_int8_t rl_unit; /* interface number */ 63540516Swpaul u_int8_t rl_type; 63667931Swpaul int rl_eecmd_read; 63740516Swpaul u_int8_t rl_stats_no_timeout; 63852426Swpaul int rl_txthresh; 63940516Swpaul struct rl_chain_data rl_cdata; 640117388Swpaul struct rl_list_data rl_ldata; 64150703Swpaul struct callout_handle rl_stat_ch; 64267087Swpaul struct mtx rl_mtx; 64386822Siwasaki int suspended; /* 0 = normal 1 = suspended */ 64494883Sluigi#ifdef DEVICE_POLLING 64594883Sluigi int rxcycles; 64694883Sluigi#endif 64786822Siwasaki 64886822Siwasaki u_int32_t saved_maps[5]; /* pci data */ 64986822Siwasaki u_int32_t saved_biosaddr; 65086822Siwasaki u_int8_t saved_intline; 65186822Siwasaki u_int8_t saved_cachelnsz; 65286822Siwasaki u_int8_t saved_lattimer; 65340516Swpaul}; 65440516Swpaul 65572200Sbmilekic#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 65672200Sbmilekic#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 65767087Swpaul 65840516Swpaul/* 65940516Swpaul * register space access macros 66040516Swpaul */ 66140516Swpaul#define CSR_WRITE_4(sc, reg, val) \ 66241569Swpaul bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val) 66340516Swpaul#define CSR_WRITE_2(sc, reg, val) \ 66441569Swpaul bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val) 66540516Swpaul#define CSR_WRITE_1(sc, reg, val) \ 66641569Swpaul bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val) 66740516Swpaul 66841569Swpaul#define CSR_READ_4(sc, reg) \ 66941569Swpaul bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg) 67041569Swpaul#define CSR_READ_2(sc, reg) \ 67141569Swpaul bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg) 67241569Swpaul#define CSR_READ_1(sc, reg) \ 67341569Swpaul bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg) 67440516Swpaul 67540516Swpaul#define RL_TIMEOUT 1000 67640516Swpaul 67740516Swpaul/* 67840516Swpaul * General constants that are fun to know. 67940516Swpaul * 68040516Swpaul * RealTek PCI vendor ID 68140516Swpaul */ 68240516Swpaul#define RT_VENDORID 0x10EC 68340516Swpaul 68440516Swpaul/* 68540516Swpaul * RealTek chip device IDs. 68640516Swpaul */ 68740516Swpaul#define RT_DEVICEID_8129 0x8129 68867771Swpaul#define RT_DEVICEID_8138 0x8138 68940516Swpaul#define RT_DEVICEID_8139 0x8139 690117388Swpaul#define RT_DEVICEID_8169 0x8169 69140516Swpaul 692117388Swpaul#define RT_REVID_8139CPLUS 0x20 693117388Swpaul 69440516Swpaul/* 69544238Swpaul * Accton PCI vendor ID 69644238Swpaul */ 69744238Swpaul#define ACCTON_VENDORID 0x1113 69844238Swpaul 69944238Swpaul/* 70041243Swpaul * Accton MPX 5030/5038 device ID. 70141243Swpaul */ 70241243Swpaul#define ACCTON_DEVICEID_5030 0x1211 70341243Swpaul 70441243Swpaul/* 70594400Swpaul * Nortel PCI vendor ID 70694400Swpaul */ 70794400Swpaul#define NORTEL_VENDORID 0x126C 70894400Swpaul 70994400Swpaul/* 71044238Swpaul * Delta Electronics Vendor ID. 71144238Swpaul */ 71244238Swpaul#define DELTA_VENDORID 0x1500 71344238Swpaul 71444238Swpaul/* 71544238Swpaul * Delta device IDs. 71644238Swpaul */ 71744238Swpaul#define DELTA_DEVICEID_8139 0x1360 71844238Swpaul 71944238Swpaul/* 72044238Swpaul * Addtron vendor ID. 72144238Swpaul */ 72244238Swpaul#define ADDTRON_VENDORID 0x4033 72344238Swpaul 72444238Swpaul/* 72544238Swpaul * Addtron device IDs. 72644238Swpaul */ 72744238Swpaul#define ADDTRON_DEVICEID_8139 0x1360 72844238Swpaul 72944238Swpaul/* 73072813Swpaul * D-Link vendor ID. 73172813Swpaul */ 73272813Swpaul#define DLINK_VENDORID 0x1186 73372813Swpaul 73472813Swpaul/* 73572813Swpaul * D-Link DFE-530TX+ device ID 73672813Swpaul */ 73772813Swpaul#define DLINK_DEVICEID_530TXPLUS 0x1300 73872813Swpaul 73972813Swpaul/* 74096112Sjhb * D-Link DFE-690TXD device ID 74196112Sjhb */ 74296112Sjhb#define DLINK_DEVICEID_690TXD 0x1340 74396112Sjhb 74496112Sjhb/* 745103020Siwasaki * Corega K.K vendor ID 746103020Siwasaki */ 747103020Siwasaki#define COREGA_VENDORID 0x1259 748103020Siwasaki 749103020Siwasaki/* 750109095Ssanpei * Corega FEther CB-TXD device ID 751103020Siwasaki */ 752109095Ssanpei#define COREGA_DEVICEID_FETHERCBTXD 0xa117 753103020Siwasaki 754103020Siwasaki/* 755109095Ssanpei * Corega FEtherII CB-TXD device ID 756109095Ssanpei */ 757109095Ssanpei#define COREGA_DEVICEID_FETHERIICBTXD 0xa11e 758109095Ssanpei 759111381Sdan/* 760111381Sdan * Peppercon vendor ID 761111381Sdan */ 762111381Sdan#define PEPPERCON_VENDORID 0x1743 763109095Ssanpei 764111381Sdan/* 765111381Sdan * Peppercon ROL-F device ID 766111381Sdan */ 767111381Sdan#define PEPPERCON_DEVICEID_ROLF 0x8139 768109095Ssanpei 769109095Ssanpei/* 770112379Ssanpei * Planex Communications, Inc. vendor ID 771112379Ssanpei */ 772117388Swpaul#define PLANEX_VENDORID 0x14ea 773112379Ssanpei 774112379Ssanpei/* 775112379Ssanpei * Planex FNW-3800-TX device ID 776112379Ssanpei */ 777117388Swpaul#define PLANEX_DEVICEID_FNW3800TX 0xab07 778112379Ssanpei 779112379Ssanpei/* 780117388Swpaul * LevelOne vendor ID 781117388Swpaul */ 782117388Swpaul#define LEVEL1_VENDORID 0x018A 783117388Swpaul 784117388Swpaul/* 785117388Swpaul * LevelOne FPC-0106TX devide ID 786117388Swpaul */ 787117388Swpaul#define LEVEL1_DEVICEID_FPC0106TX 0x0106 788117388Swpaul 789117388Swpaul/* 790117388Swpaul * Compaq vendor ID 791117388Swpaul */ 792117388Swpaul#define CP_VENDORID 0x021B 793117388Swpaul 794117388Swpaul/* 795117388Swpaul * Edimax vendor ID 796117388Swpaul */ 797117388Swpaul#define EDIMAX_VENDORID 0x13D1 798117388Swpaul 799117388Swpaul/* 800117388Swpaul * Edimax EP-4103DL cardbus device ID 801117388Swpaul */ 802117388Swpaul#define EDIMAX_DEVICEID_EP4103DL 0xAB06 803117388Swpaul 804117388Swpaul/* 80540516Swpaul * PCI low memory base and low I/O base register, and 80650703Swpaul * other PCI registers. 80740516Swpaul */ 80840516Swpaul 80940516Swpaul#define RL_PCI_VENDOR_ID 0x00 81040516Swpaul#define RL_PCI_DEVICE_ID 0x02 81140516Swpaul#define RL_PCI_COMMAND 0x04 81240516Swpaul#define RL_PCI_STATUS 0x06 81340516Swpaul#define RL_PCI_CLASSCODE 0x09 81440516Swpaul#define RL_PCI_LATENCY_TIMER 0x0D 81540516Swpaul#define RL_PCI_HEADER_TYPE 0x0E 81640516Swpaul#define RL_PCI_LOIO 0x10 81740516Swpaul#define RL_PCI_LOMEM 0x14 81840516Swpaul#define RL_PCI_BIOSROM 0x30 81940516Swpaul#define RL_PCI_INTLINE 0x3C 82040516Swpaul#define RL_PCI_INTPIN 0x3D 82140516Swpaul#define RL_PCI_MINGNT 0x3E 82240516Swpaul#define RL_PCI_MINLAT 0x0F 82340516Swpaul#define RL_PCI_RESETOPT 0x48 82440516Swpaul#define RL_PCI_EEPROM_DATA 0x4C 82540516Swpaul 82650097Swpaul#define RL_PCI_CAPID 0x50 /* 8 bits */ 82750097Swpaul#define RL_PCI_NEXTPTR 0x51 /* 8 bits */ 82850097Swpaul#define RL_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 82950097Swpaul#define RL_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 83040516Swpaul 83140516Swpaul#define RL_PSTATE_MASK 0x0003 83240516Swpaul#define RL_PSTATE_D0 0x0000 83340516Swpaul#define RL_PSTATE_D1 0x0002 83440516Swpaul#define RL_PSTATE_D2 0x0002 83540516Swpaul#define RL_PSTATE_D3 0x0003 83640516Swpaul#define RL_PME_EN 0x0010 83740516Swpaul#define RL_PME_STATUS 0x8000 838