en_port.c revision 219820
1/* 2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 * 32 */ 33 34 35#include "mlx4_en.h" 36 37#include <linux/if_vlan.h> 38 39#include <linux/mlx4/device.h> 40#include <linux/mlx4/cmd.h> 41 42 43int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, 44 u64 mac, u64 clear, u8 mode) 45{ 46 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode, 47 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B); 48} 49 50int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, u32 *vlans) 51{ 52 struct mlx4_cmd_mailbox *mailbox; 53 struct mlx4_set_vlan_fltr_mbox *filter; 54 int i; 55 int err = 0; 56 57 mailbox = mlx4_alloc_cmd_mailbox(dev); 58 if (IS_ERR(mailbox)) 59 return PTR_ERR(mailbox); 60 61 filter = mailbox->buf; 62 memset(filter, 0, sizeof *filter); 63 if (vlans) 64 for (i = 0; i < VLAN_FLTR_SIZE; i ++) 65 filter->entry[i] = cpu_to_be32(vlans[i]); 66 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_VLAN_FLTR, 67 MLX4_CMD_TIME_CLASS_B); 68 mlx4_free_cmd_mailbox(dev, mailbox); 69 return err; 70} 71 72 73int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, 74 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx) 75{ 76 struct mlx4_cmd_mailbox *mailbox; 77 struct mlx4_set_port_general_context *context; 78 int err; 79 u32 in_mod; 80 81 mailbox = mlx4_alloc_cmd_mailbox(dev); 82 if (IS_ERR(mailbox)) 83 return PTR_ERR(mailbox); 84 context = mailbox->buf; 85 memset(context, 0, sizeof *context); 86 87 context->flags = SET_PORT_GEN_ALL_VALID; 88 context->mtu = cpu_to_be16(mtu); 89 context->pptx = (pptx * (!pfctx)) << 7; 90 context->pfctx = pfctx; 91 context->pprx = (pprx * (!pfcrx)) << 7; 92 context->pfcrx = pfcrx; 93 94 in_mod = MLX4_SET_PORT_GENERAL << 8 | port; 95 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, 96 MLX4_CMD_TIME_CLASS_B); 97 98 mlx4_free_cmd_mailbox(dev, mailbox); 99 return err; 100} 101 102int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, 103 u8 promisc) 104{ 105 struct mlx4_cmd_mailbox *mailbox; 106 struct mlx4_set_port_rqp_calc_context *context; 107 int err; 108 u32 in_mod; 109 110 mailbox = mlx4_alloc_cmd_mailbox(dev); 111 if (IS_ERR(mailbox)) 112 return PTR_ERR(mailbox); 113 context = mailbox->buf; 114 memset(context, 0, sizeof *context); 115 116 context->base_qpn = cpu_to_be32(base_qpn); 117 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_EN_SHIFT | base_qpn); 118 context->mcast = cpu_to_be32((dev->caps.mc_promisc_mode << 119 SET_PORT_PROMISC_MODE_SHIFT) | base_qpn); 120 context->intra_no_vlan = 0; 121 context->no_vlan = MLX4_NO_VLAN_IDX; 122 context->intra_vlan_miss = 0; 123 context->vlan_miss = MLX4_VLAN_MISS_IDX; 124 125 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port; 126 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, 127 MLX4_CMD_TIME_CLASS_B); 128 129 mlx4_free_cmd_mailbox(dev, mailbox); 130 return err; 131} 132 133int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port) 134{ 135 struct mlx4_en_query_port_context *qport_context; 136 struct mlx4_en_priv *priv = netdev_priv(mdev->pndev[port]); 137 struct mlx4_en_port_state *state = &priv->port_state; 138 struct mlx4_cmd_mailbox *mailbox; 139 int err; 140 141 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 142 if (IS_ERR(mailbox)) 143 return PTR_ERR(mailbox); 144 memset(mailbox->buf, 0, sizeof(*qport_context)); 145 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0, 146 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B); 147 if (err) 148 goto out; 149 qport_context = mailbox->buf; 150 151 /* This command is always accessed from Ethtool context 152 * already synchronized, no need in locking */ 153 state->link_state = !!(qport_context->link_up & MLX4_EN_LINK_UP_MASK); 154 if ((qport_context->link_speed & MLX4_EN_SPEED_MASK) == 155 MLX4_EN_1G_SPEED) 156 state->link_speed = 1000; 157 else 158 state->link_speed = 10000; 159 state->transciver = qport_context->transceiver; 160 if (be32_to_cpu(qport_context->transceiver_code_hi) & 0x400) 161 state->transciver = 0x80; 162 163out: 164 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 165 return err; 166} 167 168static int read_iboe_counters(struct mlx4_dev *dev, int index, u64 counters[]) 169{ 170 struct mlx4_cmd_mailbox *mailbox; 171 int err; 172 int mode; 173 struct mlx4_counters_ext *ext; 174 struct mlx4_counters *reg; 175 176 mailbox = mlx4_alloc_cmd_mailbox(dev); 177 if (IS_ERR(mailbox)) 178 return -ENOMEM; 179 180 err = mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, 181 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C); 182 if (err) 183 goto out; 184 185 mode = be32_to_cpu(((struct mlx4_counters *)mailbox->buf)->counter_mode) & 0xf; 186 switch (mode) { 187 case 0: 188 reg = mailbox->buf; 189 counters[0] = be64_to_cpu(reg->rx_frames); 190 counters[1] = be64_to_cpu(reg->tx_frames); 191 counters[2] = be64_to_cpu(reg->rx_bytes); 192 counters[3] = be64_to_cpu(reg->tx_bytes); 193 break; 194 case 1: 195 ext = mailbox->buf; 196 counters[0] = be64_to_cpu(ext->rx_uni_frames); 197 counters[1] = be64_to_cpu(ext->tx_uni_frames); 198 counters[2] = be64_to_cpu(ext->rx_uni_bytes); 199 counters[3] = be64_to_cpu(ext->tx_uni_bytes); 200 break; 201 default: 202 err = -EINVAL; 203 } 204 205out: 206 mlx4_free_cmd_mailbox(dev, mailbox); 207 return err; 208} 209 210int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset) 211{ 212 struct mlx4_en_stat_out_mbox *mlx4_en_stats; 213 struct net_device *dev; 214 struct mlx4_en_priv *priv; 215 struct mlx4_cmd_mailbox *mailbox; 216 u64 in_mod = reset << 8 | port; 217 unsigned long oerror; 218 unsigned long ierror; 219 int err; 220 int i; 221 int counter; 222 u64 counters[4]; 223 224 dev = mdev->pndev[port]; 225 priv = netdev_priv(dev); 226 memset(counters, 0, sizeof counters); 227 counter = mlx4_get_iboe_counter(priv->mdev->dev, port); 228 if (counter >= 0) 229 err = read_iboe_counters(priv->mdev->dev, counter, counters); 230 231 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); 232 if (IS_ERR(mailbox)) 233 return PTR_ERR(mailbox); 234 memset(mailbox->buf, 0, sizeof(*mlx4_en_stats)); 235 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, in_mod, 0, 236 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B); 237 if (err) 238 goto out; 239 240 mlx4_en_stats = mailbox->buf; 241 242 spin_lock(&priv->stats_lock); 243 244 oerror = ierror = 0; 245 dev->if_ipackets = counters[0]; 246 dev->if_ibytes = counters[2]; 247 for (i = 0; i < priv->rx_ring_num; i++) { 248 dev->if_ipackets += priv->rx_ring[i].packets; 249 dev->if_ibytes += priv->rx_ring[i].bytes; 250 ierror += priv->rx_ring[i].errors; 251 } 252 dev->if_opackets = counters[1]; 253 dev->if_obytes = counters[3]; 254 for (i = 0; i <= priv->tx_ring_num; i++) { 255 dev->if_opackets += priv->tx_ring[i].packets; 256 dev->if_obytes += priv->tx_ring[i].bytes; 257 oerror += priv->tx_ring[i].errors; 258 } 259 260 dev->if_ierrors = be32_to_cpu(mlx4_en_stats->RDROP) + ierror; 261 dev->if_oerrors = be32_to_cpu(mlx4_en_stats->TDROP) + oerror; 262 dev->if_imcasts = be64_to_cpu(mlx4_en_stats->MCAST_prio_0) + 263 be64_to_cpu(mlx4_en_stats->MCAST_prio_1) + 264 be64_to_cpu(mlx4_en_stats->MCAST_prio_2) + 265 be64_to_cpu(mlx4_en_stats->MCAST_prio_3) + 266 be64_to_cpu(mlx4_en_stats->MCAST_prio_4) + 267 be64_to_cpu(mlx4_en_stats->MCAST_prio_5) + 268 be64_to_cpu(mlx4_en_stats->MCAST_prio_6) + 269 be64_to_cpu(mlx4_en_stats->MCAST_prio_7) + 270 be64_to_cpu(mlx4_en_stats->MCAST_novlan); 271 dev->if_omcasts = be64_to_cpu(mlx4_en_stats->TMCAST_prio_0) + 272 be64_to_cpu(mlx4_en_stats->TMCAST_prio_1) + 273 be64_to_cpu(mlx4_en_stats->TMCAST_prio_2) + 274 be64_to_cpu(mlx4_en_stats->TMCAST_prio_3) + 275 be64_to_cpu(mlx4_en_stats->TMCAST_prio_4) + 276 be64_to_cpu(mlx4_en_stats->TMCAST_prio_5) + 277 be64_to_cpu(mlx4_en_stats->TMCAST_prio_6) + 278 be64_to_cpu(mlx4_en_stats->TMCAST_prio_7) + 279 be64_to_cpu(mlx4_en_stats->TMCAST_novlan); 280 dev->if_collisions = 0; 281 282 priv->pkstats.broadcast = 283 be64_to_cpu(mlx4_en_stats->RBCAST_prio_0) + 284 be64_to_cpu(mlx4_en_stats->RBCAST_prio_1) + 285 be64_to_cpu(mlx4_en_stats->RBCAST_prio_2) + 286 be64_to_cpu(mlx4_en_stats->RBCAST_prio_3) + 287 be64_to_cpu(mlx4_en_stats->RBCAST_prio_4) + 288 be64_to_cpu(mlx4_en_stats->RBCAST_prio_5) + 289 be64_to_cpu(mlx4_en_stats->RBCAST_prio_6) + 290 be64_to_cpu(mlx4_en_stats->RBCAST_prio_7) + 291 be64_to_cpu(mlx4_en_stats->RBCAST_novlan); 292 priv->pkstats.rx_prio[0] = be64_to_cpu(mlx4_en_stats->RTOT_prio_0); 293 priv->pkstats.rx_prio[1] = be64_to_cpu(mlx4_en_stats->RTOT_prio_1); 294 priv->pkstats.rx_prio[2] = be64_to_cpu(mlx4_en_stats->RTOT_prio_2); 295 priv->pkstats.rx_prio[3] = be64_to_cpu(mlx4_en_stats->RTOT_prio_3); 296 priv->pkstats.rx_prio[4] = be64_to_cpu(mlx4_en_stats->RTOT_prio_4); 297 priv->pkstats.rx_prio[5] = be64_to_cpu(mlx4_en_stats->RTOT_prio_5); 298 priv->pkstats.rx_prio[6] = be64_to_cpu(mlx4_en_stats->RTOT_prio_6); 299 priv->pkstats.rx_prio[7] = be64_to_cpu(mlx4_en_stats->RTOT_prio_7); 300 priv->pkstats.tx_prio[0] = be64_to_cpu(mlx4_en_stats->TTOT_prio_0); 301 priv->pkstats.tx_prio[1] = be64_to_cpu(mlx4_en_stats->TTOT_prio_1); 302 priv->pkstats.tx_prio[2] = be64_to_cpu(mlx4_en_stats->TTOT_prio_2); 303 priv->pkstats.tx_prio[3] = be64_to_cpu(mlx4_en_stats->TTOT_prio_3); 304 priv->pkstats.tx_prio[4] = be64_to_cpu(mlx4_en_stats->TTOT_prio_4); 305 priv->pkstats.tx_prio[5] = be64_to_cpu(mlx4_en_stats->TTOT_prio_5); 306 priv->pkstats.tx_prio[6] = be64_to_cpu(mlx4_en_stats->TTOT_prio_6); 307 priv->pkstats.tx_prio[7] = be64_to_cpu(mlx4_en_stats->TTOT_prio_7); 308 spin_unlock(&priv->stats_lock); 309 310out: 311 mlx4_free_cmd_mailbox(mdev->dev, mailbox); 312 return err; 313} 314 315