mpreset.S revision 224110
1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD: head/sys/mips/nlm/mpreset.S 224110 2011-07-16 19:35:44Z jchandra $ 29 * NETLOGIC_BSD */ 30 31#include <machine/asm.h> 32#include <machine/cpu.h> 33#include <machine/cpuregs.h> 34#include <mips/nlm/hal/iomap.h> 35#include <mips/nlm/hal/sys.h> 36#include <mips/nlm/hal/cpucontrol.h> 37 38#include "assym.s" 39 40 .text 41 .set noat 42 .set noreorder 43 .set mips64 44 45VECTOR(XLPResetEntry, unknown) 46 mfc0 t0, MIPS_COP_0_STATUS 47 li t1, 0x80000 48 and t1, t0, t1 49 bnez t1, nmi_handler 50 nop 51 52#ifdef SMP 53 /* Reset entry for secordary cores */ 54 mfc0 t0, MIPS_COP_0_PRID, 1 55 srl t0, t0, 2 /* discard thread id */ 56 andi t0, t0, 0x7 /* core id */ 57 li t1, 1 58 sll t0, t1, t0 59 nor t0, t0, zero /* mask with core id bit clear */ 60 61 /* clear CPU non-coherent bit */ 62 li t2, XLP_DEFAULT_IO_BASE_KSEG1 + XLP_IO_SYS_OFFSET(0) + XLP_SYS_CPU_NONCOHERENT_MODE_REG * 4 63 lw t1, 0(t2) 64 and t1, t1, t0 65 sw t1, 0(t2) 66 lw t1, 0(t2) /* read-back ensures operation complete */ 67 sync 68 69 dla t2, mpentry 70 jr t2 71 nop 72#endif 73 nop 74 /* NOT REACHED */ 75VECTOR_END(XLPResetEntry) 76 77 78 /* Not yet */ 79nmi_handler: 80 nop 81 nop 82 j nmi_handler 83 84#ifdef SMP 85 /* 86 * Enable other threads in the core, called from thread 0 87 * of the core 88 */ 89LEAF(xlp_enable_threads) 90 /* 91 * Save and restore callee saved registers of all ABIs 92 * Enabling threads trashes the registers 93 */ 94 dmtc0 sp, $4, 2 /* SP saved in UserLocal */ 95 ori sp, sp, 0x7 96 xori sp, sp, 0x7 /* align 64 bit */ 97 addiu sp, sp, -128 98 mfc0 t1, MIPS_COP_0_STATUS 99 sd s0, 0(sp) 100 sd s1, 8(sp) 101 sd s2, 16(sp) 102 sd s3, 24(sp) 103 sd s4, 32(sp) 104 sd s5, 40(sp) 105 sd s6, 48(sp) 106 sd s7, 56(sp) 107 sd s8, 64(sp) 108 sd t1, 72(sp) 109 sd gp, 80(sp) 110 sd ra, 88(sp) 111 /* Use register number to work in o32 and n32 */ 112 li $9, ((XLP_CPU_BLOCKID_MAP << 8) | XLP_BLKID_MAP_THREADMODE) 113 move $8, a0 114 sync 115 .word 0x71280019 /* mtcr t0, t1*/ 116 mfc0 t0, MIPS_COP_0_PRID, 1 117 andi t0, 0x3 118 beqz t0, 2f 119 nop 120 dla t1, mpentry /* child thread, go to hardware init */ 121 jr t1 122 nop 123 124 1252: /* 126 * Parent hardware thread, restore registers, return 127 */ 128#if 1 129 /* 130 * A0 Errata - Write MMU_SETUP after changing thread mode register. 131 */ 132 li $9, 0x400 133 li $8, 0 134 .word 0x71280019 /* mtcr $8, $9*/ 135 .word 0x000000c0 /* ehb */ 136#endif 137 dmfc0 t0, $4, 2 /* SP saved in UserLocal */ 138 ori sp, t0, 0x7 139 xori sp, sp, 0x7 /* align 64 bit */ 140 addiu sp, sp, -128 141 ld s0, 0(sp) 142 ld s1, 8(sp) 143 ld s2, 16(sp) 144 ld s3, 24(sp) 145 ld s4, 32(sp) 146 ld s5, 40(sp) 147 ld s6, 48(sp) 148 ld s7, 56(sp) 149 ld s8, 64(sp) 150 ld t1, 72(sp) 151 ld gp, 80(sp) 152 ld ra, 88(sp) 153 mfc0 t1, MIPS_COP_0_STATUS 154 155 move sp, t0 /* Restore the real SP */ 156 jr ra 157 nop 158END(xlp_enable_threads) 159#endif 160