sys.h revision 285830
11541Srgrimes/*- 21541Srgrimes * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 31541Srgrimes * reserved. 41541Srgrimes * 51541Srgrimes * Redistribution and use in source and binary forms, with or without 61541Srgrimes * modification, are permitted provided that the following conditions are 71541Srgrimes * met: 81541Srgrimes * 91541Srgrimes * 1. Redistributions of source code must retain the above copyright 101541Srgrimes * notice, this list of conditions and the following disclaimer. 111541Srgrimes * 2. Redistributions in binary form must reproduce the above copyright 121541Srgrimes * notice, this list of conditions and the following disclaimer in 131541Srgrimes * the documentation and/or other materials provided with the 141541Srgrimes * distribution. 151541Srgrimes * 161541Srgrimes * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 171541Srgrimes * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181541Srgrimes * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 191541Srgrimes * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 201541Srgrimes * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 211541Srgrimes * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 221541Srgrimes * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 231541Srgrimes * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 241541Srgrimes * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 251541Srgrimes * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 261541Srgrimes * THE POSSIBILITY OF SUCH DAMAGE. 271541Srgrimes * 281541Srgrimes * NETLOGIC_BSD 291541Srgrimes * $FreeBSD: releng/10.2/sys/mips/nlm/hal/sys.h 255368 2013-09-07 18:26:16Z jchandra $ 301541Srgrimes */ 311541Srgrimes 321541Srgrimes#ifndef __NLM_HAL_SYS_H__ 331541Srgrimes#define __NLM_HAL_SYS_H__ 3442957Sdillon 351541Srgrimes/** 361541Srgrimes* @file_name sys.h 371541Srgrimes* @author Netlogic Microsystems 381541Srgrimes* @brief HAL for System configuration registers 391541Srgrimes*/ 401541Srgrimes#define SYS_CHIP_RESET 0x00 4134924Sbde#define SYS_POWER_ON_RESET_CFG 0x01 4212662Sdg#define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 4312662Sdg#define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 441541Srgrimes#define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 4540794Speter#define SYS_EFUSE_DEVICE_CFG3 0x05 4640794Speter#define SYS_EFUSE_DEVICE_CFG4 0x06 4712726Sbde#define SYS_EFUSE_DEVICE_CFG5 0x07 4812662Sdg#define SYS_EFUSE_DEVICE_CFG6 0x08 4922521Sdyson#define SYS_EFUSE_DEVICE_CFG7 0x09 5012662Sdg#define SYS_PLL_CTRL 0x0a 5112662Sdg#define SYS_CPU_RESET 0x0b 5212662Sdg#define SYS_CPU_NONCOHERENT_MODE 0x0d 531541Srgrimes#define SYS_CORE_DFS_DIS_CTRL 0x0e 541541Srgrimes#define SYS_CORE_DFS_RST_CTRL 0x0f 5512623Sphk#define SYS_CORE_DFS_BYP_CTRL 0x10 5612623Sphk#define SYS_CORE_DFS_PHA_CTRL 0x11 5712623Sphk#define SYS_CORE_DFS_DIV_INC_CTRL 0x12 589759Sbde#define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 591541Srgrimes#define SYS_CORE_DFS_DIV_VALUE 0x14 6012820Sphk#define SYS_RESET 0x15 611541Srgrimes#define SYS_DFS_DIS_CTRL 0x16 621541Srgrimes#define SYS_DFS_RST_CTRL 0x17 631541Srgrimes#define SYS_DFS_BYP_CTRL 0x18 641541Srgrimes#define SYS_DFS_DIV_INC_CTRL 0x19 651541Srgrimes#define SYS_DFS_DIV_DEC_CTRL 0x1a 6612820Sphk#define SYS_DFS_DIV_VALUE0 0x1b 671541Srgrimes#define SYS_DFS_DIV_VALUE1 0x1c 681541Srgrimes#define SYS_SENSE_AMP_DLY 0x1d 691541Srgrimes#define SYS_SOC_SENSE_AMP_DLY 0x1e 701541Srgrimes#define SYS_CTRL0 0x1f 711541Srgrimes#define SYS_CTRL1 0x20 721541Srgrimes#define SYS_TIMEOUT_BS1 0x21 731541Srgrimes#define SYS_BYTE_SWAP 0x22 741541Srgrimes#define SYS_VRM_VID 0x23 751541Srgrimes#define SYS_PWR_RAM_CMD 0x24 769507Sdg#define SYS_PWR_RAM_ADDR 0x25 7712286Sphk#define SYS_PWR_RAM_DATA0 0x26 781541Srgrimes#define SYS_PWR_RAM_DATA1 0x27 791541Srgrimes#define SYS_PWR_RAM_DATA2 0x28 801541Srgrimes#define SYS_PWR_UCODE 0x29 811541Srgrimes#define SYS_CPU0_PWR_STATUS 0x2a 8214531Shsu#define SYS_CPU1_PWR_STATUS 0x2b 831541Srgrimes#define SYS_CPU2_PWR_STATUS 0x2c 841541Srgrimes#define SYS_CPU3_PWR_STATUS 0x2d 851541Srgrimes#define SYS_CPU4_PWR_STATUS 0x2e 861541Srgrimes#define SYS_CPU5_PWR_STATUS 0x2f 871541Srgrimes#define SYS_CPU6_PWR_STATUS 0x30 881541Srgrimes#define SYS_CPU7_PWR_STATUS 0x31 891541Srgrimes#define SYS_STATUS 0x32 901541Srgrimes#define SYS_INT_POL 0x33 911541Srgrimes#define SYS_INT_TYPE 0x34 921541Srgrimes#define SYS_INT_STATUS 0x35 931541Srgrimes#define SYS_INT_MASK0 0x36 941541Srgrimes#define SYS_INT_MASK1 0x37 955455Sdg#define SYS_UCO_S_ECC 0x38 961541Srgrimes#define SYS_UCO_M_ECC 0x39 971541Srgrimes#define SYS_UCO_ADDR 0x3a 989507Sdg#define SYS_PLL_DFS_BYP_CTRL 0x3a /* Bx stepping */ 999507Sdg#define SYS_UCO_INSTR 0x3b 1009507Sdg#define SYS_MEM_BIST0 0x3c 1019507Sdg#define SYS_MEM_BIST1 0x3d 10234961Sphk#define SYS_PLL_DFS_DIV_VALUE 0x3d /* Bx stepping */ 1039507Sdg#define SYS_MEM_BIST2 0x3e 1049507Sdg#define SYS_MEM_BIST3 0x3f 1059507Sdg#define SYS_MEM_BIST4 0x40 1069507Sdg#define SYS_MEM_BIST5 0x41 1079507Sdg#define SYS_MEM_BIST6 0x42 10812286Sphk#define SYS_MEM_BIST7 0x43 10912286Sphk#define SYS_MEM_BIST8 0x44 11012286Sphk#define SYS_MEM_BIST9 0x45 11112286Sphk#define SYS_MEM_BIST10 0x46 11212286Sphk#define SYS_MEM_BIST11 0x47 11312286Sphk#define SYS_MEM_BIST12 0x48 11412286Sphk#define SYS_SCRTCH0 0x49 11512286Sphk#define SYS_SCRTCH1 0x4a 11612286Sphk#define SYS_SCRTCH2 0x4b 11712286Sphk#define SYS_SCRTCH3 0x4c 11812286Sphk 11912286Sphk#if !defined(LOCORE) && !defined(__ASSEMBLY__) 12012286Sphk 12112286Sphk#define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) 12212286Sphk#define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) 12312623Sphk#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) 1241541Srgrimes#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) 12512286Sphk 12612286Sphkenum { 1271541Srgrimes /* Don't change order and it must start from zero */ 12812286Sphk DFS_DEVICE_NAE = 0, 12912286Sphk DFS_DEVICE_SAE, 13012286Sphk DFS_DEVICE_RSA, 13112286Sphk DFS_DEVICE_DTRE, 13212286Sphk DFS_DEVICE_CMP, 1331541Srgrimes DFS_DEVICE_KBP, 1341541Srgrimes DFS_DEVICE_DMC, 13512286Sphk DFS_DEVICE_NAND, 1361541Srgrimes DFS_DEVICE_MMC, 1371541Srgrimes DFS_DEVICE_NOR, 1381541Srgrimes DFS_DEVICE_CORE, 1391541Srgrimes DFS_DEVICE_REGEX_SLOW, 14015809Sdyson DFS_DEVICE_REGEX_FAST, 1415455Sdg DFS_DEVICE_SATA, 14215809Sdyson INVALID_DFS_DEVICE = 0xFF 14338517Sdfr}; 1441541Srgrimes 1451541Srgrimesstatic __inline 1461541Srgrimesvoid nlm_sys_enable_block(uint64_t sys_base, int block) 14714531Shsu{ 1481541Srgrimes uint32_t dfsdis, mask; 1491541Srgrimes 1501541Srgrimes mask = 1 << block; 1511541Srgrimes dfsdis = nlm_read_sys_reg(sys_base, SYS_DFS_DIS_CTRL); 1521541Srgrimes if ((dfsdis & mask) == 0) 1531541Srgrimes return; /* already enabled, nothing to do */ 1541541Srgrimes dfsdis &= ~mask; 1551541Srgrimes nlm_write_sys_reg(sys_base, SYS_DFS_DIS_CTRL, dfsdis); 1561541Srgrimes} 1571541Srgrimes 1581541Srgrimes#endif 1591541Srgrimes#endif 1601541Srgrimes