mips-extns.h revision 225394
11769Sjkh/*- 21769Sjkh * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 31769Sjkh * reserved. 41769Sjkh * 51769Sjkh * Redistribution and use in source and binary forms, with or without 61769Sjkh * modification, are permitted provided that the following conditions are 71769Sjkh * met: 81769Sjkh * 91769Sjkh * 1. Redistributions of source code must retain the above copyright 101769Sjkh * notice, this list of conditions and the following disclaimer. 111769Sjkh * 2. Redistributions in binary form must reproduce the above copyright 121769Sjkh * notice, this list of conditions and the following disclaimer in 131769Sjkh * the documentation and/or other materials provided with the 141769Sjkh * distribution. 151769Sjkh * 161769Sjkh * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 171769Sjkh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 181769Sjkh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 191769Sjkh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 201769Sjkh * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 211769Sjkh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 221769Sjkh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 231769Sjkh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 241769Sjkh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 251769Sjkh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 261769Sjkh * THE POSSIBILITY OF SUCH DAMAGE. 271769Sjkh * 281769Sjkh * NETLOGIC_BSD 291769Sjkh * $FreeBSD: head/sys/mips/nlm/hal/mips-extns.h 225394 2011-09-05 10:45:29Z jchandra $ 301769Sjkh */ 311769Sjkh 321769Sjkh#ifndef __NLM_MIPS_EXTNS_H__ 331769Sjkh#define __NLM_MIPS_EXTNS_H__ 341769Sjkh 351769Sjkh#if !defined(LOCORE) && !defined(__ASSEMBLY__) 363120Sachestatic __inline__ int32_t nlm_swapw(int32_t *loc, int32_t val) 373120Sache{ 383120Sache int32_t oldval = 0; 393120Sache 403120Sache __asm__ __volatile__ ( 413120Sache ".set push\n" 423120Sache ".set noreorder\n" 433120Sache "move $9, %2\n" 443120Sache "move $8, %3\n" 453120Sache ".word 0x71280014\n" /* "swapw $8, $9\n" */ 461769Sjkh "move %1, $8\n" 473120Sache ".set pop\n" 483120Sache : "+m" (*loc), "=r" (oldval) 491769Sjkh : "r" (loc), "r" (val) 501769Sjkh : "$8", "$9" ); 513120Sache 523132Sache return oldval; 533120Sache} 543120Sache 553120Sachestatic __inline__ uint32_t nlm_swapwu(int32_t *loc, uint32_t val) 563132Sache{ 573132Sache uint32_t oldval; 583132Sache 593132Sache __asm__ __volatile__ ( 603132Sache ".set push\n" 613132Sache ".set noreorder\n" 623132Sache "move $9, %2\n" 631769Sjkh "move $8, %3\n" 641769Sjkh ".word 0x71280015\n" /* "swapwu $8, $9\n" */ 651769Sjkh "move %1, $8\n" 661769Sjkh ".set pop\n" 671769Sjkh : "+m" (*loc), "=r" (oldval) 681769Sjkh : "r" (loc), "r" (val) 691769Sjkh : "$8", "$9" ); 701769Sjkh 711769Sjkh return oldval; 721769Sjkh} 731769Sjkh 741769Sjkh#if (__mips == 64) 751769Sjkhstatic __inline__ uint64_t nlm_swapd(int32_t *loc, uint64_t val) 761769Sjkh{ 771769Sjkh uint64_t oldval; 781769Sjkh 791769Sjkh __asm__ __volatile__ ( 801769Sjkh ".set push\n" 811769Sjkh ".set noreorder\n" 821769Sjkh "move $9, %2\n" 831769Sjkh "move $8, %3\n" 841769Sjkh ".word 0x71280014\n" /* "swapw $8, $9\n" */ 851769Sjkh "move %1, $8\n" 863120Sache ".set pop\n" 871769Sjkh : "+m" (*loc), "=r" (oldval) 883120Sache : "r" (loc), "r" (val) 893120Sache : "$8", "$9" ); 901769Sjkh 911769Sjkh return oldval; 921769Sjkh} 931769Sjkh#endif 941769Sjkh 951769Sjkh/* 961769Sjkh * Atomic increment a unsigned int 973120Sache */ 983120Sachestatic __inline unsigned int 991769Sjkhnlm_ldaddwu(unsigned int value, unsigned int *addr) 1003120Sache{ 1011769Sjkh __asm__ __volatile__( 1021769Sjkh ".set push\n" 1031769Sjkh ".set noreorder\n" 1041769Sjkh "move $8, %2\n" 1051769Sjkh "move $9, %3\n" 1061769Sjkh ".word 0x71280011\n" /* ldaddwu $8, $9 */ 1071769Sjkh "move %0, $8\n" 1081769Sjkh ".set pop\n" 1091769Sjkh : "=&r"(value), "+m"(*addr) 1101769Sjkh : "0"(value), "r" ((unsigned long)addr) 1111769Sjkh : "$8", "$9"); 1121769Sjkh 1131769Sjkh return (value); 1143120Sache} 1153120Sache/* 1161769Sjkh * 32 bit read write for c0 1171769Sjkh */ 1181769Sjkh#define read_c0_register32(reg, sel) \ 1191769Sjkh({ \ 1201769Sjkh uint32_t __rv; \ 1211769Sjkh __asm__ __volatile__( \ 1221769Sjkh ".set push\n\t" \ 1231769Sjkh ".set mips32\n\t" \ 1241769Sjkh "mfc0 %0, $%1, %2\n\t" \ 1251769Sjkh ".set pop\n" \ 1263120Sache : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 1271769Sjkh __rv; \ 1281769Sjkh }) 1291769Sjkh 1301769Sjkh#define write_c0_register32(reg, sel, value) \ 1311769Sjkh __asm__ __volatile__( \ 1321769Sjkh ".set push\n\t" \ 1331769Sjkh ".set mips32\n\t" \ 1341769Sjkh "mtc0 %0, $%1, %2\n\t" \ 1351769Sjkh ".set pop\n" \ 1361769Sjkh : : "r" (value), "i" (reg), "i" (sel) ); 1371769Sjkh 1381769Sjkh#if defined(__mips_n64) || defined(__mips_n32) 1393120Sache/* 1403120Sache * On 64 bit compilation, the operations are simple 1411769Sjkh */ 1421769Sjkh#define read_c0_register64(reg, sel) \ 1431769Sjkh({ \ 1441769Sjkh uint64_t __rv; \ 1451769Sjkh __asm__ __volatile__( \ 1461769Sjkh ".set push\n\t" \ 1471769Sjkh ".set mips64\n\t" \ 1481769Sjkh "dmfc0 %0, $%1, %2\n\t" \ 1493120Sache ".set pop\n" \ 1503120Sache : "=r" (__rv) : "i" (reg), "i" (sel) ); \ 151 __rv; \ 152 }) 153 154#define write_c0_register64(reg, sel, value) \ 155 __asm__ __volatile__( \ 156 ".set push\n\t" \ 157 ".set mips64\n\t" \ 158 "dmtc0 %0, $%1, %2\n\t" \ 159 ".set pop\n" \ 160 : : "r" (value), "i" (reg), "i" (sel) ); 161#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ 162 163/* 164 * 32 bit compilation, 64 bit values has to split 165 */ 166#define read_c0_register64(reg, sel) \ 167({ \ 168 uint32_t __high, __low; \ 169 __asm__ __volatile__( \ 170 ".set push\n\t" \ 171 ".set noreorder\n\t" \ 172 ".set mips64\n\t" \ 173 "dmfc0 $8, $%2, %3\n\t" \ 174 "dsra32 %0, $8, 0\n\t" \ 175 "sll %1, $8, 0\n\t" \ 176 ".set pop\n" \ 177 : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ 178 : "$8"); \ 179 ((uint64_t)__high << 32) | __low; \ 180}) 181 182#define write_c0_register64(reg, sel, value) \ 183do { \ 184 uint32_t __high = value >> 32; \ 185 uint32_t __low = value & 0xffffffff; \ 186 __asm__ __volatile__( \ 187 ".set push\n\t" \ 188 ".set noreorder\n\t" \ 189 ".set mips64\n\t" \ 190 "dsll32 $8, %1, 0\n\t" \ 191 "dsll32 $9, %0, 0\n\t" \ 192 "dsrl32 $8, $8, 0\n\t" \ 193 "or $8, $8, $9\n\t" \ 194 "dmtc0 $8, $%2, %3\n\t" \ 195 ".set pop" \ 196 :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \ 197 :"$8", "$9"); \ 198} while(0) 199 200#endif 201/* functions to write to and read from the extended 202 * cp0 registers. 203 * EIRR : Extended Interrupt Request Register 204 * cp0 register 9 sel 6 205 * bits 0...7 are same as cause register 8...15 206 * EIMR : Extended Interrupt Mask Register 207 * cp0 register 9 sel 7 208 * bits 0...7 are same as status register 8...15 209 */ 210static __inline uint64_t 211nlm_read_c0_eirr(void) 212{ 213 214 return (read_c0_register64(9, 6)); 215} 216 217static __inline void 218nlm_write_c0_eirr(uint64_t val) 219{ 220 221 write_c0_register64(9, 6, val); 222} 223 224static __inline uint64_t 225nlm_read_c0_eimr(void) 226{ 227 228 return (read_c0_register64(9, 7)); 229} 230 231static __inline void 232nlm_write_c0_eimr(uint64_t val) 233{ 234 235 write_c0_register64(9, 7, val); 236} 237 238static __inline__ uint32_t 239nlm_read_c0_ebase(void) 240{ 241 242 return (read_c0_register32(15, 1)); 243} 244 245static __inline__ int 246nlm_nodeid(void) 247{ 248 return (nlm_read_c0_ebase() >> 5) & 0x3; 249} 250 251static __inline__ int 252nlm_cpuid(void) 253{ 254 return nlm_read_c0_ebase() & 0x1f; 255} 256 257static __inline__ int 258nlm_threadid(void) 259{ 260 return nlm_read_c0_ebase() & 0x3; 261} 262 263static __inline__ int 264nlm_coreid(void) 265{ 266 return (nlm_read_c0_ebase() >> 2) & 0x7; 267} 268#endif 269 270#define XLP_MAX_NODES 4 271#define XLP_MAX_CORES 8 272#define XLP_MAX_THREADS 4 273 274#endif 275